blob: 05138326f0a572f45122f5ee425089f945fdc656 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2020 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
6 */
7
8#include <dt-bindings/clock/imx8-clock.h>
9#include <dt-bindings/clock/imx8-lpcg.h>
10#include <dt-bindings/firmware/imx/rsrc.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/pinctrl/pads-imx8qxp.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 ethernet0 = &fec1;
24 ethernet1 = &fec2;
25 gpio0 = &lsio_gpio0;
26 gpio1 = &lsio_gpio1;
27 gpio2 = &lsio_gpio2;
28 gpio3 = &lsio_gpio3;
29 gpio4 = &lsio_gpio4;
30 gpio5 = &lsio_gpio5;
31 gpio6 = &lsio_gpio6;
32 gpio7 = &lsio_gpio7;
33 i2c0 = &i2c0;
34 i2c1 = &i2c1;
35 i2c2 = &i2c2;
36 i2c3 = &i2c3;
37 mmc0 = &usdhc1;
38 mmc1 = &usdhc2;
39 mmc2 = &usdhc3;
40 mu0 = &lsio_mu0;
41 mu1 = &lsio_mu1;
42 mu2 = &lsio_mu2;
43 mu3 = &lsio_mu3;
44 mu4 = &lsio_mu4;
45 serial0 = &lpuart0;
46 serial1 = &lpuart1;
47 serial2 = &lpuart2;
48 serial3 = &lpuart3;
Tom Rini844493d2025-01-26 16:17:47 -060049 spi0 = &lpspi0;
50 spi1 = &lpspi1;
51 spi2 = &lpspi2;
52 spi3 = &lpspi3;
Tom Rini53633a82024-02-29 12:33:36 -050053 vpu-core0 = &vpu_core0;
54 vpu-core1 = &vpu_core1;
Tom Rini53633a82024-02-29 12:33:36 -050055 };
56
57 cpus {
58 #address-cells = <2>;
59 #size-cells = <0>;
60
61 /* We have 1 clusters with 4 Cortex-A35 cores */
62 A35_0: cpu@0 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a35";
65 reg = <0x0 0x0>;
66 enable-method = "psci";
67 i-cache-size = <0x8000>;
68 i-cache-line-size = <64>;
69 i-cache-sets = <256>;
70 d-cache-size = <0x8000>;
71 d-cache-line-size = <64>;
72 d-cache-sets = <128>;
73 next-level-cache = <&A35_L2>;
74 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
75 operating-points-v2 = <&a35_opp_table>;
76 #cooling-cells = <2>;
77 };
78
79 A35_1: cpu@1 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a35";
82 reg = <0x0 0x1>;
83 enable-method = "psci";
84 i-cache-size = <0x8000>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <256>;
87 d-cache-size = <0x8000>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <128>;
90 next-level-cache = <&A35_L2>;
91 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
92 operating-points-v2 = <&a35_opp_table>;
93 #cooling-cells = <2>;
94 };
95
96 A35_2: cpu@2 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a35";
99 reg = <0x0 0x2>;
100 enable-method = "psci";
101 i-cache-size = <0x8000>;
102 i-cache-line-size = <64>;
103 i-cache-sets = <256>;
104 d-cache-size = <0x8000>;
105 d-cache-line-size = <64>;
106 d-cache-sets = <128>;
107 next-level-cache = <&A35_L2>;
108 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
109 operating-points-v2 = <&a35_opp_table>;
110 #cooling-cells = <2>;
111 };
112
113 A35_3: cpu@3 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a35";
116 reg = <0x0 0x3>;
117 enable-method = "psci";
118 i-cache-size = <0x8000>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <0x8000>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <128>;
124 next-level-cache = <&A35_L2>;
125 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
126 operating-points-v2 = <&a35_opp_table>;
127 #cooling-cells = <2>;
128 };
129
130 A35_L2: l2-cache0 {
131 compatible = "cache";
132 cache-level = <2>;
133 cache-unified;
134 cache-size = <0x80000>;
135 cache-line-size = <64>;
136 cache-sets = <1024>;
137 };
138 };
139
140 a35_opp_table: opp-table {
141 compatible = "operating-points-v2";
142 opp-shared;
143
144 opp-900000000 {
145 opp-hz = /bits/ 64 <900000000>;
146 opp-microvolt = <1000000>;
147 clock-latency-ns = <150000>;
148 };
149
150 opp-1200000000 {
151 opp-hz = /bits/ 64 <1200000000>;
152 opp-microvolt = <1100000>;
153 clock-latency-ns = <150000>;
154 opp-suspend;
155 };
156 };
157
158 gic: interrupt-controller@51a00000 {
159 compatible = "arm,gic-v3";
160 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
161 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
162 #interrupt-cells = <3>;
163 interrupt-controller;
164 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
165 };
166
167 reserved-memory {
168 #address-cells = <2>;
169 #size-cells = <2>;
170 ranges;
171
172 decoder_boot: decoder-boot@84000000 {
173 reg = <0 0x84000000 0 0x2000000>;
174 no-map;
175 };
176
177 encoder_boot: encoder-boot@86000000 {
178 reg = <0 0x86000000 0 0x200000>;
179 no-map;
180 };
181
182 decoder_rpc: decoder-rpc@92000000 {
183 reg = <0 0x92000000 0 0x100000>;
184 no-map;
185 };
186
187 dsp_reserved: dsp@92400000 {
188 reg = <0 0x92400000 0 0x2000000>;
189 no-map;
Tom Rini93743d22024-04-01 09:08:13 -0400190 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500191 };
192
193 encoder_rpc: encoder-rpc@94400000 {
194 reg = <0 0x94400000 0 0x700000>;
195 no-map;
196 };
197 };
198
199 pmu {
200 compatible = "arm,cortex-a35-pmu";
201 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
202 };
203
204 psci {
205 compatible = "arm,psci-1.0";
206 method = "smc";
207 };
208
209 system-controller {
210 compatible = "fsl,imx-scu";
211 mbox-names = "tx0",
212 "rx0",
213 "gip3";
214 mboxes = <&lsio_mu1 0 0
215 &lsio_mu1 1 0
216 &lsio_mu1 3 3>;
217
218 pd: power-controller {
219 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
220 #power-domain-cells = <1>;
221 };
222
223 clk: clock-controller {
224 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
225 #clock-cells = <2>;
226 };
227
228 iomuxc: pinctrl {
229 compatible = "fsl,imx8qxp-iomuxc";
230 };
231
232 ocotp: ocotp {
233 compatible = "fsl,imx8qxp-scu-ocotp";
234 #address-cells = <1>;
235 #size-cells = <1>;
236 };
237
238 scu_key: keys {
239 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
240 linux,keycodes = <KEY_POWER>;
241 status = "disabled";
242 };
243
244 rtc: rtc {
245 compatible = "fsl,imx8qxp-sc-rtc";
246 };
247
248 watchdog {
249 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
250 timeout-sec = <60>;
251 };
252
253 tsens: thermal-sensor {
254 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
255 #thermal-sensor-cells = <1>;
256 };
257 };
258
259 timer {
260 compatible = "arm,armv8-timer";
261 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
262 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
263 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
264 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
265 };
266
Tom Rini6bb92fc2024-05-20 09:54:58 -0600267 clk_dummy: clock-dummy {
268 compatible = "fixed-clock";
269 #clock-cells = <0>;
270 clock-frequency = <0>;
271 clock-output-names = "clk_dummy";
272 };
273
Tom Rini53633a82024-02-29 12:33:36 -0500274 xtal32k: clock-xtal32k {
275 compatible = "fixed-clock";
276 #clock-cells = <0>;
277 clock-frequency = <32768>;
278 clock-output-names = "xtal_32KHz";
279 };
280
281 xtal24m: clock-xtal24m {
282 compatible = "fixed-clock";
283 #clock-cells = <0>;
284 clock-frequency = <24000000>;
285 clock-output-names = "xtal_24MHz";
286 };
287
288 thermal_zones: thermal-zones {
289 cpu0-thermal {
290 polling-delay-passive = <250>;
291 polling-delay = <2000>;
292 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
293
294 trips {
295 cpu_alert0: trip0 {
296 temperature = <107000>;
297 hysteresis = <2000>;
298 type = "passive";
299 };
300
301 cpu_crit0: trip1 {
302 temperature = <127000>;
303 hysteresis = <2000>;
304 type = "critical";
305 };
306 };
307
308 cooling-maps {
309 map0 {
310 trip = <&cpu_alert0>;
311 cooling-device =
312 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
313 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
314 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
315 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
316 };
317 };
318 };
319 };
320
321 /* sorted in register address */
322 #include "imx8-ss-img.dtsi"
323 #include "imx8-ss-vpu.dtsi"
Tom Rini762f85b2024-07-20 11:15:10 -0600324 #include "imx8-ss-cm40.dtsi"
Tom Rini6bb92fc2024-05-20 09:54:58 -0600325 #include "imx8-ss-gpu0.dtsi"
Tom Rini53633a82024-02-29 12:33:36 -0500326 #include "imx8-ss-adma.dtsi"
327 #include "imx8-ss-conn.dtsi"
328 #include "imx8-ss-ddr.dtsi"
329 #include "imx8-ss-lsio.dtsi"
Tom Rini844493d2025-01-26 16:17:47 -0600330 #include "imx8-ss-hsio.dtsi"
Tom Rini53633a82024-02-29 12:33:36 -0500331};
332
333#include "imx8qxp-ss-img.dtsi"
Tom Rini93743d22024-04-01 09:08:13 -0400334#include "imx8qxp-ss-vpu.dtsi"
Tom Rini53633a82024-02-29 12:33:36 -0500335#include "imx8qxp-ss-adma.dtsi"
336#include "imx8qxp-ss-conn.dtsi"
337#include "imx8qxp-ss-lsio.dtsi"
Tom Rini844493d2025-01-26 16:17:47 -0600338#include "imx8qxp-ss-hsio.dtsi"