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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / dts / upstream / src / arm64 / freescale / imx8mp-navqp.dts
blob: 4a4f7c1adc23fe2615d8eb4904d795b46af4ca9f [file] [log] [blame]
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Emcraft Systems
4 * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/leds/common.h>
11#include "imx8mp.dtsi"
12
13/ {
14 model = "Emcraft Systems i.MX8MPlus NavQ+ Kit";
15 compatible = "emcraft,imx8mp-navqp", "fsl,imx8mp";
16
17 chosen {
18 stdout-path = &uart2;
19 };
20
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]21 hdmi-connector {
22 compatible = "hdmi-connector";
23 label = "J15";
24 type = "d";
25
26 port {
27 hdmi_connector_in: endpoint {
28 remote-endpoint = <&hdmi_tx_out>;
29 };
30 };
31 };
32
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]33 leds {
34 compatible = "gpio-leds";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_gpio_led>;
37
38 led-0 {
39 color = <LED_COLOR_ID_GREEN>;
40 function = LED_FUNCTION_STATUS;
41 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
42 default-state = "on";
43 };
44 };
45
46 reg_usdhc2_vmmc: regulator-usdhc2 {
47 compatible = "regulator-fixed";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
50 regulator-name = "VSD_3V3";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
54 enable-active-high;
55 startup-delay-us = <100>;
56 off-on-delay-us = <12000>;
57 };
58};
59
60&A53_0 {
61 cpu-supply = <&buck2>;
62};
63
64&A53_1 {
65 cpu-supply = <&buck2>;
66};
67
68&A53_2 {
69 cpu-supply = <&buck2>;
70};
71
72&A53_3 {
73 cpu-supply = <&buck2>;
74};
75
76&eqos {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_eqos>;
79 phy-mode = "rgmii-id";
80 phy-handle = <&ethphy0>;
81 status = "okay";
82
83 mdio {
84 compatible = "snps,dwmac-mdio";
85 #address-cells = <1>;
86 #size-cells = <0>;
87
88 ethphy0: ethernet-phy@0 {
89 compatible = "ethernet-phy-ieee802.3-c22";
90 reg = <0>;
91 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
92 reset-assert-us = <1000>;
93 reset-deassert-us = <10000>;
94 qca,disable-smarteee;
95 qca,disable-hibernation-mode;
96 };
97 };
98};
99
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]100&hdmi_pvi {
101 status = "okay";
102};
103
104&hdmi_tx {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_hdmi>;
107 status = "okay";
108
109 ports {
110 port@1 {
111 hdmi_tx_out: endpoint {
112 remote-endpoint = <&hdmi_connector_in>;
113 };
114 };
115 };
116};
117
118&hdmi_tx_phy {
119 status = "okay";
120};
121
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]122&i2c1 {
123 clock-frequency = <400000>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c1>;
126 status = "okay";
127
128 pmic@25 {
129 compatible = "nxp,pca9450c";
130 reg = <0x25>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_pmic>;
133 interrupt-parent = <&gpio1>;
134 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
135
136 regulators {
137 BUCK1 {
138 regulator-name = "BUCK1";
139 regulator-min-microvolt = <600000>;
140 regulator-max-microvolt = <2187500>;
141 regulator-boot-on;
142 regulator-always-on;
143 regulator-ramp-delay = <3125>;
144 };
145
146 buck2: BUCK2 {
147 regulator-name = "BUCK2";
148 regulator-min-microvolt = <600000>;
149 regulator-max-microvolt = <2187500>;
150 regulator-boot-on;
151 regulator-always-on;
152 regulator-ramp-delay = <3125>;
153 nxp,dvs-run-voltage = <950000>;
154 nxp,dvs-standby-voltage = <850000>;
155 };
156
157 BUCK4 {
158 regulator-name = "BUCK4";
159 regulator-min-microvolt = <600000>;
160 regulator-max-microvolt = <3400000>;
161 regulator-boot-on;
162 regulator-always-on;
163 };
164
165 BUCK5 {
166 regulator-name = "BUCK5";
167 regulator-min-microvolt = <600000>;
168 regulator-max-microvolt = <3400000>;
169 regulator-boot-on;
170 regulator-always-on;
171 };
172
173 BUCK6 {
174 regulator-name = "BUCK6";
175 regulator-min-microvolt = <600000>;
176 regulator-max-microvolt = <3400000>;
177 regulator-boot-on;
178 regulator-always-on;
179 };
180
181 LDO1 {
182 regulator-name = "LDO1";
183 regulator-min-microvolt = <1600000>;
184 regulator-max-microvolt = <3300000>;
185 regulator-boot-on;
186 regulator-always-on;
187 };
188
189 LDO2 {
190 regulator-name = "LDO2";
191 regulator-min-microvolt = <800000>;
192 regulator-max-microvolt = <1150000>;
193 regulator-boot-on;
194 regulator-always-on;
195 };
196
197 LDO3 {
198 regulator-name = "LDO3";
199 regulator-min-microvolt = <800000>;
200 regulator-max-microvolt = <3300000>;
201 regulator-boot-on;
202 regulator-always-on;
203 };
204
205 LDO4 {
206 regulator-name = "LDO4";
207 regulator-min-microvolt = <800000>;
208 regulator-max-microvolt = <3300000>;
209 regulator-boot-on;
210 regulator-always-on;
211 };
212
213 LDO5 {
214 regulator-name = "LDO5";
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <3300000>;
217 regulator-boot-on;
218 regulator-always-on;
219 };
220 };
221 };
222};
223
224&i2c2 {
225 clock-frequency = <400000>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_i2c2>;
228 status = "okay";
229};
230
231&i2c3 {
232 clock-frequency = <400000>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_i2c3>;
235 status = "okay";
236};
237
238&i2c4 {
239 clock-frequency = <400000>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_i2c4>;
242 status = "okay";
243
244 rtc@53 {
245 compatible = "nxp,pcf2131";
246 reg = <0x53>;
247 };
248};
249
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]250&lcdif3 {
251 status = "okay";
252};
253
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]254&uart2 {
255 /* console */
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_uart2>;
258 status = "okay";
259};
260
261/* SD Card */
262&usdhc2 {
263 pinctrl-names = "default", "state_100mhz", "state_200mhz";
264 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
265 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
266 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
267 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
268 vmmc-supply = <&reg_usdhc2_vmmc>;
269 bus-width = <4>;
270 status = "okay";
271};
272
273/* eMMC */
274&usdhc3 {
275 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
276 assigned-clock-rates = <400000000>;
277 pinctrl-names = "default", "state_100mhz", "state_200mhz";
278 pinctrl-0 = <&pinctrl_usdhc3>;
279 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
280 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
281 bus-width = <8>;
282 non-removable;
283 status = "okay";
284};
285
286&wdog1 {
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_wdog>;
289 fsl,ext-reset-output;
290 status = "okay";
291};
292
293&iomuxc {
294 pinctrl_eqos: eqosgrp {
295 fsl,pins = <
296 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
297 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
298 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
299 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
300 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
301 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
302 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
303 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
304 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
305 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
306 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
307 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
308 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
309 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
310 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x110
311 >;
312 };
313
314 pinctrl_gpio_led: gpioledgrp {
315 fsl,pins = <
316 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
317 >;
318 };
319
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]320 pinctrl_hdmi: hdmigrp {
321 fsl,pins = <
322 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
323 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
324 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10
325 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
326 >;
327 };
328
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]329 pinctrl_i2c1: i2c1grp {
330 fsl,pins = <
331 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
332 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
333 >;
334 };
335
336 pinctrl_i2c2: i2c2grp {
337 fsl,pins = <
338 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
339 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
340 >;
341 };
342
343 pinctrl_i2c3: i2c3grp {
344 fsl,pins = <
345 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
346 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
347 >;
348 };
349
350 pinctrl_i2c4: i2c4grp {
351 fsl,pins = <
352 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
353 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
354 >;
355 };
356
357 pinctrl_pmic: pmicgrp {
358 fsl,pins = <
359 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
360 >;
361 };
362
363 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
364 fsl,pins = <
365 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
366 >;
367 };
368
369 pinctrl_uart2: uart2grp {
370 fsl,pins = <
371 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
372 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
373 >;
374 };
375
376 pinctrl_usdhc2: usdhc2grp {
377 fsl,pins = <
378 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
379 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
380 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
381 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
382 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
383 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
384 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
385 >;
386 };
387
388 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
389 fsl,pins = <
390 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
391 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
392 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
393 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
394 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
395 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
396 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
397 >;
398 };
399
400 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
401 fsl,pins = <
402 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
403 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
404 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
405 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
406 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
407 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
408 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
409 >;
410 };
411
412 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
413 fsl,pins = <
414 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
415 >;
416 };
417
418 pinctrl_usdhc3: usdhc3grp {
419 fsl,pins = <
420 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
421 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
422 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
423 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
424 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
425 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
426 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
427 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
428 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
429 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
430 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
431 >;
432 };
433
434 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
435 fsl,pins = <
436 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
437 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
438 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
439 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
440 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
441 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
442 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
443 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
444 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
445 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
446 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
447 >;
448 };
449
450 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
451 fsl,pins = <
452 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
453 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
454 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
455 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
456 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
457 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
458 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
459 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
460 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
461 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
462 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
463 >;
464 };
465
466 pinctrl_wdog: wdoggrp {
467 fsl,pins = <
468 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
469 >;
470 };
471};