blob: 0eb9e726a9b8199499caf22740a388ab1f1c879d [file] [log] [blame]
Tom Rini844493d2025-01-26 16:17:47 -06001// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mp-kontron-osm-s.dtsi"
9
10/ {
11 model = "Kontron BL i.MX8MP OSM-S";
12 compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";
13
14 aliases {
15 ethernet0 = &fec;
16 ethernet1 = &eqos;
17 };
18
19 extcon_usbc: usbc {
20 compatible = "linux,extcon-usb-gpio";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_usb1_id>;
23 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 led1 {
30 label = "led1";
31 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
32 linux,default-trigger = "heartbeat";
33 };
34 };
35
36 pwm-beeper {
37 compatible = "pwm-beeper";
38 pwms = <&pwm2 0 5000 0>;
39 };
40
41 reg_vcc_panel: regulator-vcc-panel {
42 compatible = "regulator-fixed";
43 gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
44 enable-active-high;
45 regulator-max-microvolt = <3300000>;
46 regulator-min-microvolt = <3300000>;
47 regulator-name = "VCC_PANEL";
48 };
49};
50
51&ecspi2 {
52 status = "okay";
53
54 eeram@0 {
55 compatible = "microchip,48l640";
56 reg = <0>;
57 spi-max-frequency = <20000000>;
58 };
59};
60
61&eqos { /* Second ethernet (OSM-S ETH_B) */
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_eqos_rgmii>;
64 phy-mode = "rgmii-id";
65 phy-handle = <&ethphy1>;
66 status = "okay";
67
68 mdio {
69 compatible = "snps,dwmac-mdio";
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 ethphy1: ethernet-phy@1 {
74 compatible = "ethernet-phy-id4f51.e91b";
75 reg = <1>;
76 pinctrl-0 = <&pinctrl_ethphy1>;
77 pinctrl-names = "default";
78 reset-assert-us = <10000>;
79 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
80 };
81 };
82};
83
84&fec { /* First ethernet (OSM-S ETH_A) */
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_enet_rgmii>;
87 phy-connection-type = "rgmii-id";
88 phy-handle = <&ethphy0>;
89 status = "okay";
90
91 mdio {
92 #address-cells = <1>;
93 #size-cells = <0>;
94
95 ethphy0: ethernet-phy@1 {
96 compatible = "ethernet-phy-id4f51.e91b";
97 reg = <1>;
98 pinctrl-0 = <&pinctrl_ethphy0>;
99 pinctrl-names = "default";
100 reset-assert-us = <10000>;
101 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
102 };
103 };
104};
105
106&flexcan1 {
107 status = "okay";
108};
109
110/*
111 * Rename SoM signals according to board usage:
112 * SDIO_A_PWR_EN -> CAN_ADDR2
113 * SDIO_A_WP -> CAN_ADDR3
114 */
115&gpio2 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_gpio2>;
118 gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
119 "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
120 "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "CAN_ADDR2",
121 "CAN_ADDR3";
122};
123
124/*
125 * Rename SoM signals according to board usage:
126 * SPI_A_WP -> CAN_ADDR0
127 * SPI_A_HOLD -> CAN_ADDR1
128 * GPIO_B_0 -> DIO1_OUT
129 * GPIO_B_1 -> DIO2_OUT
130 */
131&gpio3 {
132 gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
133 "SDIO_B_D6", "SDIO_B_D7", "CAN_ADDR0", "CAN_ADDR1",
134 "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
135 "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
136 "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "DIO1_OUT",
137 "DIO2_OUT", "", "BOOT_SEL0", "BOOT_SEL1",
138 "", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
139 "HDMI_CEC", "HDMI_HPD";
140};
141
142/*
143 * Rename SoM signals according to board usage:
144 * GPIO_B_5 -> DIO2_IN
145 * GPIO_B_6 -> DIO3_IN
146 * GPIO_B_7 -> DIO4_IN
147 * GPIO_B_3 -> DIO4_OUT
148 * GPIO_B_4 -> DIO1_IN
149 * GPIO_B_2 -> DIO3_OUT
150 */
151&gpio4 {
152 gpio-line-names = "DIO2_IN", "DIO3_IN", "DIO4_IN", "GPIO_C_0",
153 "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
154 "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
155 "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
156 "ETH_A_TX_EN", "ETH_A_TX_CLK", "DIO4_OUT", "DIO1_IN",
157 "DIO3_OUT", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS",
158 "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
159 "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
160};
161
162&hdmi_pvi {
163 status = "okay";
164};
165
166&hdmi_tx {
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_hdmi>;
169 ddc-i2c-bus = <&i2c2>;
170 status = "okay";
171};
172
173&hdmi_tx_phy {
174 status = "okay";
175};
176
177&i2c1 {
178 status = "okay";
179
180 gpio_expander_dio: io-expander@20 {
181 compatible = "ti,tca6408";
182 reg = <0x20>;
183 gpio-controller;
184 #gpio-cells = <2>;
185 gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN",
186 "DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN";
187 interrupt-parent = <&gpio3>;
188 interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
189 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
190 };
191};
192
193&i2c2 {
194 status = "okay";
195};
196
197&i2c4 {
198 status = "okay";
199};
200
201&lcdif3 {
202 status = "okay";
203};
204
205&pwm2 {
206 status = "okay";
207};
208
209&reg_usdhc2_vcc {
210 status = "disabled";
211};
212
213&snvs_pwrkey {
214 status = "okay";
215};
216
217&uart1 {
218 uart-has-rtscts;
219 status = "okay";
220};
221
222&uart4 {
223 linux,rs485-enabled-at-boot-time;
224 uart-has-rtscts;
225 status = "okay";
226};
227
228&usb_dwc3_0 {
229 adp-disable;
230 hnp-disable;
231 srp-disable;
232 dr_mode = "otg";
233 extcon = <&extcon_usbc>;
234 usb-role-switch;
235 status = "okay";
236};
237
238&usb_dwc3_1 {
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_usb_hub>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243 dr_mode = "host";
244 status = "okay";
245
246 usb-hub@1 {
247 compatible = "usb424,2514";
248 reg = <1>;
249 reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
250 };
251};
252
253&usb3_0 {
254 status = "okay";
255};
256
257&usb3_1 {
258 fsl,disable-port-power-control;
259 fsl,permanently-attached;
260 status = "okay";
261};
262
263&usb3_phy0 {
264 vbus-supply = <&reg_usb1_vbus>;
265 status = "okay";
266};
267
268&usb3_phy1 {
269 status = "okay";
270};
271
272&usdhc2 {
273 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
274 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
275 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
276 vmmc-supply = <&reg_vdd_3v3>;
277 status = "okay";
278};
279
280&iomuxc {
281 pinctrl_ethphy0: ethphy0grp {
282 fsl,pins = <
283 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46
284 >;
285 };
286
287 pinctrl_ethphy1: ethphy1grp {
288 fsl,pins = <
289 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46
290 >;
291 };
292
293 pinctrl_gpio2: gpio2grp {
294 fsl,pins = <
295 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x46
296 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x46
297 >;
298 };
299
300 pinctrl_usb_hub: usbhubgrp {
301 fsl,pins = <
302 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46
303 >;
304 };
305};