Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / dts / upstream / src / arm64 / freescale / imx8mp-iota2-lumpy.dts
blob: f48cf22b423db5bf204a679e54f21c40fddb499d [file] [log] [blame]
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2023 Y Soft
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9
10/ {
11 compatible = "ysoft,imx8mp-iota2-lumpy", "fsl,imx8mp";
12 model = "Y Soft i.MX8MPlus IOTA2 Lumpy board";
13
14 beeper {
15 compatible = "pwm-beeper";
16 pwms = <&pwm4 0 500000 0>;
17 };
18
19 chosen {
20 stdout-path = &uart2;
21 };
22
23 gpio_keys: gpio-keys {
24 compatible = "gpio-keys";
25 pinctrl-0 = <&pinctrl_gpio_keys>;
26 pinctrl-names = "default";
27
28 button-reset {
29 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
30 label = "Factory RESET";
31 linux,code = <BTN_0>;
32 };
33 };
34
35 reg_usb_host: regulator-usb-host {
36 compatible = "regulator-fixed";
37 pinctrl-0 = <&pinctrl_usb_host_vbus>;
38 pinctrl-names = "default";
39 regulator-max-microvolt = <5000000>;
40 regulator-min-microvolt = <5000000>;
41 regulator-name = "usb-host";
42 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
43 enable-active-high;
44 };
45
46 memory@40000000 {
47 reg = <0x0 0x40000000 0 0x80000000>,
48 <0x1 0x00000000 0 0x80000000>;
49 device_type = "memory";
50 };
51};
52
53&A53_0 {
54 cpu-supply = <&reg_arm>;
55};
56
57&A53_1 {
58 cpu-supply = <&reg_arm>;
59};
60
61&A53_2 {
62 cpu-supply = <&reg_arm>;
63};
64
65&A53_3 {
66 cpu-supply = <&reg_arm>;
67};
68
69&eqos {
70 phy-handle = <&ethphy0>;
71 phy-mode = "rgmii-id";
72 pinctrl-0 = <&pinctrl_eqos>;
73 pinctrl-names = "default";
74 status = "okay";
75
76 mdio {
77 compatible = "snps,dwmac-mdio";
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 ethphy0: ethernet-phy@0 {
82 reg = <0>;
83 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
84 interrupt-parent = <&gpio3>;
85 pinctrl-0 = <&pinctrl_ethphy0>;
86 pinctrl-names = "default";
87 reset-assert-us = <1000>;
88 reset-deassert-us = <1000>;
89 reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
90 micrel,led-mode = <0>;
91 };
92 };
93};
94
95&fec {
96 fsl,magic-packet;
97 phy-handle = <&ethphy1>;
98 phy-mode = "rgmii-id";
99 pinctrl-0 = <&pinctrl_fec>;
100 pinctrl-names = "default";
101 status = "okay";
102
103 mdio {
104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 ethphy1: ethernet-phy@0 {
108 reg = <0>;
109 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
110 interrupt-parent = <&gpio3>;
111 pinctrl-0 = <&pinctrl_ethphy1>;
112 pinctrl-names = "default";
113 reset-assert-us = <1000>;
114 reset-deassert-us = <1000>;
115 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
116 micrel,led-mode = <0>;
117 };
118 };
119};
120
121&i2c1 {
122 clock-frequency = <400000>;
123 pinctrl-0 = <&pinctrl_i2c1>;
124 pinctrl-names = "default";
125 status = "okay";
126
127 pmic@25 {
128 compatible = "nxp,pca9450c";
129 reg = <0x25>;
130 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
131 interrupt-parent = <&gpio1>;
132 pinctrl-0 = <&pinctrl_pmic>;
133 pinctrl-names = "default";
134
135 regulators {
136 BUCK1 {
137 regulator-always-on;
138 regulator-boot-on;
139 regulator-max-microvolt = <1000000>;
140 regulator-min-microvolt = <720000>;
141 regulator-name = "BUCK1";
142 regulator-ramp-delay = <3125>;
143 };
144
145 reg_arm: BUCK2 {
146 nxp,dvs-run-voltage = <950000>;
147 nxp,dvs-standby-voltage = <850000>;
148 regulator-always-on;
149 regulator-boot-on;
150 regulator-max-microvolt = <1025000>;
151 regulator-min-microvolt = <720000>;
152 regulator-name = "BUCK2";
153 regulator-ramp-delay = <3125>;
154 };
155
156 BUCK4 {
157 regulator-always-on;
158 regulator-boot-on;
159 regulator-max-microvolt = <3600000>;
160 regulator-min-microvolt = <3000000>;
161 regulator-name = "BUCK4";
162 };
163
164 BUCK5 {
165 regulator-always-on;
166 regulator-boot-on;
167 regulator-max-microvolt = <1950000>;
168 regulator-min-microvolt = <1650000>;
169 regulator-name = "BUCK5";
170 };
171
172 BUCK6 {
173 regulator-always-on;
174 regulator-boot-on;
175 regulator-max-microvolt = <1155000>;
176 regulator-min-microvolt = <1045000>;
177 regulator-name = "BUCK6";
178 };
179
180 LDO1 {
181 regulator-always-on;
182 regulator-boot-on;
183 regulator-max-microvolt = <1950000>;
184 regulator-min-microvolt = <1650000>;
185 regulator-name = "LDO1";
186 };
187
188 LDO3 {
189 regulator-always-on;
190 regulator-boot-on;
191 regulator-max-microvolt = <1890000>;
192 regulator-min-microvolt = <1710000>;
193 regulator-name = "LDO3";
194 };
195
196 LDO4 {
197 regulator-always-on;
198 regulator-boot-on;
199 regulator-max-microvolt = <950000>;
200 regulator-min-microvolt = <850000>;
201 regulator-name = "LDO4";
202 };
203
204 LDO5 {
205 regulator-always-on;
206 regulator-boot-on;
207 regulator-max-microvolt = <3300000>;
208 regulator-min-microvolt = <1800000>;
209 regulator-name = "LDO5";
210 };
211 };
212 };
213};
214
215&i2c2 {
216 clock-frequency = <400000>;
217 pinctrl-0 = <&pinctrl_i2c2>;
218 pinctrl-names = "default";
219 status = "okay";
220
221 rtc: rtc@68 {
222 compatible = "dallas,ds1341";
223 reg = <0x68>;
224 };
225};
226
227&pwm4 {
228 pinctrl-0 = <&pinctrl_pwm4>;
229 pinctrl-names = "default";
230 status = "okay";
231};
232
233&uart2 {
234 pinctrl-0 = <&pinctrl_uart2>;
235 pinctrl-names = "default";
236 status = "okay";
237};
238
239&usb3_1 {
240 status = "okay";
241};
242
243&usb3_phy1 {
244 vbus-supply = <&reg_usb_host>;
245 status = "okay";
246};
247
248&usb_dwc3_1 {
249 dr_mode = "host";
250 status = "okay";
251};
252
253&usdhc3 {
254 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
255 assigned-clock-rates = <400000000>;
256 pinctrl-0 = <&pinctrl_usdhc3>;
257 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
258 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
259 pinctrl-names = "default", "state_100mhz", "state_200mhz";
260 bus-width = <8>;
261 non-removable;
262 status = "okay";
263};
264
265&wdog1 {
266 pinctrl-0 = <&pinctrl_wdog>;
267 pinctrl-names = "default";
268 fsl,ext-reset-output;
269 status = "okay";
270};
271
272&iomuxc {
273 pinctrl_eqos: eqosgrp {
274 fsl,pins = <
275 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
276 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
277 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
278 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
279 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
280 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
281 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
282 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
283 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
284 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
285 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
286 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
287 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
288 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
289 >;
290 };
291
292 pinctrl_ethphy0: ethphy0grp {
293 fsl,pins = <
294 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x10
295 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x10
296 >;
297 };
298
299 pinctrl_ethphy1: ethphy1grp {
300 fsl,pins = <
301 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x10
302 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10
303 >;
304 };
305
306 pinctrl_fec: fecgrp {
307 fsl,pins = <
308 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
309 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
310 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
311 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
312 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
313 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
314 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
315 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
316 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
317 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
318 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
319 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
320 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
321 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
322 >;
323 };
324
325 pinctrl_gpio_keys: gpiokeysgrp {
326 fsl,pins = <
327 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80
328 >;
329 };
330
331 pinctrl_i2c1: i2c1grp {
332 fsl,pins = <
333 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
334 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
335 >;
336 };
337
338 pinctrl_i2c2: i2c2grp {
339 fsl,pins = <
340 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
341 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
342 >;
343 };
344
345 pinctrl_pmic: pmicgrp {
346 fsl,pins = <
347 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
348 >;
349 };
350
351 pinctrl_pwm4: pwm4grp {
352 fsl,pins = <
353 MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x102
354 >;
355 };
356
357 pinctrl_uart2: uart2grp {
358 fsl,pins = <
359 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x0
360 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x0
361 >;
362 };
363
364 pinctrl_usb_host_vbus: usb1grp {
365 fsl,pins = <
366 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x0
367 >;
368 };
369
370 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
371 fsl,pins = <
372 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
373 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
374 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
375 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
376 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
377 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
378 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
379 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
380 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
381 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
382 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
383 >;
384 };
385
386 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
387 fsl,pins = <
388 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
389 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
390 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
391 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
392 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
393 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
394 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
395 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
396 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
397 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
398 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
399 >;
400 };
401
402 pinctrl_usdhc3: usdhc3grp {
403 fsl,pins = <
404 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
405 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
406 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
407 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
408 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
409 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
410 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
411 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
412 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
413 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
414 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
415 >;
416 };
417
418 pinctrl_wdog: wdoggrp {
419 fsl,pins = <
420 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
421 >;
422 };
423};