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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / dts / upstream / src / arm64 / freescale / imx8mm-iot-gateway.dts
blob: 370558a8ba46cdbc5de68b951fde085b836a4905 [file] [log] [blame]
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright 2020 CompuLab
4
5#include "imx8mm-ucm-som.dtsi"
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7/ {
8 model = "CompuLab i.MX8MM IoT Gateway";
9 compatible = "compulab,imx8mm-iot-gateway", "compulab,imx8mm-ucm-som", "fsl,imx8mm";
10
11 regulator-usbhub-ena {
12 compatible = "regulator-fixed";
13 regulator-name = "usbhub_ena";
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
16 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
17 enable-active-high;
18 regulator-always-on;
19 };
20
21 regulator-usbhub-rst {
22 compatible = "regulator-fixed";
23 regulator-name = "usbhub_rst";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
27 enable-active-high;
28 regulator-always-on;
29 };
30
31 regulator-uart1-mode {
32 compatible = "regulator-fixed";
33 regulator-name = "uart1_mode";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
37 enable-active-high;
38 regulator-always-on;
39 };
40
41 regulator-uart1-duplex {
42 compatible = "regulator-fixed";
43 regulator-name = "uart1_duplex";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
47 enable-active-high;
48 regulator-always-on;
49 };
50
51 regulator-uart1-shdn {
52 compatible = "regulator-fixed";
53 regulator-name = "uart1_shdn";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
57 enable-active-high;
58 regulator-always-on;
59 };
60
61 regulator-uart1-trmen {
62 compatible = "regulator-fixed";
63 regulator-name = "uart1_trmen";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 gpio = <&gpio4 25 GPIO_ACTIVE_LOW>;
67 regulator-always-on;
68 };
69
70 regulator-usdhc2-v {
71 compatible = "regulator-fixed";
72 regulator-name = "usdhc2_v";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
76 enable-active-high;
77 regulator-always-on;
78 };
79
80 regulator-mpcie2-rst {
81 compatible = "regulator-fixed";
82 regulator-name = "mpcie2_rst";
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
86 enable-active-high;
87 regulator-always-on;
88 };
89
90 regulator-mpcie2lora-dis {
91 compatible = "regulator-fixed";
92 regulator-name = "mpcie2lora_dis";
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
96 enable-active-high;
97 regulator-always-on;
98 };
99
100 pcie0_refclk: clock-pcie0-refclk {
101 compatible = "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <100000000>;
104 };
105};
106
107&i2c1 {
108 clock-frequency = <100000>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_i2c1>;
111 status = "okay";
112
113 eeprom@54 {
114 compatible = "atmel,24c08";
115 reg = <0x54>;
116 pagesize = <16>;
117 };
118};
119
120&ecspi1 {
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
123 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
124 status = "okay";
125};
126
127&pcie_phy {
128 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
129 fsl,tx-deemph-gen1 = <0x2d>;
130 fsl,tx-deemph-gen2 = <0xf>;
131 fsl,clkreq-unsupported;
132 clocks = <&pcie0_refclk>;
133 clock-names = "ref";
134 status = "okay";
135};
136
137&pcie0 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_pcie0>;
140 reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
141 status = "okay";
142};
143
144&usbotg1 {
145 dr_mode = "host";
146 status = "okay";
147};
148
149&usbotg2 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 dr_mode = "host";
153 usb-role-switch;
154 status = "okay";
155
156 usbhub@1 {
157 compatible = "usb424,9514";
158 reg = <1>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_usb9514>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163
164 ethernet: ethernet@1 {
165 compatible = "usb424,ec00";
166 reg = <1>;
167 };
168 };
169};
170
171&usdhc2 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_usdhc2>;
174 bus-width = <4>;
175 mmc-ddr-1_8v;
176 non-removable;
177 status = "okay";
178};
179
180&iomuxc {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_hog>;
183
184 pinctrl_hog: hoggrp {
185 fsl,pins = <
186 /* mPCIe2 */
187 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x140
188 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x140
189 >;
190 };
191
192 pinctrl_ecspi1: ecspi1grp {
193 fsl,pins = <
194 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
195 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
196 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
197 >;
198 };
199
200 pinctrl_ecspi1_cs: ecspi1csgrp {
201 fsl,pins = <
202 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
203 >;
204 };
205
206 pinctrl_pcie0: pcie0grp {
207 fsl,pins = <
208 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x140
209 >;
210 };
211
212 pinctrl_usb9514: usb9514grp {
213 fsl,pins = <
214 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x140 /* USB_PS_EN */
215 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 /* HUB_RSTn */
216 >;
217 };
218};