Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / dts / upstream / src / arm / nxp / imx / imx6sll.dtsi
blob: 8c5ca4f9b87fd6e5b37c2f7235ede43e7164c1e9 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
5 *
6 */
7
8#include <dt-bindings/clock/imx6sll-clock.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include "imx6sll-pinfunc.h"
12
13/ {
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 gpio5 = &gpio6;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 mmc0 = &usdhc1;
28 mmc1 = &usdhc2;
29 mmc2 = &usdhc3;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 spi0 = &ecspi1;
36 spi1 = &ecspi2;
37 spi3 = &ecspi3;
38 spi4 = &ecspi4;
39 usb0 = &usbotg1;
40 usb1 = &usbotg2;
41 usbphy0 = &usbphy1;
42 usbphy1 = &usbphy2;
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu0: cpu@0 {
50 compatible = "arm,cortex-a9";
51 device_type = "cpu";
52 reg = <0>;
53 next-level-cache = <&L2>;
54 operating-points =
55 /* kHz uV */
56 <996000 1275000>,
57 <792000 1175000>,
58 <396000 1075000>,
59 <198000 975000>;
60 fsl,soc-operating-points =
61 /* ARM kHz SOC-PU uV */
62 <996000 1175000>,
63 <792000 1175000>,
64 <396000 1175000>,
65 <198000 1175000>;
66 clock-latency = <61036>; /* two CLK32 periods */
67 #cooling-cells = <2>;
68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
73 clock-names = "arm", "pll2_pfd2_396m", "step",
74 "pll1_sw", "pll1_sys";
75 nvmem-cells = <&cpu_speed_grade>;
76 nvmem-cell-names = "speed_grade";
77 };
78 };
79
80 ckil: clock-ckil {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 clock-output-names = "ckil";
85 };
86
87 osc: clock-osc-24m {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
91 clock-output-names = "osc";
92 };
93
94 ipp_di0: clock-ipp-di0 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <0>;
98 clock-output-names = "ipp_di0";
99 };
100
101 ipp_di1: clock-ipp-di1 {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <0>;
105 clock-output-names = "ipp_di1";
106 };
107
108 soc {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "simple-bus";
112 interrupt-parent = <&gpc>;
113 ranges;
114
115 ocram: sram@900000 {
116 compatible = "mmio-sram";
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
119 #address-cells = <1>;
120 #size-cells = <1>;
121 };
122
123 intc: interrupt-controller@a01000 {
124 compatible = "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
126 interrupt-controller;
127 reg = <0x00a01000 0x1000>,
128 <0x00a00100 0x100>;
129 interrupt-parent = <&intc>;
130 };
131
132 L2: cache-controller@a02000 {
133 compatible = "arm,pl310-cache";
134 reg = <0x00a02000 0x1000>;
135 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
136 cache-unified;
137 cache-level = <2>;
138 arm,tag-latency = <4 2 3>;
139 arm,data-latency = <4 2 3>;
140 };
141
142 aips1: bus@2000000 {
143 compatible = "fsl,aips-bus", "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
146 reg = <0x02000000 0x100000>;
147 ranges;
148
149 spba: spba-bus@2000000 {
150 compatible = "fsl,spba-bus", "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
153 reg = <0x02000000 0x40000>;
154 ranges;
155
156 spdif: spdif@2004000 {
157 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
158 reg = <0x02004000 0x4000>;
159 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
160 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
161 dma-names = "rx", "tx";
162 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
163 <&clks IMX6SLL_CLK_OSC>,
164 <&clks IMX6SLL_CLK_SPDIF>,
165 <&clks IMX6SLL_CLK_DUMMY>,
166 <&clks IMX6SLL_CLK_DUMMY>,
167 <&clks IMX6SLL_CLK_DUMMY>,
168 <&clks IMX6SLL_CLK_IPG>,
169 <&clks IMX6SLL_CLK_DUMMY>,
170 <&clks IMX6SLL_CLK_DUMMY>,
171 <&clks IMX6SLL_CLK_SPBA>;
172 clock-names = "core", "rxtx0",
173 "rxtx1", "rxtx2",
174 "rxtx3", "rxtx4",
175 "rxtx5", "rxtx6",
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]176 "rxtx7", "spba";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]177 status = "disabled";
178 };
179
180 ecspi1: spi@2008000 {
181 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
182 reg = <0x02008000 0x4000>;
183 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
184 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
185 dma-names = "rx", "tx";
186 clocks = <&clks IMX6SLL_CLK_ECSPI1>,
187 <&clks IMX6SLL_CLK_ECSPI1>;
188 clock-names = "ipg", "per";
189 status = "disabled";
190 };
191
192 ecspi2: spi@200c000 {
193 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
194 reg = <0x0200c000 0x4000>;
195 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
196 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
197 dma-names = "rx", "tx";
198 clocks = <&clks IMX6SLL_CLK_ECSPI2>,
199 <&clks IMX6SLL_CLK_ECSPI2>;
200 clock-names = "ipg", "per";
201 status = "disabled";
202 };
203
204 ecspi3: spi@2010000 {
205 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
206 reg = <0x02010000 0x4000>;
207 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
208 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
209 dma-names = "rx", "tx";
210 clocks = <&clks IMX6SLL_CLK_ECSPI3>,
211 <&clks IMX6SLL_CLK_ECSPI3>;
212 clock-names = "ipg", "per";
213 status = "disabled";
214 };
215
216 ecspi4: spi@2014000 {
217 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
218 reg = <0x02014000 0x4000>;
219 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
220 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
221 dma-names = "rx", "tx";
222 clocks = <&clks IMX6SLL_CLK_ECSPI4>,
223 <&clks IMX6SLL_CLK_ECSPI4>;
224 clock-names = "ipg", "per";
225 status = "disabled";
226 };
227
228 uart4: serial@2018000 {
229 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
230 "fsl,imx21-uart";
231 reg = <0x02018000 0x4000>;
232 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
233 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
234 dma-names = "rx", "tx";
235 clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
236 <&clks IMX6SLL_CLK_UART4_SERIAL>;
237 clock-names = "ipg", "per";
238 status = "disabled";
239 };
240
241 uart1: serial@2020000 {
242 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
243 "fsl,imx21-uart";
244 reg = <0x02020000 0x4000>;
245 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
246 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
247 dma-names = "rx", "tx";
248 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
249 <&clks IMX6SLL_CLK_UART1_SERIAL>;
250 clock-names = "ipg", "per";
251 status = "disabled";
252 };
253
254 uart2: serial@2024000 {
255 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
256 "fsl,imx21-uart";
257 reg = <0x02024000 0x4000>;
258 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
259 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
260 dma-names = "rx", "tx";
261 clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
262 <&clks IMX6SLL_CLK_UART2_SERIAL>;
263 clock-names = "ipg", "per";
264 status = "disabled";
265 };
266
267 ssi1: ssi@2028000 {
268 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
269 reg = <0x02028000 0x4000>;
270 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
271 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
272 dma-names = "rx", "tx";
273 fsl,fifo-depth = <15>;
274 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
275 <&clks IMX6SLL_CLK_SSI1>;
276 clock-names = "ipg", "baud";
277 status = "disabled";
278 };
279
280 ssi2: ssi@202c000 {
281 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
282 reg = <0x0202c000 0x4000>;
283 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
284 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
285 dma-names = "rx", "tx";
286 fsl,fifo-depth = <15>;
287 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
288 <&clks IMX6SLL_CLK_SSI2>;
289 clock-names = "ipg", "baud";
290 status = "disabled";
291 };
292
293 ssi3: ssi@2030000 {
294 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
295 reg = <0x02030000 0x4000>;
296 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
297 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
298 dma-names = "rx", "tx";
299 fsl,fifo-depth = <15>;
300 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
301 <&clks IMX6SLL_CLK_SSI3>;
302 clock-names = "ipg", "baud";
303 status = "disabled";
304 };
305
306 uart3: serial@2034000 {
307 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
308 "fsl,imx21-uart";
309 reg = <0x02034000 0x4000>;
310 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
311 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
312 dma-name = "rx", "tx";
313 clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
314 <&clks IMX6SLL_CLK_UART3_SERIAL>;
315 clock-names = "ipg", "per";
316 status = "disabled";
317 };
318 };
319
320 pwm1: pwm@2080000 {
321 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
322 reg = <0x02080000 0x4000>;
323 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clks IMX6SLL_CLK_PWM1>,
325 <&clks IMX6SLL_CLK_PWM1>;
326 clock-names = "ipg", "per";
327 #pwm-cells = <3>;
328 };
329
330 pwm2: pwm@2084000 {
331 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
332 reg = <0x02084000 0x4000>;
333 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clks IMX6SLL_CLK_PWM2>,
335 <&clks IMX6SLL_CLK_PWM2>;
336 clock-names = "ipg", "per";
337 #pwm-cells = <3>;
338 };
339
340 pwm3: pwm@2088000 {
341 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
342 reg = <0x02088000 0x4000>;
343 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clks IMX6SLL_CLK_PWM3>,
345 <&clks IMX6SLL_CLK_PWM3>;
346 clock-names = "ipg", "per";
347 #pwm-cells = <3>;
348 };
349
350 pwm4: pwm@208c000 {
351 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
352 reg = <0x0208c000 0x4000>;
353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&clks IMX6SLL_CLK_PWM4>,
355 <&clks IMX6SLL_CLK_PWM4>;
356 clock-names = "ipg", "per";
357 #pwm-cells = <3>;
358 };
359
360 gpt1: timer@2098000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]361 compatible = "fsl,imx6sl-gpt", "fsl,imx6dl-gpt";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]362 reg = <0x02098000 0x4000>;
363 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
365 <&clks IMX6SLL_CLK_GPT_SERIAL>;
366 clock-names = "ipg", "per";
367 };
368
369 gpio1: gpio@209c000 {
370 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
371 reg = <0x0209c000 0x4000>;
372 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clks IMX6SLL_CLK_GPIO1>;
375 gpio-controller;
376 #gpio-cells = <2>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
380 };
381
382 gpio2: gpio@20a0000 {
383 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
384 reg = <0x020a0000 0x4000>;
385 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6SLL_CLK_GPIO2>;
388 gpio-controller;
389 #gpio-cells = <2>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
392 gpio-ranges = <&iomuxc 0 50 32>;
393 };
394
395 gpio3: gpio@20a4000 {
396 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
397 reg = <0x020a4000 0x4000>;
398 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6SLL_CLK_GPIO3>;
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
406 <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
407 <&iomuxc 21 6 11>;
408 };
409
410 gpio4: gpio@20a8000 {
411 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
412 reg = <0x020a8000 0x4000>;
413 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clks IMX6SLL_CLK_GPIO4>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
421 <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
422 <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
423 <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
424 <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
425 <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
426 <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
427 <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
428 <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
429 };
430
431 gpio5: gpio@20ac000 {
432 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
433 reg = <0x020ac000 0x4000>;
434 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clks IMX6SLL_CLK_GPIO5>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
442 <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
443 <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
444 <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
445 <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
446 <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
447 <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
448 <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
449 <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
450 <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
451 <&iomuxc 21 137 1>;
452 };
453
454 gpio6: gpio@20b0000 {
455 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
456 reg = <0x020b0000 0x4000>;
457 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&clks IMX6SLL_CLK_GPIO6>;
460 gpio-controller;
461 #gpio-cells = <2>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
464 };
465
466 kpp: keypad@20b8000 {
467 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
468 reg = <0x020b8000 0x4000>;
469 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&clks IMX6SLL_CLK_KPP>;
471 status = "disabled";
472 };
473
474 wdog1: watchdog@20bc000 {
475 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
476 reg = <0x020bc000 0x4000>;
477 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&clks IMX6SLL_CLK_WDOG1>;
479 };
480
481 wdog2: watchdog@20c0000 {
482 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
483 reg = <0x020c0000 0x4000>;
484 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clks IMX6SLL_CLK_WDOG2>;
486 status = "disabled";
487 };
488
489 clks: clock-controller@20c4000 {
490 compatible = "fsl,imx6sll-ccm";
491 reg = <0x020c4000 0x4000>;
492 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
494 #clock-cells = <1>;
495 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
496 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
497
498 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
499 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
500 };
501
502 anatop: anatop@20c8000 {
503 compatible = "fsl,imx6sll-anatop",
504 "fsl,imx6q-anatop",
505 "syscon", "simple-mfd";
506 reg = <0x020c8000 0x4000>;
507 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]510
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]511 reg_3p0: regulator-3p0 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]512 compatible = "fsl,anatop-regulator";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]513 regulator-name = "vdd3p0";
514 regulator-min-microvolt = <2625000>;
515 regulator-max-microvolt = <3400000>;
516 anatop-reg-offset = <0x120>;
517 anatop-vol-bit-shift = <8>;
518 anatop-vol-bit-width = <5>;
519 anatop-min-bit-val = <0>;
520 anatop-min-voltage = <2625000>;
521 anatop-max-voltage = <3400000>;
522 anatop-enable-bit = <0>;
523 };
524
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]525 tempmon: tempmon {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]526 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
527 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
528 interrupt-parent = <&gpc>;
529 fsl,tempmon = <&anatop>;
530 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
531 nvmem-cell-names = "calib", "temp_grade";
532 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]533 #thermal-sensor-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]534 };
535 };
536
537 usbphy1: usb-phy@20c9000 {
538 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
539 "fsl,imx23-usbphy";
540 reg = <0x020c9000 0x1000>;
541 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
543 phy-3p0-supply = <&reg_3p0>;
544 fsl,anatop = <&anatop>;
545 };
546
547 usbphy2: usb-phy@20ca000 {
548 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
549 "fsl,imx23-usbphy";
550 reg = <0x020ca000 0x1000>;
551 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
553 phy-3p0-supply = <&reg_3p0>;
554 fsl,anatop = <&anatop>;
555 };
556
557 snvs: snvs@20cc000 {
558 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
559 reg = <0x020cc000 0x4000>;
560
561 snvs_rtc: snvs-rtc-lp {
562 compatible = "fsl,sec-v4.0-mon-rtc-lp";
563 regmap = <&snvs>;
564 offset = <0x34>;
565 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
567 };
568
569 snvs_poweroff: snvs-poweroff {
570 compatible = "syscon-poweroff";
571 regmap = <&snvs>;
572 offset = <0x38>;
573 mask = <0x61>;
574 status = "disabled";
575 };
576
577 snvs_pwrkey: snvs-powerkey {
578 compatible = "fsl,sec-v4.0-pwrkey";
579 regmap = <&snvs>;
580 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
581 linux,keycode = <KEY_POWER>;
582 wakeup-source;
583 status = "disabled";
584 };
585 };
586
587 src: reset-controller@20d8000 {
588 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
589 reg = <0x020d8000 0x4000>;
590 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
592 #reset-cells = <1>;
593 };
594
595 gpc: interrupt-controller@20dc000 {
596 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
597 reg = <0x020dc000 0x4000>;
598 interrupt-controller;
599 #interrupt-cells = <3>;
600 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
601 interrupt-parent = <&intc>;
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]602 clocks = <&clks IMX6SLL_CLK_IPG>;
603 clock-names = "ipg";
604
605 pgc {
606 #address-cells = <1>;
607 #size-cells = <0>;
608
609 power-domain@0 {
610 reg = <0>;
611 #power-domain-cells = <0>;
612 };
613 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]614 };
615
616 iomuxc: pinctrl@20e0000 {
617 compatible = "fsl,imx6sll-iomuxc";
618 reg = <0x020e0000 0x4000>;
619 };
620
621 gpr: iomuxc-gpr@20e4000 {
622 compatible = "fsl,imx6sll-iomuxc-gpr",
623 "fsl,imx6q-iomuxc-gpr", "syscon";
624 reg = <0x020e4000 0x4000>;
625 };
626
627 csi: csi@20e8000 {
628 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
629 reg = <0x020e8000 0x4000>;
630 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&clks IMX6SLL_CLK_DUMMY>,
632 <&clks IMX6SLL_CLK_CSI>,
633 <&clks IMX6SLL_CLK_DUMMY>;
634 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
635 status = "disabled";
636 };
637
638 sdma: dma-controller@20ec000 {
639 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
640 reg = <0x020ec000 0x4000>;
641 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&clks IMX6SLL_CLK_IPG>,
643 <&clks IMX6SLL_CLK_SDMA>;
644 clock-names = "ipg", "ahb";
645 #dma-cells = <3>;
646 iram = <&ocram>;
647 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
648 };
649
650 pxp: pxp@20f0000 {
651 compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
652 reg = <0x20f0000 0x4000>;
653 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&clks IMX6SLL_CLK_PXP>;
656 clock-names = "axi";
657 };
658
659 lcdif: lcd-controller@20f8000 {
660 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
661 reg = <0x020f8000 0x4000>;
662 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
664 <&clks IMX6SLL_CLK_LCDIF_APB>,
665 <&clks IMX6SLL_CLK_DUMMY>;
666 clock-names = "pix", "axi", "disp_axi";
667 status = "disabled";
668 };
669
670 dcp: crypto@20fc000 {
671 compatible = "fsl,imx28-dcp";
672 reg = <0x020fc000 0x4000>;
673 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clks IMX6SLL_CLK_DCP>;
677 clock-names = "dcp";
678 };
679 };
680
681 aips2: bus@2100000 {
682 compatible = "fsl,aips-bus", "simple-bus";
683 #address-cells = <1>;
684 #size-cells = <1>;
685 reg = <0x02100000 0x100000>;
686 ranges;
687
688 usbotg1: usb@2184000 {
689 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
690 "fsl,imx27-usb";
691 reg = <0x02184000 0x200>;
692 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clks IMX6SLL_CLK_USBOH3>;
694 fsl,usbphy = <&usbphy1>;
695 fsl,usbmisc = <&usbmisc 0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]696 ahb-burst-config = <0x0>;
697 tx-burst-size-dword = <0x10>;
698 rx-burst-size-dword = <0x10>;
699 status = "disabled";
700 };
701
702 usbotg2: usb@2184200 {
703 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
704 "fsl,imx27-usb";
705 reg = <0x02184200 0x200>;
706 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&clks IMX6SLL_CLK_USBOH3>;
708 fsl,usbphy = <&usbphy2>;
709 fsl,usbmisc = <&usbmisc 1>;
710 ahb-burst-config = <0x0>;
711 tx-burst-size-dword = <0x10>;
712 rx-burst-size-dword = <0x10>;
713 status = "disabled";
714 };
715
716 usbmisc: usbmisc@2184800 {
717 #index-cells = <1>;
718 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
719 "fsl,imx6q-usbmisc";
720 reg = <0x02184800 0x200>;
721 };
722
723 usdhc1: mmc@2190000 {
724 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
725 reg = <0x02190000 0x4000>;
726 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clks IMX6SLL_CLK_USDHC1>,
728 <&clks IMX6SLL_CLK_USDHC1>,
729 <&clks IMX6SLL_CLK_USDHC1>;
730 clock-names = "ipg", "ahb", "per";
731 bus-width = <4>;
732 fsl,tuning-step = <2>;
733 fsl,tuning-start-tap = <20>;
734 status = "disabled";
735 };
736
737 usdhc2: mmc@2194000 {
738 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
739 reg = <0x02194000 0x4000>;
740 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clks IMX6SLL_CLK_USDHC2>,
742 <&clks IMX6SLL_CLK_USDHC2>,
743 <&clks IMX6SLL_CLK_USDHC2>;
744 clock-names = "ipg", "ahb", "per";
745 bus-width = <4>;
746 fsl,tuning-step = <2>;
747 fsl,tuning-start-tap = <20>;
748 status = "disabled";
749 };
750
751 usdhc3: mmc@2198000 {
752 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
753 reg = <0x02198000 0x4000>;
754 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&clks IMX6SLL_CLK_USDHC3>,
756 <&clks IMX6SLL_CLK_USDHC3>,
757 <&clks IMX6SLL_CLK_USDHC3>;
758 clock-names = "ipg", "ahb", "per";
759 bus-width = <4>;
760 fsl,tuning-step = <2>;
761 fsl,tuning-start-tap = <20>;
762 status = "disabled";
763 };
764
765 i2c1: i2c@21a0000 {
766 #address-cells = <1>;
767 #size-cells = <0>;
768 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
769 reg = <0x021a0000 0x4000>;
770 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&clks IMX6SLL_CLK_I2C1>;
772 status = "disabled";
773 };
774
775 i2c2: i2c@21a4000 {
776 #address-cells = <1>;
777 #size-cells = <0>;
778 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
779 reg = <0x021a4000 0x4000>;
780 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clks IMX6SLL_CLK_I2C2>;
782 status = "disabled";
783 };
784
785 i2c3: i2c@21a8000 {
786 #address-cells = <1>;
787 #size-cells = <0>;
788 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
789 reg = <0x021a8000 0x4000>;
790 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&clks IMX6SLL_CLK_I2C3>;
792 status = "disabled";
793 };
794
795 mmdc: memory-controller@21b0000 {
796 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
797 reg = <0x021b0000 0x4000>;
798 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
799 };
800
801 rngb: rng@21b4000 {
802 compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
803 reg = <0x021b4000 0x4000>;
804 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clks IMX6SLL_CLK_DUMMY>;
806 };
807
808 ocotp: efuse@21bc000 {
809 #address-cells = <1>;
810 #size-cells = <1>;
811 compatible = "fsl,imx6sll-ocotp", "syscon";
812 reg = <0x021bc000 0x4000>;
813 clocks = <&clks IMX6SLL_CLK_OCOTP>;
814
815 cpu_speed_grade: speed-grade@10 {
816 reg = <0x10 4>;
817 };
818
819 tempmon_calib: calib@38 {
820 reg = <0x38 4>;
821 };
822
823 tempmon_temp_grade: temp-grade@20 {
824 reg = <0x20 4>;
825 };
826 };
827
828 audmux: audmux@21d8000 {
829 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
830 reg = <0x021d8000 0x4000>;
831 status = "disabled";
832 };
833
834 uart5: serial@21f4000 {
835 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
836 "fsl,imx21-uart";
837 reg = <0x021f4000 0x4000>;
838 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
839 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
840 dma-names = "rx", "tx";
841 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
842 <&clks IMX6SLL_CLK_UART5_SERIAL>;
843 clock-names = "ipg", "per";
844 status = "disabled";
845 };
846 };
847 };
848};