Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / dts / upstream / src / arm / microchip / sam9x60.dtsi
blob: b8b2c1ddf3f1ebd2ff8639cf488b4b5378df27e8 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
4 *
5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
8 */
9
10#include <dt-bindings/dma/at91.h>
11#include <dt-bindings/pinctrl/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/clock/at91.h>
15#include <dt-bindings/mfd/at91-usart.h>
16#include <dt-bindings/mfd/atmel-flexcom.h>
17
18/ {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 model = "Microchip SAM9X60 SoC";
22 compatible = "microchip,sam9x60";
23 interrupt-parent = <&aic>;
24
25 aliases {
26 serial0 = &dbgu;
27 gpio0 = &pioA;
28 gpio1 = &pioB;
29 gpio2 = &pioC;
30 gpio3 = &pioD;
31 tcb0 = &tcb0;
32 tcb1 = &tcb1;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 compatible = "arm,arm926ej-s";
41 device_type = "cpu";
42 reg = <0>;
43 };
44 };
45
46 memory@20000000 {
47 device_type = "memory";
48 reg = <0x20000000 0x10000000>;
49 };
50
51 clocks {
52 slow_xtal: slow_xtal {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 };
56
57 main_xtal: main_xtal {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 };
61 };
62
63 sram: sram@300000 {
64 compatible = "mmio-sram";
65 reg = <0x00300000 0x100000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x00300000 0x100000>;
69 };
70
71 ahb {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 usb0: gadget@500000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "microchip,sam9x60-udc";
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
83 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
84 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
85 clock-names = "pclk", "hclk";
86 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
87 assigned-clock-rates = <480000000>;
88 status = "disabled";
89 };
90
91 usb1: ohci@600000 {
92 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
93 reg = <0x00600000 0x100000>;
94 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
95 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
96 clock-names = "ohci_clk", "hclk", "uhpck";
97 status = "disabled";
98 };
99
100 usb2: ehci@700000 {
101 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
102 reg = <0x00700000 0x100000>;
103 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
104 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
105 clock-names = "usb_clk", "ehci_clk";
106 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
107 assigned-clock-rates = <480000000>;
108 status = "disabled";
109 };
110
111 ebi: ebi@10000000 {
112 compatible = "microchip,sam9x60-ebi";
113 #address-cells = <2>;
114 #size-cells = <1>;
115 atmel,smc = <&smc>;
116 microchip,sfr = <&sfr>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
124 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
125 status = "disabled";
126
127 nand_controller: nand-controller {
128 compatible = "microchip,sam9x60-nand-controller";
129 ecc-engine = <&pmecc>;
130 #address-cells = <2>;
131 #size-cells = <1>;
132 ranges;
133 status = "disabled";
134 };
135 };
136
137 sdmmc0: sdio-host@80000000 {
138 compatible = "microchip,sam9x60-sdhci";
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
141 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
142 clock-names = "hclock", "multclk";
143 assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
144 assigned-clock-rates = <100000000>;
145 status = "disabled";
146 };
147
148 sdmmc1: sdio-host@90000000 {
149 compatible = "microchip,sam9x60-sdhci";
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
152 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
153 clock-names = "hclock", "multclk";
154 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
155 assigned-clock-rates = <100000000>;
156 status = "disabled";
157 };
158
159 apb {
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164
165 flx4: flexcom@f0000000 {
166 compatible = "atmel,sama5d2-flexcom";
167 reg = <0xf0000000 0x200>;
168 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0xf0000000 0x800>;
172 status = "disabled";
173
174 uart4: serial@200 {
175 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
176 reg = <0x200 0x200>;
177 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
178 dmas = <&dma0
179 (AT91_XDMAC_DT_MEM_IF(0) |
180 AT91_XDMAC_DT_PER_IF(1) |
181 AT91_XDMAC_DT_PERID(8))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]182 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]183 (AT91_XDMAC_DT_MEM_IF(0) |
184 AT91_XDMAC_DT_PER_IF(1) |
185 AT91_XDMAC_DT_PERID(9))>;
186 dma-names = "tx", "rx";
187 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
188 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]189 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]190 atmel,use-dma-rx;
191 atmel,use-dma-tx;
192 atmel,fifo-size = <16>;
193 status = "disabled";
194 };
195
196 spi4: spi@400 {
197 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
198 reg = <0x400 0x200>;
199 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame]200 #address-cells = <1>;
201 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]202 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
203 clock-names = "spi_clk";
204 dmas = <&dma0
205 (AT91_XDMAC_DT_MEM_IF(0) |
206 AT91_XDMAC_DT_PER_IF(1) |
207 AT91_XDMAC_DT_PERID(8))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]208 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]209 (AT91_XDMAC_DT_MEM_IF(0) |
210 AT91_XDMAC_DT_PER_IF(1) |
211 AT91_XDMAC_DT_PERID(9))>;
212 dma-names = "tx", "rx";
213 atmel,fifo-size = <16>;
214 status = "disabled";
215 };
216
217 i2c4: i2c@600 {
218 compatible = "microchip,sam9x60-i2c";
219 reg = <0x600 0x200>;
220 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]221 #address-cells = <1>;
222 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]223 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
224 dmas = <&dma0
225 (AT91_XDMAC_DT_MEM_IF(0) |
226 AT91_XDMAC_DT_PER_IF(1) |
227 AT91_XDMAC_DT_PERID(8))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]228 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]229 (AT91_XDMAC_DT_MEM_IF(0) |
230 AT91_XDMAC_DT_PER_IF(1) |
231 AT91_XDMAC_DT_PERID(9))>;
232 dma-names = "tx", "rx";
233 atmel,fifo-size = <16>;
234 status = "disabled";
235 };
236 };
237
238 flx5: flexcom@f0004000 {
239 compatible = "atmel,sama5d2-flexcom";
240 reg = <0xf0004000 0x200>;
241 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
242 #address-cells = <1>;
243 #size-cells = <1>;
244 ranges = <0x0 0xf0004000 0x800>;
245 status = "disabled";
246
247 uart5: serial@200 {
248 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
249 reg = <0x200 0x200>;
250 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
251 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
252 dmas = <&dma0
253 (AT91_XDMAC_DT_MEM_IF(0) |
254 AT91_XDMAC_DT_PER_IF(1) |
255 AT91_XDMAC_DT_PERID(10))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]256 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]257 (AT91_XDMAC_DT_MEM_IF(0) |
258 AT91_XDMAC_DT_PER_IF(1) |
259 AT91_XDMAC_DT_PERID(11))>;
260 dma-names = "tx", "rx";
261 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
262 clock-names = "usart";
263 atmel,use-dma-rx;
264 atmel,use-dma-tx;
265 atmel,fifo-size = <16>;
266 status = "disabled";
267 };
268
269 spi5: spi@400 {
270 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
271 reg = <0x400 0x200>;
272 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame]273 #address-cells = <1>;
274 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]275 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
276 clock-names = "spi_clk";
277 dmas = <&dma0
278 (AT91_XDMAC_DT_MEM_IF(0) |
279 AT91_XDMAC_DT_PER_IF(1) |
280 AT91_XDMAC_DT_PERID(10))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]281 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]282 (AT91_XDMAC_DT_MEM_IF(0) |
283 AT91_XDMAC_DT_PER_IF(1) |
284 AT91_XDMAC_DT_PERID(11))>;
285 dma-names = "tx", "rx";
286 atmel,fifo-size = <16>;
287 status = "disabled";
288 };
289
290 i2c5: i2c@600 {
291 compatible = "microchip,sam9x60-i2c";
292 reg = <0x600 0x200>;
293 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]294 #address-cells = <1>;
295 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]296 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
297 dmas = <&dma0
298 (AT91_XDMAC_DT_MEM_IF(0) |
299 AT91_XDMAC_DT_PER_IF(1) |
300 AT91_XDMAC_DT_PERID(10))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]301 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]302 (AT91_XDMAC_DT_MEM_IF(0) |
303 AT91_XDMAC_DT_PER_IF(1) |
304 AT91_XDMAC_DT_PERID(11))>;
305 dma-names = "tx", "rx";
306 atmel,fifo-size = <16>;
307 status = "disabled";
308 };
309 };
310
311 dma0: dma-controller@f0008000 {
312 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
313 reg = <0xf0008000 0x1000>;
314 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
315 #dma-cells = <1>;
316 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
317 clock-names = "dma_clk";
318 };
319
320 ssc: ssc@f0010000 {
321 compatible = "atmel,at91sam9g45-ssc";
322 reg = <0xf0010000 0x4000>;
323 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
324 dmas = <&dma0
325 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
326 AT91_XDMAC_DT_PERID(38))>,
327 <&dma0
328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
329 AT91_XDMAC_DT_PERID(39))>;
330 dma-names = "tx", "rx";
331 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
332 clock-names = "pclk";
333 status = "disabled";
334 };
335
336 qspi: spi@f0014000 {
337 compatible = "microchip,sam9x60-qspi";
338 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
339 reg-names = "qspi_base", "qspi_mmap";
340 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
341 dmas = <&dma0
342 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
343 AT91_XDMAC_DT_PERID(26))>,
344 <&dma0
345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
346 AT91_XDMAC_DT_PERID(27))>;
347 dma-names = "tx", "rx";
348 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
349 clock-names = "pclk", "qspick";
350 atmel,pmc = <&pmc>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 status = "disabled";
354 };
355
356 i2s: i2s@f001c000 {
357 compatible = "microchip,sam9x60-i2smcc";
358 reg = <0xf001c000 0x100>;
359 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
360 dmas = <&dma0
361 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
362 AT91_XDMAC_DT_PERID(36))>,
363 <&dma0
364 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
365 AT91_XDMAC_DT_PERID(37))>;
366 dma-names = "tx", "rx";
367 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
368 clock-names = "pclk", "gclk";
369 status = "disabled";
370 };
371
372 flx11: flexcom@f0020000 {
373 compatible = "atmel,sama5d2-flexcom";
374 reg = <0xf0020000 0x200>;
375 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
376 #address-cells = <1>;
377 #size-cells = <1>;
378 ranges = <0x0 0xf0020000 0x800>;
379 status = "disabled";
380
381 uart11: serial@200 {
382 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
383 reg = <0x200 0x200>;
384 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
385 dmas = <&dma0
386 (AT91_XDMAC_DT_MEM_IF(0) |
387 AT91_XDMAC_DT_PER_IF(1) |
388 AT91_XDMAC_DT_PERID(22))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]389 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]390 (AT91_XDMAC_DT_MEM_IF(0) |
391 AT91_XDMAC_DT_PER_IF(1) |
392 AT91_XDMAC_DT_PERID(23))>;
393 dma-names = "tx", "rx";
394 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
395 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]396 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]397 atmel,use-dma-rx;
398 atmel,use-dma-tx;
399 atmel,fifo-size = <16>;
400 status = "disabled";
401 };
402
403 i2c11: i2c@600 {
404 compatible = "microchip,sam9x60-i2c";
405 reg = <0x600 0x200>;
406 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]407 #address-cells = <1>;
408 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]409 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
410 dmas = <&dma0
411 (AT91_XDMAC_DT_MEM_IF(0) |
412 AT91_XDMAC_DT_PER_IF(1) |
413 AT91_XDMAC_DT_PERID(22))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]414 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]415 (AT91_XDMAC_DT_MEM_IF(0) |
416 AT91_XDMAC_DT_PER_IF(1) |
417 AT91_XDMAC_DT_PERID(23))>;
418 dma-names = "tx", "rx";
419 atmel,fifo-size = <16>;
420 status = "disabled";
421 };
422 };
423
424 flx12: flexcom@f0024000 {
425 compatible = "atmel,sama5d2-flexcom";
426 reg = <0xf0024000 0x200>;
427 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0xf0024000 0x800>;
431 status = "disabled";
432
433 uart12: serial@200 {
434 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
435 reg = <0x200 0x200>;
436 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
437 dmas = <&dma0
438 (AT91_XDMAC_DT_MEM_IF(0) |
439 AT91_XDMAC_DT_PER_IF(1) |
440 AT91_XDMAC_DT_PERID(24))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]441 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]442 (AT91_XDMAC_DT_MEM_IF(0) |
443 AT91_XDMAC_DT_PER_IF(1) |
444 AT91_XDMAC_DT_PERID(25))>;
445 dma-names = "tx", "rx";
446 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
447 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]448 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]449 atmel,use-dma-rx;
450 atmel,use-dma-tx;
451 atmel,fifo-size = <16>;
452 status = "disabled";
453 };
454
455 i2c12: i2c@600 {
456 compatible = "microchip,sam9x60-i2c";
457 reg = <0x600 0x200>;
458 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]459 #address-cells = <1>;
460 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]461 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
462 dmas = <&dma0
463 (AT91_XDMAC_DT_MEM_IF(0) |
464 AT91_XDMAC_DT_PER_IF(1) |
465 AT91_XDMAC_DT_PERID(24))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]466 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]467 (AT91_XDMAC_DT_MEM_IF(0) |
468 AT91_XDMAC_DT_PER_IF(1) |
469 AT91_XDMAC_DT_PERID(25))>;
470 dma-names = "tx", "rx";
471 atmel,fifo-size = <16>;
472 status = "disabled";
473 };
474 };
475
476 pit64b: timer@f0028000 {
477 compatible = "microchip,sam9x60-pit64b";
478 reg = <0xf0028000 0x100>;
479 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
480 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
481 clock-names = "pclk", "gclk";
482 };
483
484 sha: crypto@f002c000 {
485 compatible = "atmel,at91sam9g46-sha";
486 reg = <0xf002c000 0x100>;
487 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
488 dmas = <&dma0
489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
490 AT91_XDMAC_DT_PERID(34))>;
491 dma-names = "tx";
492 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
493 clock-names = "sha_clk";
494 };
495
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]496 trng: rng@f0030000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]497 compatible = "microchip,sam9x60-trng";
498 reg = <0xf0030000 0x100>;
499 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
500 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
501 };
502
503 aes: crypto@f0034000 {
504 compatible = "atmel,at91sam9g46-aes";
505 reg = <0xf0034000 0x100>;
506 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
507 dmas = <&dma0
508 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
509 AT91_XDMAC_DT_PERID(32))>,
510 <&dma0
511 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
512 AT91_XDMAC_DT_PERID(33))>;
513 dma-names = "tx", "rx";
514 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
515 clock-names = "aes_clk";
516 };
517
518 tdes: crypto@f0038000 {
519 compatible = "atmel,at91sam9g46-tdes";
520 reg = <0xf0038000 0x100>;
521 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
522 dmas = <&dma0
523 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
524 AT91_XDMAC_DT_PERID(31))>,
525 <&dma0
526 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
527 AT91_XDMAC_DT_PERID(30))>;
528 dma-names = "tx", "rx";
529 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
530 clock-names = "tdes_clk";
531 };
532
533 classd: classd@f003c000 {
534 compatible = "atmel,sama5d2-classd";
535 reg = <0xf003c000 0x100>;
536 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
537 dmas = <&dma0
538 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
539 AT91_XDMAC_DT_PERID(35))>;
540 dma-names = "tx";
541 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
542 clock-names = "pclk", "gclk";
543 status = "disabled";
544 };
545
546 can0: can@f8000000 {
547 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
548 reg = <0xf8000000 0x300>;
549 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
550 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
551 clock-names = "can_clk";
552 status = "disabled";
553 };
554
555 can1: can@f8004000 {
556 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
557 reg = <0xf8004000 0x300>;
558 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
559 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
560 clock-names = "can_clk";
561 status = "disabled";
562 };
563
564 tcb0: timer@f8008000 {
565 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 reg = <0xf8008000 0x100>;
569 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
570 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
571 clock-names = "t0_clk", "slow_clk";
572 };
573
574 tcb1: timer@f800c000 {
575 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 reg = <0xf800c000 0x100>;
579 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
580 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
581 clock-names = "t0_clk", "slow_clk";
582 };
583
584 flx6: flexcom@f8010000 {
585 compatible = "atmel,sama5d2-flexcom";
586 reg = <0xf8010000 0x200>;
587 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
588 #address-cells = <1>;
589 #size-cells = <1>;
590 ranges = <0x0 0xf8010000 0x800>;
591 status = "disabled";
592
593 uart6: serial@200 {
594 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
595 reg = <0x200 0x200>;
596 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
597 dmas = <&dma0
598 (AT91_XDMAC_DT_MEM_IF(0) |
599 AT91_XDMAC_DT_PER_IF(1) |
600 AT91_XDMAC_DT_PERID(12))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]601 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]602 (AT91_XDMAC_DT_MEM_IF(0) |
603 AT91_XDMAC_DT_PER_IF(1) |
604 AT91_XDMAC_DT_PERID(13))>;
605 dma-names = "tx", "rx";
606 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
607 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]608 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]609 atmel,use-dma-rx;
610 atmel,use-dma-tx;
611 atmel,fifo-size = <16>;
612 status = "disabled";
613 };
614
615 i2c6: i2c@600 {
616 compatible = "microchip,sam9x60-i2c";
617 reg = <0x600 0x200>;
618 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]619 #address-cells = <1>;
620 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]621 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
622 dmas = <&dma0
623 (AT91_XDMAC_DT_MEM_IF(0) |
624 AT91_XDMAC_DT_PER_IF(1) |
625 AT91_XDMAC_DT_PERID(12))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]626 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]627 (AT91_XDMAC_DT_MEM_IF(0) |
628 AT91_XDMAC_DT_PER_IF(1) |
629 AT91_XDMAC_DT_PERID(13))>;
630 dma-names = "tx", "rx";
631 atmel,fifo-size = <16>;
632 status = "disabled";
633 };
634 };
635
636 flx7: flexcom@f8014000 {
637 compatible = "atmel,sama5d2-flexcom";
638 reg = <0xf8014000 0x200>;
639 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges = <0x0 0xf8014000 0x800>;
643 status = "disabled";
644
645 uart7: serial@200 {
646 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
647 reg = <0x200 0x200>;
648 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
649 dmas = <&dma0
650 (AT91_XDMAC_DT_MEM_IF(0) |
651 AT91_XDMAC_DT_PER_IF(1) |
652 AT91_XDMAC_DT_PERID(14))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]653 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]654 (AT91_XDMAC_DT_MEM_IF(0) |
655 AT91_XDMAC_DT_PER_IF(1) |
656 AT91_XDMAC_DT_PERID(15))>;
657 dma-names = "tx", "rx";
658 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
659 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]660 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]661 atmel,use-dma-rx;
662 atmel,use-dma-tx;
663 atmel,fifo-size = <16>;
664 status = "disabled";
665 };
666
667 i2c7: i2c@600 {
668 compatible = "microchip,sam9x60-i2c";
669 reg = <0x600 0x200>;
670 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]671 #address-cells = <1>;
672 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]673 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
674 dmas = <&dma0
675 (AT91_XDMAC_DT_MEM_IF(0) |
676 AT91_XDMAC_DT_PER_IF(1) |
677 AT91_XDMAC_DT_PERID(14))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]678 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]679 (AT91_XDMAC_DT_MEM_IF(0) |
680 AT91_XDMAC_DT_PER_IF(1) |
681 AT91_XDMAC_DT_PERID(15))>;
682 dma-names = "tx", "rx";
683 atmel,fifo-size = <16>;
684 status = "disabled";
685 };
686 };
687
688 flx8: flexcom@f8018000 {
689 compatible = "atmel,sama5d2-flexcom";
690 reg = <0xf8018000 0x200>;
691 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
692 #address-cells = <1>;
693 #size-cells = <1>;
694 ranges = <0x0 0xf8018000 0x800>;
695 status = "disabled";
696
697 uart8: serial@200 {
698 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
699 reg = <0x200 0x200>;
700 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
701 dmas = <&dma0
702 (AT91_XDMAC_DT_MEM_IF(0) |
703 AT91_XDMAC_DT_PER_IF(1) |
704 AT91_XDMAC_DT_PERID(16))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]705 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]706 (AT91_XDMAC_DT_MEM_IF(0) |
707 AT91_XDMAC_DT_PER_IF(1) |
708 AT91_XDMAC_DT_PERID(17))>;
709 dma-names = "tx", "rx";
710 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
711 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]712 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]713 atmel,use-dma-rx;
714 atmel,use-dma-tx;
715 atmel,fifo-size = <16>;
716 status = "disabled";
717 };
718
719 i2c8: i2c@600 {
720 compatible = "microchip,sam9x60-i2c";
721 reg = <0x600 0x200>;
722 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]723 #address-cells = <1>;
724 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]725 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
726 dmas = <&dma0
727 (AT91_XDMAC_DT_MEM_IF(0) |
728 AT91_XDMAC_DT_PER_IF(1) |
729 AT91_XDMAC_DT_PERID(16))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]730 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]731 (AT91_XDMAC_DT_MEM_IF(0) |
732 AT91_XDMAC_DT_PER_IF(1) |
733 AT91_XDMAC_DT_PERID(17))>;
734 dma-names = "tx", "rx";
735 atmel,fifo-size = <16>;
736 status = "disabled";
737 };
738 };
739
740 flx0: flexcom@f801c000 {
741 compatible = "atmel,sama5d2-flexcom";
742 reg = <0xf801c000 0x200>;
743 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
744 #address-cells = <1>;
745 #size-cells = <1>;
746 ranges = <0x0 0xf801c000 0x800>;
747 status = "disabled";
748
749 uart0: serial@200 {
750 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
751 reg = <0x200 0x200>;
752 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
753 dmas = <&dma0
754 (AT91_XDMAC_DT_MEM_IF(0) |
755 AT91_XDMAC_DT_PER_IF(1) |
756 AT91_XDMAC_DT_PERID(0))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]757 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]758 (AT91_XDMAC_DT_MEM_IF(0) |
759 AT91_XDMAC_DT_PER_IF(1) |
760 AT91_XDMAC_DT_PERID(1))>;
761 dma-names = "tx", "rx";
762 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
763 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]764 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]765 atmel,use-dma-rx;
766 atmel,use-dma-tx;
767 atmel,fifo-size = <16>;
768 status = "disabled";
769 };
770
771 spi0: spi@400 {
772 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
773 reg = <0x400 0x200>;
774 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame]775 #address-cells = <1>;
776 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]777 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
778 clock-names = "spi_clk";
779 dmas = <&dma0
780 (AT91_XDMAC_DT_MEM_IF(0) |
781 AT91_XDMAC_DT_PER_IF(1) |
782 AT91_XDMAC_DT_PERID(0))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]783 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]784 (AT91_XDMAC_DT_MEM_IF(0) |
785 AT91_XDMAC_DT_PER_IF(1) |
786 AT91_XDMAC_DT_PERID(1))>;
787 dma-names = "tx", "rx";
788 atmel,fifo-size = <16>;
789 status = "disabled";
790 };
791
792 i2c0: i2c@600 {
793 compatible = "microchip,sam9x60-i2c";
794 reg = <0x600 0x200>;
795 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]796 #address-cells = <1>;
797 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]798 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
799 dmas = <&dma0
800 (AT91_XDMAC_DT_MEM_IF(0) |
801 AT91_XDMAC_DT_PER_IF(1) |
802 AT91_XDMAC_DT_PERID(0))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]803 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]804 (AT91_XDMAC_DT_MEM_IF(0) |
805 AT91_XDMAC_DT_PER_IF(1) |
806 AT91_XDMAC_DT_PERID(1))>;
807 dma-names = "tx", "rx";
808 atmel,fifo-size = <16>;
809 status = "disabled";
810 };
811 };
812
813 flx1: flexcom@f8020000 {
814 compatible = "atmel,sama5d2-flexcom";
815 reg = <0xf8020000 0x200>;
816 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
817 #address-cells = <1>;
818 #size-cells = <1>;
819 ranges = <0x0 0xf8020000 0x800>;
820 status = "disabled";
821
822 uart1: serial@200 {
823 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
824 reg = <0x200 0x200>;
825 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
826 dmas = <&dma0
827 (AT91_XDMAC_DT_MEM_IF(0) |
828 AT91_XDMAC_DT_PER_IF(1) |
829 AT91_XDMAC_DT_PERID(2))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]830 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]831 (AT91_XDMAC_DT_MEM_IF(0) |
832 AT91_XDMAC_DT_PER_IF(1) |
833 AT91_XDMAC_DT_PERID(3))>;
834 dma-names = "tx", "rx";
835 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
836 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]837 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]838 atmel,use-dma-rx;
839 atmel,use-dma-tx;
840 atmel,fifo-size = <16>;
841 status = "disabled";
842 };
843
844 spi1: spi@400 {
845 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
846 reg = <0x400 0x200>;
847 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame]848 #address-cells = <1>;
849 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]850 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
851 clock-names = "spi_clk";
852 dmas = <&dma0
853 (AT91_XDMAC_DT_MEM_IF(0) |
854 AT91_XDMAC_DT_PER_IF(1) |
855 AT91_XDMAC_DT_PERID(2))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]856 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]857 (AT91_XDMAC_DT_MEM_IF(0) |
858 AT91_XDMAC_DT_PER_IF(1) |
859 AT91_XDMAC_DT_PERID(3))>;
860 dma-names = "tx", "rx";
861 atmel,fifo-size = <16>;
862 status = "disabled";
863 };
864
865 i2c1: i2c@600 {
866 compatible = "microchip,sam9x60-i2c";
867 reg = <0x600 0x200>;
868 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]869 #address-cells = <1>;
870 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]871 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
872 dmas = <&dma0
873 (AT91_XDMAC_DT_MEM_IF(0) |
874 AT91_XDMAC_DT_PER_IF(1) |
875 AT91_XDMAC_DT_PERID(2))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]876 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]877 (AT91_XDMAC_DT_MEM_IF(0) |
878 AT91_XDMAC_DT_PER_IF(1) |
879 AT91_XDMAC_DT_PERID(3))>;
880 dma-names = "tx", "rx";
881 atmel,fifo-size = <16>;
882 status = "disabled";
883 };
884 };
885
886 flx2: flexcom@f8024000 {
887 compatible = "atmel,sama5d2-flexcom";
888 reg = <0xf8024000 0x200>;
889 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
890 #address-cells = <1>;
891 #size-cells = <1>;
892 ranges = <0x0 0xf8024000 0x800>;
893 status = "disabled";
894
895 uart2: serial@200 {
896 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
897 reg = <0x200 0x200>;
898 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
899 dmas = <&dma0
900 (AT91_XDMAC_DT_MEM_IF(0) |
901 AT91_XDMAC_DT_PER_IF(1) |
902 AT91_XDMAC_DT_PERID(4))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]903 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]904 (AT91_XDMAC_DT_MEM_IF(0) |
905 AT91_XDMAC_DT_PER_IF(1) |
906 AT91_XDMAC_DT_PERID(5))>;
907 dma-names = "tx", "rx";
908 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
909 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]910 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]911 atmel,use-dma-rx;
912 atmel,use-dma-tx;
913 atmel,fifo-size = <16>;
914 status = "disabled";
915 };
916
917 spi2: spi@400 {
918 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
919 reg = <0x400 0x200>;
920 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame]921 #address-cells = <1>;
922 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]923 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
924 clock-names = "spi_clk";
925 dmas = <&dma0
926 (AT91_XDMAC_DT_MEM_IF(0) |
927 AT91_XDMAC_DT_PER_IF(1) |
928 AT91_XDMAC_DT_PERID(4))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]929 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]930 (AT91_XDMAC_DT_MEM_IF(0) |
931 AT91_XDMAC_DT_PER_IF(1) |
932 AT91_XDMAC_DT_PERID(5))>;
933 dma-names = "tx", "rx";
934 atmel,fifo-size = <16>;
935 status = "disabled";
936 };
937
938 i2c2: i2c@600 {
939 compatible = "microchip,sam9x60-i2c";
940 reg = <0x600 0x200>;
941 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]942 #address-cells = <1>;
943 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]944 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
945 dmas = <&dma0
946 (AT91_XDMAC_DT_MEM_IF(0) |
947 AT91_XDMAC_DT_PER_IF(1) |
948 AT91_XDMAC_DT_PERID(4))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]949 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]950 (AT91_XDMAC_DT_MEM_IF(0) |
951 AT91_XDMAC_DT_PER_IF(1) |
952 AT91_XDMAC_DT_PERID(5))>;
953 dma-names = "tx", "rx";
954 atmel,fifo-size = <16>;
955 status = "disabled";
956 };
957 };
958
959 flx3: flexcom@f8028000 {
960 compatible = "atmel,sama5d2-flexcom";
961 reg = <0xf8028000 0x200>;
962 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
963 #address-cells = <1>;
964 #size-cells = <1>;
965 ranges = <0x0 0xf8028000 0x800>;
966 status = "disabled";
967
968 uart3: serial@200 {
969 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
970 reg = <0x200 0x200>;
971 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
972 dmas = <&dma0
973 (AT91_XDMAC_DT_MEM_IF(0) |
974 AT91_XDMAC_DT_PER_IF(1) |
975 AT91_XDMAC_DT_PERID(6))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]976 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]977 (AT91_XDMAC_DT_MEM_IF(0) |
978 AT91_XDMAC_DT_PER_IF(1) |
979 AT91_XDMAC_DT_PERID(7))>;
980 dma-names = "tx", "rx";
981 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
982 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]983 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]984 atmel,use-dma-rx;
985 atmel,use-dma-tx;
986 atmel,fifo-size = <16>;
987 status = "disabled";
988 };
989
990 spi3: spi@400 {
991 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
992 reg = <0x400 0x200>;
993 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame]994 #address-cells = <1>;
995 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]996 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
997 clock-names = "spi_clk";
998 dmas = <&dma0
999 (AT91_XDMAC_DT_MEM_IF(0) |
1000 AT91_XDMAC_DT_PER_IF(1) |
1001 AT91_XDMAC_DT_PERID(6))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1002 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1003 (AT91_XDMAC_DT_MEM_IF(0) |
1004 AT91_XDMAC_DT_PER_IF(1) |
1005 AT91_XDMAC_DT_PERID(7))>;
1006 dma-names = "tx", "rx";
1007 atmel,fifo-size = <16>;
1008 status = "disabled";
1009 };
1010
1011 i2c3: i2c@600 {
1012 compatible = "microchip,sam9x60-i2c";
1013 reg = <0x600 0x200>;
1014 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1015 #address-cells = <1>;
1016 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1017 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
1018 dmas = <&dma0
1019 (AT91_XDMAC_DT_MEM_IF(0) |
1020 AT91_XDMAC_DT_PER_IF(1) |
1021 AT91_XDMAC_DT_PERID(6))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1022 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1023 (AT91_XDMAC_DT_MEM_IF(0) |
1024 AT91_XDMAC_DT_PER_IF(1) |
1025 AT91_XDMAC_DT_PERID(7))>;
1026 dma-names = "tx", "rx";
1027 atmel,fifo-size = <16>;
1028 status = "disabled";
1029 };
1030 };
1031
1032 macb0: ethernet@f802c000 {
1033 compatible = "cdns,sam9x60-macb", "cdns,macb";
1034 reg = <0xf802c000 0x1000>;
1035 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
1036 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
1037 clock-names = "hclk", "pclk";
1038 status = "disabled";
1039 };
1040
1041 macb1: ethernet@f8030000 {
1042 compatible = "cdns,sam9x60-macb", "cdns,macb";
1043 reg = <0xf8030000 0x1000>;
1044 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
1045 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
1046 clock-names = "hclk", "pclk";
1047 status = "disabled";
1048 };
1049
1050 pwm0: pwm@f8034000 {
1051 compatible = "microchip,sam9x60-pwm";
1052 reg = <0xf8034000 0x300>;
1053 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1054 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1055 #pwm-cells = <3>;
1056 status = "disabled";
1057 };
1058
1059 hlcdc: hlcdc@f8038000 {
1060 compatible = "microchip,sam9x60-hlcdc";
1061 reg = <0xf8038000 0x4000>;
1062 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
1063 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
1064 clock-names = "periph_clk","sys_clk", "slow_clk";
1065 assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
1066 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
1067 status = "disabled";
1068
1069 hlcdc-display-controller {
1070 compatible = "atmel,hlcdc-display-controller";
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1073
1074 port@0 {
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1077 reg = <0>;
1078 };
1079 };
1080
1081 hlcdc_pwm: hlcdc-pwm {
1082 compatible = "atmel,hlcdc-pwm";
1083 #pwm-cells = <3>;
1084 };
1085 };
1086
1087 flx9: flexcom@f8040000 {
1088 compatible = "atmel,sama5d2-flexcom";
1089 reg = <0xf8040000 0x200>;
1090 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1091 #address-cells = <1>;
1092 #size-cells = <1>;
1093 ranges = <0x0 0xf8040000 0x800>;
1094 status = "disabled";
1095
1096 uart9: serial@200 {
1097 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
1098 reg = <0x200 0x200>;
1099 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
1100 dmas = <&dma0
1101 (AT91_XDMAC_DT_MEM_IF(0) |
1102 AT91_XDMAC_DT_PER_IF(1) |
1103 AT91_XDMAC_DT_PERID(18))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1104 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1105 (AT91_XDMAC_DT_MEM_IF(0) |
1106 AT91_XDMAC_DT_PER_IF(1) |
1107 AT91_XDMAC_DT_PERID(19))>;
1108 dma-names = "tx", "rx";
1109 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1110 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]1111 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1112 atmel,use-dma-rx;
1113 atmel,use-dma-tx;
1114 atmel,fifo-size = <16>;
1115 status = "disabled";
1116 };
1117
1118 i2c9: i2c@600 {
1119 compatible = "microchip,sam9x60-i2c";
1120 reg = <0x600 0x200>;
1121 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1122 #address-cells = <1>;
1123 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1124 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1125 dmas = <&dma0
1126 (AT91_XDMAC_DT_MEM_IF(0) |
1127 AT91_XDMAC_DT_PER_IF(1) |
1128 AT91_XDMAC_DT_PERID(18))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1129 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1130 (AT91_XDMAC_DT_MEM_IF(0) |
1131 AT91_XDMAC_DT_PER_IF(1) |
1132 AT91_XDMAC_DT_PERID(19))>;
1133 dma-names = "tx", "rx";
1134 atmel,fifo-size = <16>;
1135 status = "disabled";
1136 };
1137 };
1138
1139 flx10: flexcom@f8044000 {
1140 compatible = "atmel,sama5d2-flexcom";
1141 reg = <0xf8044000 0x200>;
1142 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1143 #address-cells = <1>;
1144 #size-cells = <1>;
1145 ranges = <0x0 0xf8044000 0x800>;
1146 status = "disabled";
1147
1148 uart10: serial@200 {
1149 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
1150 reg = <0x200 0x200>;
1151 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
1152 dmas = <&dma0
1153 (AT91_XDMAC_DT_MEM_IF(0) |
1154 AT91_XDMAC_DT_PER_IF(1) |
1155 AT91_XDMAC_DT_PERID(20))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1156 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1157 (AT91_XDMAC_DT_MEM_IF(0) |
1158 AT91_XDMAC_DT_PER_IF(1) |
1159 AT91_XDMAC_DT_PERID(21))>;
1160 dma-names = "tx", "rx";
1161 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1162 clock-names = "usart";
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]1163 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1164 atmel,use-dma-rx;
1165 atmel,use-dma-tx;
1166 atmel,fifo-size = <16>;
1167 status = "disabled";
1168 };
1169
1170 i2c10: i2c@600 {
1171 compatible = "microchip,sam9x60-i2c";
1172 reg = <0x600 0x200>;
1173 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1174 #address-cells = <1>;
1175 #size-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1176 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1177 dmas = <&dma0
1178 (AT91_XDMAC_DT_MEM_IF(0) |
1179 AT91_XDMAC_DT_PER_IF(1) |
1180 AT91_XDMAC_DT_PERID(20))>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1181 <&dma0
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1182 (AT91_XDMAC_DT_MEM_IF(0) |
1183 AT91_XDMAC_DT_PER_IF(1) |
1184 AT91_XDMAC_DT_PERID(21))>;
1185 dma-names = "tx", "rx";
1186 atmel,fifo-size = <16>;
1187 status = "disabled";
1188 };
1189 };
1190
1191 isi: isi@f8048000 {
1192 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
1193 reg = <0xf8048000 0x100>;
1194 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
1195 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
1196 clock-names = "isi_clk";
1197 status = "disabled";
1198 port {
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 };
1202 };
1203
1204 adc: adc@f804c000 {
1205 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
1206 reg = <0xf804c000 0x100>;
1207 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
1208 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
1209 clock-names = "adc_clk";
1210 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
1211 dma-names = "rx";
1212 atmel,min-sample-rate-hz = <200000>;
1213 atmel,max-sample-rate-hz = <20000000>;
1214 atmel,startup-time-ms = <4>;
1215 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1216 #io-channel-cells = <1>;
1217 status = "disabled";
1218 };
1219
1220 sfr: sfr@f8050000 {
1221 compatible = "microchip,sam9x60-sfr", "syscon";
1222 reg = <0xf8050000 0x100>;
1223 };
1224
1225 matrix: matrix@ffffde00 {
1226 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
1227 reg = <0xffffde00 0x200>;
1228 };
1229
1230 pmecc: ecc-engine@ffffe000 {
1231 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
1232 reg = <0xffffe000 0x300>,
1233 <0xffffe600 0x100>;
1234 };
1235
1236 mpddrc: mpddrc@ffffe800 {
1237 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
1238 reg = <0xffffe800 0x200>;
1239 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
1240 clock-names = "ddrck", "mpddr";
1241 };
1242
1243 smc: smc@ffffea00 {
1244 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
1245 reg = <0xffffea00 0x100>;
1246 };
1247
1248 aic: interrupt-controller@fffff100 {
1249 compatible = "microchip,sam9x60-aic";
1250 #interrupt-cells = <3>;
1251 interrupt-controller;
1252 reg = <0xfffff100 0x100>;
1253 atmel,external-irqs = <31>;
1254 };
1255
1256 dbgu: serial@fffff200 {
1257 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1258 reg = <0xfffff200 0x200>;
1259 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
1260 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
1261 dmas = <&dma0
1262 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1263 AT91_XDMAC_DT_PERID(28))>,
1264 <&dma0
1265 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1266 AT91_XDMAC_DT_PERID(29))>;
1267 dma-names = "tx", "rx";
1268 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
1269 clock-names = "usart";
1270 status = "disabled";
1271 };
1272
1273 pinctrl: pinctrl@fffff400 {
1274 #address-cells = <1>;
1275 #size-cells = <1>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1276 compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1277 ranges = <0xfffff400 0xfffff400 0x800>;
1278
1279 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
1280 atmel,mux-mask = <
1281 /* A B C */
1282 0xffffffff 0xffe03fff 0xef00019d /* pioA */
1283 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
1284 0xffffffff 0xffffffff 0xf83fffff /* pioC */
1285 0x003fffff 0x003f8000 0x00000000 /* pioD */
1286 >;
1287
1288 pioA: gpio@fffff400 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1289 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1290 reg = <0xfffff400 0x200>;
1291 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
1292 #gpio-cells = <2>;
1293 gpio-controller;
1294 interrupt-controller;
1295 #interrupt-cells = <2>;
1296 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
1297 };
1298
1299 pioB: gpio@fffff600 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1300 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1301 reg = <0xfffff600 0x200>;
1302 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
1303 #gpio-cells = <2>;
1304 gpio-controller;
1305 #gpio-lines = <26>;
1306 interrupt-controller;
1307 #interrupt-cells = <2>;
1308 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
1309 };
1310
1311 pioC: gpio@fffff800 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1312 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1313 reg = <0xfffff800 0x200>;
1314 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
1315 #gpio-cells = <2>;
1316 gpio-controller;
1317 interrupt-controller;
1318 #interrupt-cells = <2>;
1319 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
1320 };
1321
1322 pioD: gpio@fffffa00 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1323 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1324 reg = <0xfffffa00 0x200>;
1325 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
1326 #gpio-cells = <2>;
1327 gpio-controller;
1328 #gpio-lines = <22>;
1329 interrupt-controller;
1330 #interrupt-cells = <2>;
1331 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
1332 };
1333 };
1334
1335 pmc: clock-controller@fffffc00 {
1336 compatible = "microchip,sam9x60-pmc", "syscon";
1337 reg = <0xfffffc00 0x200>;
1338 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1339 #clock-cells = <2>;
1340 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1341 clock-names = "td_slck", "md_slck", "main_xtal";
1342 };
1343
1344 reset_controller: reset-controller@fffffe00 {
1345 compatible = "microchip,sam9x60-rstc";
1346 reg = <0xfffffe00 0x10>;
1347 clocks = <&clk32k 0>;
1348 };
1349
1350 shutdown_controller: poweroff@fffffe10 {
1351 compatible = "microchip,sam9x60-shdwc";
1352 reg = <0xfffffe10 0x10>;
1353 clocks = <&clk32k 0>;
1354 #address-cells = <1>;
1355 #size-cells = <0>;
1356 atmel,wakeup-rtc-timer;
1357 atmel,wakeup-rtt-timer;
1358 status = "disabled";
1359 };
1360
1361 rtt: rtc@fffffe20 {
1362 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
1363 reg = <0xfffffe20 0x20>;
1364 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1365 clocks = <&clk32k 1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1366 };
1367
1368 pit: timer@fffffe40 {
1369 compatible = "atmel,at91sam9260-pit";
1370 reg = <0xfffffe40 0x10>;
1371 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1372 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
1373 };
1374
1375 clk32k: clock-controller@fffffe50 {
1376 compatible = "microchip,sam9x60-sckc";
1377 reg = <0xfffffe50 0x4>;
1378 clocks = <&slow_xtal>;
1379 #clock-cells = <1>;
1380 };
1381
1382 gpbr: syscon@fffffe60 {
1383 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
1384 reg = <0xfffffe60 0x10>;
1385 };
1386
1387 rtc: rtc@fffffea8 {
1388 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
1389 reg = <0xfffffea8 0x100>;
1390 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1391 clocks = <&clk32k 1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1392 };
1393
1394 watchdog: watchdog@ffffff80 {
1395 compatible = "microchip,sam9x60-wdt";
1396 reg = <0xffffff80 0x24>;
1397 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1398 clocks = <&clk32k 0>;
1399 status = "disabled";
1400 };
1401 };
1402 };
1403};