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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / dts / upstream / src / arm / broadcom / bcm23550.dtsi
blob: c1c69381286ba2455358ced8d016559976e4255e [file] [log] [blame]
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1// SPDX-License-Identifier: BSD-3-Clause
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2/*
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]3 * Device tree for the BCM23550 SoC.
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4 *
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]5 * Copyright (C) 2016 Broadcom
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]6 */
7
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]8#include "bcm2166x-common.dtsi"
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]9
10/ {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]11 interrupt-parent = <&gic>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu0: cpu@0 {
18 device_type = "cpu";
19 compatible = "arm,cortex-a7";
20 reg = <0>;
21 clock-frequency = <1000000000>;
22 };
23
24 cpu1: cpu@1 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a7";
27 enable-method = "brcm,bcm23550";
28 secondary-boot-reg = <0x35004178>;
29 reg = <1>;
30 clock-frequency = <1000000000>;
31 };
32
33 cpu2: cpu@2 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a7";
36 enable-method = "brcm,bcm23550";
37 secondary-boot-reg = <0x35004178>;
38 reg = <2>;
39 clock-frequency = <1000000000>;
40 };
41
42 cpu3: cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a7";
45 enable-method = "brcm,bcm23550";
46 secondary-boot-reg = <0x35004178>;
47 reg = <3>;
48 clock-frequency = <1000000000>;
49 };
50 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]51};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]52
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]53&apps {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]54 cdc: cdc@1b0e000 {
55 compatible = "brcm,bcm23550-cdc";
56 reg = <0x01b0e000 0x78>;
57 };
58
59 gic: interrupt-controller@1b21000 {
60 compatible = "arm,cortex-a9-gic";
61 #interrupt-cells = <3>;
62 #address-cells = <0>;
63 interrupt-controller;
64 reg = <0x01b21000 0x1000>,
65 <0x01b22000 0x1000>;
66 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]67};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]68
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]69&bsc1 {
70 compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
71};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]72
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]73&bsc2 {
74 compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
75};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]76
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]77&bsc3 {
78 compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
79};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]80
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]81&bsc4 {
82 compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
83};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]84
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]85&gpio {
86 compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
87};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]88
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]89&smc {
90 compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]91};