Tom Rini | 9c8af15 | 2024-12-24 12:03:04 -0600 | [diff] [blame] | 1 | // SPDX-License-Identifier: BSD-3-Clause |
| 2 | /* |
| 3 | * Common device tree for components shared between the BCM21664 and BCM23550 |
| 4 | * SoCs. |
| 5 | * |
| 6 | * Copyright (C) 2016 Broadcom |
| 7 | */ |
| 8 | |
| 9 | /dts-v1/; |
| 10 | |
| 11 | #include <dt-bindings/clock/bcm21664.h> |
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 14 | |
| 15 | / { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
| 19 | /* Hub bus */ |
| 20 | hub: hub-bus@34000000 { |
| 21 | compatible = "simple-bus"; |
| 22 | ranges = <0 0x34000000 0x102f83ac>; |
| 23 | #address-cells = <1>; |
| 24 | #size-cells = <1>; |
| 25 | |
| 26 | smc: smc@4e000 { |
| 27 | /* Compatible filled by SoC DTSI */ |
| 28 | reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */ |
| 29 | }; |
| 30 | |
| 31 | resetmgr: reset-controller@1001f00 { |
| 32 | compatible = "brcm,bcm21664-resetmgr"; |
| 33 | reg = <0x01001f00 0x24>; |
| 34 | }; |
| 35 | |
| 36 | gpio: gpio@1003000 { |
| 37 | /* Compatible filled by SoC DTSI */ |
| 38 | reg = <0x01003000 0x524>; |
| 39 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 40 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 41 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 42 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| 43 | #gpio-cells = <2>; |
| 44 | #interrupt-cells = <2>; |
| 45 | gpio-controller; |
| 46 | interrupt-controller; |
| 47 | }; |
| 48 | |
| 49 | timer@1006000 { |
| 50 | compatible = "brcm,kona-timer"; |
| 51 | reg = <0x01006000 0x1c>; |
| 52 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 53 | clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; |
| 54 | }; |
| 55 | }; |
| 56 | |
| 57 | /* Slaves bus */ |
| 58 | slaves: slaves-bus@3e000000 { |
| 59 | compatible = "simple-bus"; |
| 60 | ranges = <0 0x3e000000 0x0001c070>; |
| 61 | #address-cells = <1>; |
| 62 | #size-cells = <1>; |
| 63 | |
| 64 | uartb: serial@0 { |
| 65 | compatible = "snps,dw-apb-uart"; |
| 66 | reg = <0x00000000 0x118>; |
| 67 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; |
| 68 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 69 | reg-shift = <2>; |
| 70 | reg-io-width = <4>; |
| 71 | status = "disabled"; |
| 72 | }; |
| 73 | |
| 74 | uartb2: serial@1000 { |
| 75 | compatible = "snps,dw-apb-uart"; |
| 76 | reg = <0x00001000 0x118>; |
| 77 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; |
| 78 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| 79 | reg-shift = <2>; |
| 80 | reg-io-width = <4>; |
| 81 | status = "disabled"; |
| 82 | }; |
| 83 | |
| 84 | uartb3: serial@2000 { |
| 85 | compatible = "snps,dw-apb-uart"; |
| 86 | reg = <0x00002000 0x118>; |
| 87 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; |
| 88 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 89 | reg-shift = <2>; |
| 90 | reg-io-width = <4>; |
| 91 | status = "disabled"; |
| 92 | }; |
| 93 | |
| 94 | bsc1: i2c@16000 { |
| 95 | /* Compatible filled by SoC DTSI */ |
| 96 | reg = <0x00016000 0x70>; |
| 97 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 98 | #address-cells = <1>; |
| 99 | #size-cells = <0>; |
| 100 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; |
| 101 | status = "disabled"; |
| 102 | }; |
| 103 | |
| 104 | bsc2: i2c@17000 { |
| 105 | /* Compatible filled by SoC DTSI */ |
| 106 | reg = <0x00017000 0x70>; |
| 107 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| 108 | #address-cells = <1>; |
| 109 | #size-cells = <0>; |
| 110 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; |
| 111 | status = "disabled"; |
| 112 | }; |
| 113 | |
| 114 | bsc3: i2c@18000 { |
| 115 | /* Compatible filled by SoC DTSI */ |
| 116 | reg = <0x00018000 0x70>; |
| 117 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| 118 | #address-cells = <1>; |
| 119 | #size-cells = <0>; |
| 120 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; |
| 121 | status = "disabled"; |
| 122 | }; |
| 123 | |
| 124 | bsc4: i2c@1c000 { |
| 125 | /* Compatible filled by SoC DTSI */ |
| 126 | reg = <0x0001c000 0x70>; |
| 127 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
| 128 | #address-cells = <1>; |
| 129 | #size-cells = <0>; |
| 130 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; |
| 131 | status = "disabled"; |
| 132 | }; |
| 133 | }; |
| 134 | |
| 135 | /* Apps bus */ |
| 136 | apps: apps-bus@3e300000 { |
| 137 | compatible = "simple-bus"; |
| 138 | ranges = <0 0x3e300000 0x01c02000>; |
| 139 | #address-cells = <1>; |
| 140 | #size-cells = <1>; |
| 141 | |
| 142 | usbotg: usb@e20000 { |
| 143 | compatible = "snps,dwc2"; |
| 144 | reg = <0x00e20000 0x10000>; |
| 145 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| 146 | clocks = <&usb_otg_ahb_clk>; |
| 147 | clock-names = "otg"; |
| 148 | phys = <&usbphy>; |
| 149 | phy-names = "usb2-phy"; |
| 150 | status = "disabled"; |
| 151 | }; |
| 152 | |
| 153 | usbphy: usb-phy@e30000 { |
| 154 | compatible = "brcm,kona-usb2-phy"; |
| 155 | reg = <0x00e30000 0x28>; |
| 156 | #phy-cells = <0>; |
| 157 | status = "disabled"; |
| 158 | }; |
| 159 | |
| 160 | sdio1: mmc@e80000 { |
| 161 | compatible = "brcm,kona-sdhci"; |
| 162 | reg = <0x00e80000 0x801c>; |
| 163 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 164 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; |
| 165 | status = "disabled"; |
| 166 | }; |
| 167 | |
| 168 | sdio2: mmc@e90000 { |
| 169 | compatible = "brcm,kona-sdhci"; |
| 170 | reg = <0x00e90000 0x801c>; |
| 171 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 172 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; |
| 173 | status = "disabled"; |
| 174 | }; |
| 175 | |
| 176 | sdio3: mmc@ea0000 { |
| 177 | compatible = "brcm,kona-sdhci"; |
| 178 | reg = <0x00ea0000 0x801c>; |
| 179 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 180 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; |
| 181 | status = "disabled"; |
| 182 | }; |
| 183 | |
| 184 | sdio4: mmc@eb0000 { |
| 185 | compatible = "brcm,kona-sdhci"; |
| 186 | reg = <0x00eb0000 0x801c>; |
| 187 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 188 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; |
| 189 | status = "disabled"; |
| 190 | }; |
| 191 | }; |
| 192 | |
| 193 | clocks { |
| 194 | #address-cells = <1>; |
| 195 | #size-cells = <1>; |
| 196 | ranges; |
| 197 | |
| 198 | /* |
| 199 | * Fixed clocks are defined before CCUs whose |
| 200 | * clocks may depend on them. |
| 201 | */ |
| 202 | |
| 203 | ref_32k_clk: ref_32k { |
| 204 | #clock-cells = <0>; |
| 205 | compatible = "fixed-clock"; |
| 206 | clock-frequency = <32768>; |
| 207 | }; |
| 208 | |
| 209 | bbl_32k_clk: bbl_32k { |
| 210 | #clock-cells = <0>; |
| 211 | compatible = "fixed-clock"; |
| 212 | clock-frequency = <32768>; |
| 213 | }; |
| 214 | |
| 215 | ref_13m_clk: ref_13m { |
| 216 | #clock-cells = <0>; |
| 217 | compatible = "fixed-clock"; |
| 218 | clock-frequency = <13000000>; |
| 219 | }; |
| 220 | |
| 221 | var_13m_clk: var_13m { |
| 222 | #clock-cells = <0>; |
| 223 | compatible = "fixed-clock"; |
| 224 | clock-frequency = <13000000>; |
| 225 | }; |
| 226 | |
| 227 | dft_19_5m_clk: dft_19_5m { |
| 228 | #clock-cells = <0>; |
| 229 | compatible = "fixed-clock"; |
| 230 | clock-frequency = <19500000>; |
| 231 | }; |
| 232 | |
| 233 | ref_crystal_clk: ref_crystal { |
| 234 | #clock-cells = <0>; |
| 235 | compatible = "fixed-clock"; |
| 236 | clock-frequency = <26000000>; |
| 237 | }; |
| 238 | |
| 239 | ref_52m_clk: ref_52m { |
| 240 | #clock-cells = <0>; |
| 241 | compatible = "fixed-clock"; |
| 242 | clock-frequency = <52000000>; |
| 243 | }; |
| 244 | |
| 245 | var_52m_clk: var_52m { |
| 246 | #clock-cells = <0>; |
| 247 | compatible = "fixed-clock"; |
| 248 | clock-frequency = <52000000>; |
| 249 | }; |
| 250 | |
| 251 | usb_otg_ahb_clk: usb_otg_ahb { |
| 252 | #clock-cells = <0>; |
| 253 | compatible = "fixed-clock"; |
| 254 | clock-frequency = <52000000>; |
| 255 | }; |
| 256 | |
| 257 | ref_96m_clk: ref_96m { |
| 258 | #clock-cells = <0>; |
| 259 | compatible = "fixed-clock"; |
| 260 | clock-frequency = <96000000>; |
| 261 | }; |
| 262 | |
| 263 | var_96m_clk: var_96m { |
| 264 | #clock-cells = <0>; |
| 265 | compatible = "fixed-clock"; |
| 266 | clock-frequency = <96000000>; |
| 267 | }; |
| 268 | |
| 269 | ref_104m_clk: ref_104m { |
| 270 | #clock-cells = <0>; |
| 271 | compatible = "fixed-clock"; |
| 272 | clock-frequency = <104000000>; |
| 273 | }; |
| 274 | |
| 275 | var_104m_clk: var_104m { |
| 276 | #clock-cells = <0>; |
| 277 | compatible = "fixed-clock"; |
| 278 | clock-frequency = <104000000>; |
| 279 | }; |
| 280 | |
| 281 | ref_156m_clk: ref_156m { |
| 282 | #clock-cells = <0>; |
| 283 | compatible = "fixed-clock"; |
| 284 | clock-frequency = <156000000>; |
| 285 | }; |
| 286 | |
| 287 | var_156m_clk: var_156m { |
| 288 | #clock-cells = <0>; |
| 289 | compatible = "fixed-clock"; |
| 290 | clock-frequency = <156000000>; |
| 291 | }; |
| 292 | |
| 293 | root_ccu: root_ccu@35001000 { |
| 294 | compatible = "brcm,bcm21664-root-ccu"; |
| 295 | reg = <0x35001000 0x0f00>; |
| 296 | #clock-cells = <1>; |
| 297 | clock-output-names = "frac_1m"; |
| 298 | }; |
| 299 | |
| 300 | aon_ccu: aon_ccu@35002000 { |
| 301 | compatible = "brcm,bcm21664-aon-ccu"; |
| 302 | reg = <0x35002000 0x0f00>; |
| 303 | #clock-cells = <1>; |
| 304 | clock-output-names = "hub_timer"; |
| 305 | }; |
| 306 | |
| 307 | slave_ccu: slave_ccu@3e011000 { |
| 308 | compatible = "brcm,bcm21664-slave-ccu"; |
| 309 | reg = <0x3e011000 0x0f00>; |
| 310 | #clock-cells = <1>; |
| 311 | clock-output-names = "uartb", |
| 312 | "uartb2", |
| 313 | "uartb3", |
| 314 | "bsc1", |
| 315 | "bsc2", |
| 316 | "bsc3", |
| 317 | "bsc4"; |
| 318 | }; |
| 319 | |
| 320 | master_ccu: master_ccu@3f001000 { |
| 321 | compatible = "brcm,bcm21664-master-ccu"; |
| 322 | reg = <0x3f001000 0x0f00>; |
| 323 | #clock-cells = <1>; |
| 324 | clock-output-names = "sdio1", |
| 325 | "sdio2", |
| 326 | "sdio3", |
| 327 | "sdio4", |
| 328 | "sdio1_sleep", |
| 329 | "sdio2_sleep", |
| 330 | "sdio3_sleep", |
| 331 | "sdio4_sleep"; |
| 332 | }; |
| 333 | }; |
| 334 | }; |