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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / drivers / video / tegra / hdmi.h
blob: d17655973e38d8d5fbb3308165d5e55816415282 [file] [log] [blame]
Svyatoslav Ryhel1f9a5cb2023-06-22 20:46:00 +0300[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2010
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7#ifndef _TEGRA_HDMI_H
8#define _TEGRA_HDMI_H
9
10#ifndef __ASSEMBLY__
11#include <linux/bitops.h>
12#endif
13
14/* Register definitions for the Tegra high-definition multimedia interface */
15
16/* High-Definition Multimedia Interface (HDMI_) regs */
17struct hdmi_ctlr {
18 /* Address 0x000 ~ 0x0d2 */
19 uint ctxsw; /* _CTXSW */ /* 0x00 */
20
21 uint nv_pdisp_sor_state0; /* _NV_PDISP_SOR_STATE0 */
22 uint nv_pdisp_sor_state1; /* _NV_PDISP_SOR_STATE1 */
23 uint nv_pdisp_sor_state2; /* _NV_PDISP_SOR_STATE2 */
24
25 uint nv_pdisp_rg_hdcp_an_msb; /* _NV_PDISP_RG_HDCP_AN_MSB */
26 uint nv_pdisp_rg_hdcp_an_lsb; /* _NV_PDISP_RG_HDCP_AN_LSB */
27 uint nv_pdisp_rg_hdcp_cn_msb; /* _NV_PDISP_RG_HDCP_CN_MSB */
28 uint nv_pdisp_rg_hdcp_cn_lsb; /* _NV_PDISP_RG_HDCP_CN_LSB */
29 uint nv_pdisp_rg_hdcp_aksv_msb; /* _NV_PDISP_RG_HDCP_AKSV_MSB */
30 uint nv_pdisp_rg_hdcp_aksv_lsb; /* _NV_PDISP_RG_HDCP_AKSV_LSB */
31 uint nv_pdisp_rg_hdcp_bksv_msb; /* _NV_PDISP_RG_HDCP_BKSV_MSB */
32 uint nv_pdisp_rg_hdcp_bksv_lsb; /* _NV_PDISP_RG_HDCP_BKSV_LSB */
33 uint nv_pdisp_rg_hdcp_cksv_msb; /* _NV_PDISP_RG_HDCP_CKSV_MSB */
34 uint nv_pdisp_rg_hdcp_cksv_lsb; /* _NV_PDISP_RG_HDCP_CKSV_LSB */
35 uint nv_pdisp_rg_hdcp_dksv_msb; /* _NV_PDISP_RG_HDCP_DKSV_MSB */
36 uint nv_pdisp_rg_hdcp_dksv_lsb; /* _NV_PDISP_RG_HDCP_DKSV_LSB */
37 uint nv_pdisp_rg_hdcp_ctrl; /* _NV_PDISP_RG_HDCP_CTRL */ /* 0x10 */
38 uint nv_pdisp_rg_hdcp_cmode; /* _NV_PDISP_RG_HDCP_CMODE */
39 uint nv_pdisp_rg_hdcp_mprime_msb; /* _NV_PDISP_RG_HDCP_MPRIME_MSB */
40 uint nv_pdisp_rg_hdcp_mprime_lsb; /* _NV_PDISP_RG_HDCP_MPRIME_LSB */
41 uint nv_pdisp_rg_hdcp_sprime_msb; /* _NV_PDISP_RG_HDCP_SPRIME_MSB */
42 uint nv_pdisp_rg_hdcp_sprime_lsb2; /* _NV_PDISP_RG_HDCP_SPRIME_LSB2 */
43 uint nv_pdisp_rg_hdcp_sprime_lsb1; /* _NV_PDISP_RG_HDCP_SPRIME_LSB1 */
44 uint nv_pdisp_rg_hdcp_ri; /* _NV_PDISP_RG_HDCP_RI */
45 uint nv_pdisp_rg_hdcp_cs_msb; /* _NV_PDISP_RG_HDCP_CS_MSB */
46 uint nv_pdisp_rg_hdcp_cs_lsb; /* _NV_PDISP_RG_HDCP_CS_LSB */
47
48 uint nv_pdisp_hdmi_audio_emu0; /* _NV_PDISP_HDMI_AUDIO_EMU0 */
49 uint nv_pdisp_hdmi_audio_emu_rdata0; /* _NV_PDISP_HDMI_AUDIO_EMU_RDATA0 */
50 uint nv_pdisp_hdmi_audio_emu1; /* _NV_PDISP_HDMI_AUDIO_EMU1 */
51 uint nv_pdisp_hdmi_audio_emu2; /* _NV_PDISP_HDMI_AUDIO_EMU2 */
52 uint nv_pdisp_hdmi_audio_infoframe_ctrl; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL */
53 uint nv_pdisp_hdmi_audio_infoframe_status; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS */
54 uint nv_pdisp_hdmi_audio_infoframe_header; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER */ /* 0x20 */
55 uint nv_pdisp_hdmi_audio_infoframe_subpack0_low; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW */
56 uint nv_pdisp_hdmi_audio_infoframe_subpack0_high; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH */
57
58 uint nv_pdisp_hdmi_avi_infoframe_ctrl; /* _NV_PDISP_HDMI_AVI_INFOFRAME_CTRL */
59 uint nv_pdisp_hdmi_avi_infoframe_status; /* _NV_PDISP_HDMI_AVI_INFOFRAME_STATUS */
60 uint nv_pdisp_hdmi_avi_infoframe_header; /* _NV_PDISP_HDMI_AVI_INFOFRAME_HEADER */
61 uint nv_pdisp_hdmi_avi_infoframe_subpack0_low; /* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW */
62 uint nv_pdisp_hdmi_avi_infoframe_subpack0_high; /* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH */
63 uint nv_pdisp_hdmi_avi_infoframe_subpack1_low; /* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW */
64 uint nv_pdisp_hdmi_avi_infoframe_subpack1_high; /* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH */
65
66 uint nv_pdisp_hdmi_generic_ctrl; /* _NV_PDISP_HDMI_GENERIC_CTRL */
67 uint nv_pdisp_hdmi_generic_status; /* _NV_PDISP_HDMI_GENERIC_STATUS */
68 uint nv_pdisp_hdmi_generic_header; /* _NV_PDISP_HDMI_GENERIC_HEADER */
69 uint nv_pdisp_hdmi_generic_subpack0_low; /* _NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW */
70 uint nv_pdisp_hdmi_generic_subpack0_high; /* _NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH */
71 uint nv_pdisp_hdmi_generic_subpack1_low; /* _NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW */
72 uint nv_pdisp_hdmi_generic_subpack1_high; /* _NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH */
73 uint nv_pdisp_hdmi_generic_subpack2_low; /* _NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW */
74 uint nv_pdisp_hdmi_generic_subpack2_high; /* _NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH */
75 uint nv_pdisp_hdmi_generic_subpack3_low; /* _NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW */
76 uint nv_pdisp_hdmi_generic_subpack3_high; /* _NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH */
77
78 uint nv_pdisp_hdmi_acr_ctrl; /* _NV_PDISP_HDMI_ACR_CTRL */
79 uint nv_pdisp_hdmi_acr_0320_subpack_low; /* _NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW */
80 uint nv_pdisp_hdmi_acr_0320_subpack_high; /* _NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH */
81 uint nv_pdisp_hdmi_acr_0441_subpack_low; /* _NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW */
82 uint nv_pdisp_hdmi_acr_0441_subpack_high; /* _NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH */
83 uint nv_pdisp_hdmi_acr_0882_subpack_low; /* _NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW */
84 uint nv_pdisp_hdmi_acr_0882_subpack_high; /* _NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH */
85 uint nv_pdisp_hdmi_acr_1764_subpack_low; /* _NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW */
86 uint nv_pdisp_hdmi_acr_1764_subpack_high; /* _NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH */
87 uint nv_pdisp_hdmi_acr_0480_subpack_low; /* _NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW */
88 uint nv_pdisp_hdmi_acr_0480_subpack_high; /* _NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH */
89 uint nv_pdisp_hdmi_acr_0960_subpack_low; /* _NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW */
90 uint nv_pdisp_hdmi_acr_0960_subpack_high; /* _NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH */
91 uint nv_pdisp_hdmi_acr_1920_subpack_low; /* _NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW */
92 uint nv_pdisp_hdmi_acr_1920_subpack_high; /* _NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH */
93
94 uint nv_pdisp_hdmi_ctrl; /* _NV_PDISP_HDMI_CTRL */
95 uint nv_pdisp_hdmi_vsync_keepout; /* _NV_PDISP_HDMI_VSYNC_KEEPOUT */
96 uint nv_pdisp_hdmi_vsync_window; /* _NV_PDISP_HDMI_VSYNC_WINDOW */
97 uint nv_pdisp_hdmi_gcp_ctrl; /* _NV_PDISP_HDMI_GCP_CTRL */
98 uint nv_pdisp_hdmi_gcp_status; /* _NV_PDISP_HDMI_GCP_STATUS */
99 uint nv_pdisp_hdmi_gcp_subpack; /* _NV_PDISP_HDMI_GCP_SUBPACK */
100 uint nv_pdisp_hdmi_channel_status1; /* _NV_PDISP_HDMI_CHANNEL_STATUS1 */
101 uint nv_pdisp_hdmi_channel_status2; /* _NV_PDISP_HDMI_CHANNEL_STATUS2 */
102 uint nv_pdisp_hdmi_emu0; /* _NV_PDISP_HDMI_EMU0 */
103 uint nv_pdisp_hdmi_emu1; /* _NV_PDISP_HDMI_EMU1 */
104 uint nv_pdisp_hdmi_emu1_rdata; /* _NV_PDISP_HDMI_EMU1_RDATA */
105 uint nv_pdisp_hdmi_spare; /* _NV_PDISP_HDMI_SPARE */
106 uint nv_pdisp_hdmi_spdif_chn_status1; /* _NV_PDISP_HDMI_SPDIF_CHN_STATUS1 */
107 uint nv_pdisp_hdmi_spdif_chn_status2; /* _NV_PDISP_HDMI_SPDIF_CHN_STATUS2 */
108
109 uint nv_pdisp_hdcprif_rom_ctrl; /* _NV_PDISP_HDCPRIF_ROM_CTRL */
110
111 uint unused;
112
113 uint nv_pdisp_sor_cap; /* _NV_PDISP_SOR_CAP */
114 uint nv_pdisp_sor_pwr; /* _NV_PDISP_SOR_PWR */
115 uint nv_pdisp_sor_test; /* _NV_PDISP_SOR_TEST */
116 uint nv_pdisp_sor_pll0; /* _NV_PDISP_SOR_PLL0 */
117 uint nv_pdisp_sor_pll1; /* _NV_PDISP_SOR_PLL1 */
118 uint nv_pdisp_sor_pll2; /* _NV_PDISP_SOR_PLL2 */
119 uint nv_pdisp_sor_cstm; /* _NV_PDISP_SOR_CSTM */
120 uint nv_pdisp_sor_lvds; /* _NV_PDISP_SOR_LVDS */
121 uint nv_pdisp_sor_crca; /* _NV_PDISP_SOR_CRCA */
122 uint nv_pdisp_sor_crcb; /* _NV_PDISP_SOR_CRCB */
123 uint nv_pdisp_sor_blank; /* _NV_PDISP_SOR_BLANK */
124
125 uint nv_pdisp_sor_seq_ctl; /* _NV_PDISP_SOR_SEQ_CTL */
126 uint nv_pdisp_sor_seq_inst0; /* _NV_PDISP_SOR_SEQ_INST0 */
127 uint nv_pdisp_sor_seq_inst1; /* _NV_PDISP_SOR_SEQ_INST1 */
128 uint nv_pdisp_sor_seq_inst2; /* _NV_PDISP_SOR_SEQ_INST2 */
129 uint nv_pdisp_sor_seq_inst3; /* _NV_PDISP_SOR_SEQ_INST3 */
130 uint nv_pdisp_sor_seq_inst4; /* _NV_PDISP_SOR_SEQ_INST4 */
131 uint nv_pdisp_sor_seq_inst5; /* _NV_PDISP_SOR_SEQ_INST5 */
132 uint nv_pdisp_sor_seq_inst6; /* _NV_PDISP_SOR_SEQ_INST6 */
133 uint nv_pdisp_sor_seq_inst7; /* _NV_PDISP_SOR_SEQ_INST7 */
134 uint nv_pdisp_sor_seq_inst8; /* _NV_PDISP_SOR_SEQ_INST8 */
135 uint nv_pdisp_sor_seq_inst9; /* _NV_PDISP_SOR_SEQ_INST9 */
136 uint nv_pdisp_sor_seq_insta; /* _NV_PDISP_SOR_SEQ_INSTA */
137 uint nv_pdisp_sor_seq_instb; /* _NV_PDISP_SOR_SEQ_INSTB */
138 uint nv_pdisp_sor_seq_instc; /* _NV_PDISP_SOR_SEQ_INSTC */
139 uint nv_pdisp_sor_seq_instd; /* _NV_PDISP_SOR_SEQ_INSTD */
140 uint nv_pdisp_sor_seq_inste; /* _NV_PDISP_SOR_SEQ_INSTE */
141 uint nv_pdisp_sor_seq_instf; /* _NV_PDISP_SOR_SEQ_INSTF */
142
143 uint unused1[2];
144
145 uint nv_pdisp_sor_vcrca0; /* _NV_PDISP_SOR_VCRCA0 */
146 uint nv_pdisp_sor_vcrca1; /* _NV_PDISP_SOR_VCRCA1 */
147 uint nv_pdisp_sor_ccrca0; /* _NV_PDISP_SOR_CCRCA0 */
148 uint nv_pdisp_sor_ccrca1; /* _NV_PDISP_SOR_CCRCA1 */
149
150 uint nv_pdisp_sor_edataa0; /* _NV_PDISP_SOR_EDATAA0 */
151 uint nv_pdisp_sor_edataa1; /* _NV_PDISP_SOR_EDATAA1 */
152
153 uint nv_pdisp_sor_counta0; /* _NV_PDISP_SOR_COUNTA0 */
154 uint nv_pdisp_sor_counta1; /* _NV_PDISP_SOR_COUNTA1 */
155
156 uint nv_pdisp_sor_debuga0; /* _NV_PDISP_SOR_DEBUGA0 */
157 uint nv_pdisp_sor_debuga1; /* _NV_PDISP_SOR_DEBUGA1 */
158
159 uint nv_pdisp_sor_trig; /* _NV_PDISP_SOR_TRIG */
160 uint nv_pdisp_sor_mscheck; /* _NV_PDISP_SOR_MSCHECK */
161 uint nv_pdisp_sor_lane_drive_current; /* _NV_PDISP_SOR_LANE_DRIVE_CURRENT */
162
163 uint nv_pdisp_audio_debug0; /* _NV_PDISP_AUDIO_DEBUG0 0x7f */
164 uint nv_pdisp_audio_debug1; /* _NV_PDISP_AUDIO_DEBUG1 0x80 */
165 uint nv_pdisp_audio_debug2; /* _NV_PDISP_AUDIO_DEBUG2 0x81 */
166
167 uint nv_pdisp_audio_fs1; /* _NV_PDISP_AUDIO_FS1 0x82 */
168 uint nv_pdisp_audio_fs2; /* _NV_PDISP_AUDIO_FS2 */
169 uint nv_pdisp_audio_fs3; /* _NV_PDISP_AUDIO_FS3 */
170 uint nv_pdisp_audio_fs4; /* _NV_PDISP_AUDIO_FS4 */
171 uint nv_pdisp_audio_fs5; /* _NV_PDISP_AUDIO_FS5 */
172 uint nv_pdisp_audio_fs6; /* _NV_PDISP_AUDIO_FS6 */
173 uint nv_pdisp_audio_fs7; /* _NV_PDISP_AUDIO_FS7 0x88 */
174
175 uint nv_pdisp_audio_pulse_width; /* _NV_PDISP_AUDIO_PULSE_WIDTH */
176 uint nv_pdisp_audio_threshold; /* _NV_PDISP_AUDIO_THRESHOLD */
177 uint nv_pdisp_audio_cntrl0; /* _NV_PDISP_AUDIO_CNTRL0 */
178 uint nv_pdisp_audio_n; /* _NV_PDISP_AUDIO_N */
179 uint nv_pdisp_audio_nval[7]; /* _NV_PDISP_AUDIO_NVAL */
180
181 uint nv_pdisp_hdcprif_rom_timing; /* _NV_PDISP_HDCPRIF_ROM_TIMING */
182 uint nv_pdisp_sor_refclk; /* _NV_PDISP_SOR_REFCLK */
183 uint nv_pdisp_crc_control; /* _NV_PDISP_CRC_CONTROL */
184 uint nv_pdisp_input_control; /* _NV_PDISP_INPUT_CONTROL */
185 uint nv_pdisp_scratch; /* _NV_PDISP_SCRATCH */
186 uint nv_pdisp_pe_current; /* _NV_PDISP_PE_CURRENT */
187
188 uint nv_pdisp_key_ctrl; /* _NV_PDISP_KEY_CTRL */
189 uint nv_pdisp_key_debug0; /* _NV_PDISP_KEY_DEBUG0 */
190 uint nv_pdisp_key_debug1; /* _NV_PDISP_KEY_DEBUG1 */
191 uint nv_pdisp_key_debug2; /* _NV_PDISP_KEY_DEBUG2 */
192 uint nv_pdisp_key_hdcp_key_0; /* _NV_PDISP_KEY_HDCP_KEY_0 */
193 uint nv_pdisp_key_hdcp_key_1; /* _NV_PDISP_KEY_HDCP_KEY_1 */
194 uint nv_pdisp_key_hdcp_key_2; /* _NV_PDISP_KEY_HDCP_KEY_2 */
195 uint nv_pdisp_key_hdcp_key_3; /* _NV_PDISP_KEY_HDCP_KEY_3 */
196 uint nv_pdisp_key_hdcp_key_trig; /* _NV_PDISP_KEY_HDCP_KEY_3 */
197 uint nv_pdisp_key_skey_index; /* _NV_PDISP_KEY_HDCP_KEY_3 */ /* 0xa3 */
198
199 uint unused2[8];
200
201 uint nv_pdisp_sor_audio_cntrl0; /* _NV_PDISP_SOR_AUDIO_CNTRL0 */ /* 0xac */
202 uint nv_pdisp_sor_audio_debug; /* _NV_PDISP_SOR_AUDIO_DEBUG */
203 uint nv_pdisp_sor_audio_spare0; /* _NV_PDISP_SOR_AUDIO_SPARE0 */
204 uint nv_pdisp_sor_audio_nval[7]; /* _NV_PDISP_SOR_AUDIO_NVAL 0xaf ~ 0xb5 */
205 uint nv_pdisp_sor_audio_hda_scratch[4]; /* _NV_PDISP_SOR_AUDIO_HDA_SCRATCH 0xb6 ~ 0xb9 */
206 uint nv_pdisp_sor_audio_hda_codec_scratch[2]; /* _NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH 0xba ~ 0xbb */
207
208 uint nv_pdisp_sor_audio_hda_eld_bufwr; /* _NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR */
209 uint nv_pdisp_sor_audio_hda_presense; /* _NV_PDISP_SOR_AUDIO_HDA_PRESENSE */
210 uint nv_pdisp_sor_audio_hda_cp; /* _NV_PDISP_SOR_AUDIO_HDA_CP */
211 uint nv_pdisp_sor_audio_aval[8]; /* _NV_PDISP_SOR_AUDIO_AVAL */
212 uint nv_pdisp_sor_audio_gen_ctrl; /* _NV_PDISP_SOR_AUDIO_GEN_CTRL */
213
214 uint unused3[4];
215
216 uint nv_pdisp_int_status; /* _NV_PDISP_INT_STATUS */
217 uint nv_pdisp_int_mask; /* _NV_PDISP_INT_MASK */
218 uint nv_pdisp_int_enable; /* _NV_PDISP_INT_ENABLE */
219
220 uint unused4[2];
221
222 uint nv_pdisp_sor_io_peak_current; /* _NV_PDISP_SOR_IO_PEAK_CURRENT */
223 uint nv_pdisp_sor_pad_ctls0; /* _NV_PDISP_SOR_PAD_CTLS0 */
224};
225
226/* HDMI_NV_PDISP_SOR_STATE0 0x01 */
227#define SOR_STATE_UPDATE BIT(0)
228
229/* HDMI_NV_PDISP_SOR_STATE1 0x02 */
230#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE BIT(1)
231#define SOR_STATE_ASY_ORMODE_NORMAL BIT(2)
232#define SOR_STATE_ATTACHED BIT(3)
233
234/* HDMI_NV_PDISP_SOR_STATE2 0x03 */
235#define SOR_STATE_ASY_OWNER_NONE (0 << 0)
236#define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
237#define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
238#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
239#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
240#define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
241#define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
242#define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
243#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
244#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
245#define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
246#define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
247#define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
248#define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
249#define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
250#define SOR_STATE_ASY_DEPOL_POS (0 << 14)
251#define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
252
253#define INFOFRAME_CTRL_ENABLE BIT(0)
254#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
255#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
256#define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
257
258/* HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a */
259#define GENERIC_CTRL_ENABLE BIT(0)
260#define GENERIC_CTRL_OTHER BIT(4)
261#define GENERIC_CTRL_SINGLE BIT(8)
262#define GENERIC_CTRL_HBLANK BIT(12)
263#define GENERIC_CTRL_AUDIO BIT(16)
264
265/* HDMI_NV_PDISP_HDMI_ACR_* */
266#define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
267#define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
268#define ACR_ENABLE BIT(31)
269
270/* HDMI_NV_PDISP_HDMI_CTRL 0x44 */
271#define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
272#define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
273#define HDMI_CTRL_ENABLE BIT(30)
274
275/* HDMI_NV_PDISP_HDMI_VSYNC_* */
276#define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
277#define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
278#define VSYNC_WINDOW_ENABLE BIT(31)
279
280/* HDMI_NV_PDISP_HDMI_SPARE 0x4f */
281#define SPARE_HW_CTS BIT(0)
282#define SPARE_FORCE_SW_CTS BIT(1)
283#define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
284
285/* HDMI_NV_PDISP_SOR_PWR 0x55 */
286#define SOR_PWR_NORMAL_STATE_PD (0 << 0)
287#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
288#define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
289#define SOR_PWR_NORMAL_START_ALT (1 << 1)
290#define SOR_PWR_SAFE_STATE_PD (0 << 16)
291#define SOR_PWR_SAFE_STATE_PU (1 << 16)
292#define SOR_PWR_SETTING_NEW_DONE (0 << 31)
293#define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
294#define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
295
296/* HDMI_NV_PDISP_SOR_PLL0 0x57 */
297#define SOR_PLL_PWR BIT(0)
298#define SOR_PLL_PDBG BIT(1)
299#define SOR_PLL_VCAPD BIT(2)
300#define SOR_PLL_PDPORT BIT(3)
301#define SOR_PLL_RESISTORSEL BIT(4)
302#define SOR_PLL_PULLDOWN BIT(5)
303#define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
304#define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
305#define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
306#define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
307#define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)
308
309/* HDMI_NV_PDISP_SOR_PLL1 0x58 */
310#define SOR_PLL_TMDS_TERM_ENABLE BIT(8)
311#define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
312#define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
313#define SOR_PLL_PE_EN BIT(28)
314#define SOR_PLL_HALF_FULL_PE BIT(29)
315#define SOR_PLL_S_D_PIN_PE BIT(30)
316
317/* HDMI_NV_PDISP_SOR_CSTM 0x5a */
318#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
319#define SOR_CSTM_PLLDIV BIT(21)
320#define SOR_CSTM_LVDS_ENABLE BIT(16)
321#define SOR_CSTM_MODE_LVDS (0 << 12)
322#define SOR_CSTM_MODE_TMDS (1 << 12)
323#define SOR_CSTM_MODE_MASK (3 << 12)
324
325/* HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f */
326#define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0)
327#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
328#define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
329#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
330#define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
331#define SOR_SEQ_STATUS BIT(28)
332#define SOR_SEQ_SWITCH BIT(30)
333
334/* HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x)) */
335#define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
336#define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
337#define SOR_SEQ_INST_HALT (1 << 15)
338#define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
339#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
340#define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
341#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
342#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
343
344/* HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e */
345#define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)
346#define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
347#define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
348#define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
349#define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0)
350#define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8)
351#define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16)
352#define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24)
353
354/* Drive current list */
355enum {
356 DRIVE_CURRENT_1_500_mA,
357 DRIVE_CURRENT_1_875_mA,
358 DRIVE_CURRENT_2_250_mA,
359 DRIVE_CURRENT_2_625_mA,
360 DRIVE_CURRENT_3_000_mA,
361 DRIVE_CURRENT_3_375_mA,
362 DRIVE_CURRENT_3_750_mA,
363 DRIVE_CURRENT_4_125_mA,
364 DRIVE_CURRENT_4_500_mA,
365 DRIVE_CURRENT_4_875_mA,
366 DRIVE_CURRENT_5_250_mA,
367 DRIVE_CURRENT_5_625_mA,
368 DRIVE_CURRENT_6_000_mA,
369 DRIVE_CURRENT_6_375_mA,
370 DRIVE_CURRENT_6_750_mA,
371 DRIVE_CURRENT_7_125_mA,
372 DRIVE_CURRENT_7_500_mA,
373 DRIVE_CURRENT_7_875_mA,
374 DRIVE_CURRENT_8_250_mA,
375 DRIVE_CURRENT_8_625_mA,
376 DRIVE_CURRENT_9_000_mA,
377 DRIVE_CURRENT_9_375_mA,
378 DRIVE_CURRENT_9_750_mA,
379 DRIVE_CURRENT_10_125_mA,
380 DRIVE_CURRENT_10_500_mA,
381 DRIVE_CURRENT_10_875_mA,
382 DRIVE_CURRENT_11_250_mA,
383 DRIVE_CURRENT_11_625_mA,
384 DRIVE_CURRENT_12_000_mA,
385 DRIVE_CURRENT_12_375_mA,
386 DRIVE_CURRENT_12_750_mA,
387 DRIVE_CURRENT_13_125_mA,
388 DRIVE_CURRENT_13_500_mA,
389 DRIVE_CURRENT_13_875_mA,
390 DRIVE_CURRENT_14_250_mA,
391 DRIVE_CURRENT_14_625_mA,
392 DRIVE_CURRENT_15_000_mA,
393 DRIVE_CURRENT_15_375_mA,
394 DRIVE_CURRENT_15_750_mA,
395 DRIVE_CURRENT_16_125_mA,
396 DRIVE_CURRENT_16_500_mA,
397 DRIVE_CURRENT_16_875_mA,
398 DRIVE_CURRENT_17_250_mA,
399 DRIVE_CURRENT_17_625_mA,
400 DRIVE_CURRENT_18_000_mA,
401 DRIVE_CURRENT_18_375_mA,
402 DRIVE_CURRENT_18_750_mA,
403 DRIVE_CURRENT_19_125_mA,
404 DRIVE_CURRENT_19_500_mA,
405 DRIVE_CURRENT_19_875_mA,
406 DRIVE_CURRENT_20_250_mA,
407 DRIVE_CURRENT_20_625_mA,
408 DRIVE_CURRENT_21_000_mA,
409 DRIVE_CURRENT_21_375_mA,
410 DRIVE_CURRENT_21_750_mA,
411 DRIVE_CURRENT_22_125_mA,
412 DRIVE_CURRENT_22_500_mA,
413 DRIVE_CURRENT_22_875_mA,
414 DRIVE_CURRENT_23_250_mA,
415 DRIVE_CURRENT_23_625_mA,
416 DRIVE_CURRENT_24_000_mA,
417 DRIVE_CURRENT_24_375_mA,
418 DRIVE_CURRENT_24_750_mA,
419};
420
421/* Drive current list for T114 */
422enum {
423 DRIVE_CURRENT_0_000_mA_T114,
424 DRIVE_CURRENT_0_400_mA_T114,
425 DRIVE_CURRENT_0_800_mA_T114,
426 DRIVE_CURRENT_1_200_mA_T114,
427 DRIVE_CURRENT_1_600_mA_T114,
428 DRIVE_CURRENT_2_000_mA_T114,
429 DRIVE_CURRENT_2_400_mA_T114,
430 DRIVE_CURRENT_2_800_mA_T114,
431 DRIVE_CURRENT_3_200_mA_T114,
432 DRIVE_CURRENT_3_600_mA_T114,
433 DRIVE_CURRENT_4_000_mA_T114,
434 DRIVE_CURRENT_4_400_mA_T114,
435 DRIVE_CURRENT_4_800_mA_T114,
436 DRIVE_CURRENT_5_200_mA_T114,
437 DRIVE_CURRENT_5_600_mA_T114,
438 DRIVE_CURRENT_6_000_mA_T114,
439 DRIVE_CURRENT_6_400_mA_T114,
440 DRIVE_CURRENT_6_800_mA_T114,
441 DRIVE_CURRENT_7_200_mA_T114,
442 DRIVE_CURRENT_7_600_mA_T114,
443 DRIVE_CURRENT_8_000_mA_T114,
444 DRIVE_CURRENT_8_400_mA_T114,
445 DRIVE_CURRENT_8_800_mA_T114,
446 DRIVE_CURRENT_9_200_mA_T114,
447 DRIVE_CURRENT_9_600_mA_T114,
448 DRIVE_CURRENT_10_000_mA_T114,
449 DRIVE_CURRENT_10_400_mA_T114,
450 DRIVE_CURRENT_10_800_mA_T114,
451 DRIVE_CURRENT_11_200_mA_T114,
452 DRIVE_CURRENT_11_600_mA_T114,
453 DRIVE_CURRENT_12_000_mA_T114,
454 DRIVE_CURRENT_12_400_mA_T114,
455 DRIVE_CURRENT_12_800_mA_T114,
456 DRIVE_CURRENT_13_200_mA_T114,
457 DRIVE_CURRENT_13_600_mA_T114,
458 DRIVE_CURRENT_14_000_mA_T114,
459 DRIVE_CURRENT_14_400_mA_T114,
460 DRIVE_CURRENT_14_800_mA_T114,
461 DRIVE_CURRENT_15_200_mA_T114,
462 DRIVE_CURRENT_15_600_mA_T114,
463 DRIVE_CURRENT_16_000_mA_T114,
464 DRIVE_CURRENT_16_400_mA_T114,
465 DRIVE_CURRENT_16_800_mA_T114,
466 DRIVE_CURRENT_17_200_mA_T114,
467 DRIVE_CURRENT_17_600_mA_T114,
468 DRIVE_CURRENT_18_000_mA_T114,
469 DRIVE_CURRENT_18_400_mA_T114,
470 DRIVE_CURRENT_18_800_mA_T114,
471 DRIVE_CURRENT_19_200_mA_T114,
472 DRIVE_CURRENT_19_600_mA_T114,
473 DRIVE_CURRENT_20_000_mA_T114,
474 DRIVE_CURRENT_20_400_mA_T114,
475 DRIVE_CURRENT_20_800_mA_T114,
476 DRIVE_CURRENT_21_200_mA_T114,
477 DRIVE_CURRENT_21_600_mA_T114,
478 DRIVE_CURRENT_22_000_mA_T114,
479 DRIVE_CURRENT_22_400_mA_T114,
480 DRIVE_CURRENT_22_800_mA_T114,
481 DRIVE_CURRENT_23_200_mA_T114,
482 DRIVE_CURRENT_23_600_mA_T114,
483 DRIVE_CURRENT_24_000_mA_T114,
484 DRIVE_CURRENT_24_400_mA_T114,
485 DRIVE_CURRENT_24_800_mA_T114,
486 DRIVE_CURRENT_25_200_mA_T114,
487 DRIVE_CURRENT_25_400_mA_T114,
488 DRIVE_CURRENT_25_800_mA_T114,
489 DRIVE_CURRENT_26_200_mA_T114,
490 DRIVE_CURRENT_26_600_mA_T114,
491 DRIVE_CURRENT_27_000_mA_T114,
492 DRIVE_CURRENT_27_400_mA_T114,
493 DRIVE_CURRENT_27_800_mA_T114,
494 DRIVE_CURRENT_28_200_mA_T114,
495};
496
497/* HDMI_NV_PDISP_AUDIO_FS */
498#define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
499#define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
500
501/* HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b */
502#define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
503#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
504#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
505#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
506#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
507
508/* HDMI_NV_PDISP_AUDIO_N 0x8c */
509#define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
510#define AUDIO_N_RESETF (1 << 20)
511#define AUDIO_N_GENERATE_NORMAL (0 << 24)
512#define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
513
514/* HDMI_NV_PDISP_SOR_REFCLK 0x95 */
515#define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
516#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
517
518/* HDMI_NV_PDISP_INPUT_CONTROL 0x97 */
519#define HDMI_SRC_DISPLAYA (0 << 0)
520#define HDMI_SRC_DISPLAYB (1 << 0)
521#define ARM_VIDEO_RANGE_FULL (0 << 1)
522#define ARM_VIDEO_RANGE_LIMITED (1 << 1)
523
524/* HDMI_NV_PDISP_PE_CURRENT 0x99 */
525#define PE_CURRENT0(x) (((x) & 0xf) << 0)
526#define PE_CURRENT1(x) (((x) & 0xf) << 8)
527#define PE_CURRENT2(x) (((x) & 0xf) << 16)
528#define PE_CURRENT3(x) (((x) & 0xf) << 24)
529
530enum {
531 PE_CURRENT_0_0_mA,
532 PE_CURRENT_0_5_mA,
533 PE_CURRENT_1_0_mA,
534 PE_CURRENT_1_5_mA,
535 PE_CURRENT_2_0_mA,
536 PE_CURRENT_2_5_mA,
537 PE_CURRENT_3_0_mA,
538 PE_CURRENT_3_5_mA,
539 PE_CURRENT_4_0_mA,
540 PE_CURRENT_4_5_mA,
541 PE_CURRENT_5_0_mA,
542 PE_CURRENT_5_5_mA,
543 PE_CURRENT_6_0_mA,
544 PE_CURRENT_6_5_mA,
545 PE_CURRENT_7_0_mA,
546 PE_CURRENT_7_5_mA,
547};
548
549enum {
550 PE_CURRENT_0_mA_T114,
551 PE_CURRENT_1_mA_T114,
552 PE_CURRENT_2_mA_T114,
553 PE_CURRENT_3_mA_T114,
554 PE_CURRENT_4_mA_T114,
555 PE_CURRENT_5_mA_T114,
556 PE_CURRENT_6_mA_T114,
557 PE_CURRENT_7_mA_T114,
558 PE_CURRENT_8_mA_T114,
559 PE_CURRENT_9_mA_T114,
560 PE_CURRENT_10_mA_T114,
561 PE_CURRENT_11_mA_T114,
562 PE_CURRENT_12_mA_T114,
563 PE_CURRENT_13_mA_T114,
564 PE_CURRENT_14_mA_T114,
565 PE_CURRENT_15_mA_T114,
566};
567
568/* HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac */
569#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
570#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
571#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
572#define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
573
574/* HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0xae */
575#define SOR_AUDIO_SPARE0_HBR_ENABLE BIT(27)
576
577/* HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0xba */
578#define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID BIT(30)
579#define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff
580
581/* HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd */
582#define SOR_AUDIO_HDA_PRESENSE_VALID BIT(1)
583#define SOR_AUDIO_HDA_PRESENSE_PRESENT BIT(0)
584
585/* HDMI_NV_PDISP_INT_STATUS 0xcc */
586#define INT_SCRATCH BIT(3)
587#define INT_CP_REQUEST BIT(2)
588#define INT_CODEC_SCRATCH1 BIT(1)
589#define INT_CODEC_SCRATCH0 BIT(0)
590
591/* HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1 */
592#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0)
593#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8)
594#define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16)
595#define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24)
596
597enum {
598 PEAK_CURRENT_0_000_mA,
599 PEAK_CURRENT_0_200_mA,
600 PEAK_CURRENT_0_400_mA,
601 PEAK_CURRENT_0_600_mA,
602 PEAK_CURRENT_0_800_mA,
603 PEAK_CURRENT_1_000_mA,
604 PEAK_CURRENT_1_200_mA,
605 PEAK_CURRENT_1_400_mA,
606 PEAK_CURRENT_1_600_mA,
607 PEAK_CURRENT_1_800_mA,
608 PEAK_CURRENT_2_000_mA,
609 PEAK_CURRENT_2_200_mA,
610 PEAK_CURRENT_2_400_mA,
611 PEAK_CURRENT_2_600_mA,
612 PEAK_CURRENT_2_800_mA,
613 PEAK_CURRENT_3_000_mA,
614 PEAK_CURRENT_3_200_mA,
615 PEAK_CURRENT_3_400_mA,
616 PEAK_CURRENT_3_600_mA,
617 PEAK_CURRENT_3_800_mA,
618 PEAK_CURRENT_4_000_mA,
619 PEAK_CURRENT_4_200_mA,
620 PEAK_CURRENT_4_400_mA,
621 PEAK_CURRENT_4_600_mA,
622 PEAK_CURRENT_4_800_mA,
623 PEAK_CURRENT_5_000_mA,
624 PEAK_CURRENT_5_200_mA,
625 PEAK_CURRENT_5_400_mA,
626 PEAK_CURRENT_5_600_mA,
627 PEAK_CURRENT_5_800_mA,
628 PEAK_CURRENT_6_000_mA,
629 PEAK_CURRENT_6_200_mA,
630 PEAK_CURRENT_6_400_mA,
631 PEAK_CURRENT_6_600_mA,
632 PEAK_CURRENT_6_800_mA,
633 PEAK_CURRENT_7_000_mA,
634 PEAK_CURRENT_7_200_mA,
635 PEAK_CURRENT_7_400_mA,
636 PEAK_CURRENT_7_600_mA,
637 PEAK_CURRENT_7_800_mA,
638 PEAK_CURRENT_8_000_mA,
639 PEAK_CURRENT_8_200_mA,
640 PEAK_CURRENT_8_400_mA,
641 PEAK_CURRENT_8_600_mA,
642 PEAK_CURRENT_8_800_mA,
643 PEAK_CURRENT_9_000_mA,
644 PEAK_CURRENT_9_200_mA,
645 PEAK_CURRENT_9_400_mA,
646};
647
648#endif /* _TEGRA_HDMI_H */