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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / drivers / reset / rst-rk3528.c
blob: f6e760d468d9b7f75ebdc4599af2b8591be6547e [file] [log] [blame]
Joseph Chen72c11232025-04-07 22:46:49 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 * Based on Sebastian Reichel's implementation for RK3588
5 */
6
7#include <dm.h>
8#include <asm/arch-rockchip/clock.h>
9#include <dt-bindings/reset/rockchip,rk3528-cru.h>
10
11/* 0xFF4A0000 + 0x0A00 */
12#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
13
14/* mapping table for reset ID to register offset */
15static const int rk3528_register_offset[] = {
16 /* CRU_SOFTRST_CON03 */
17 RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
18 RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
19 RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
20 RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
21 RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
22 RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
23 RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
24 RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
25 RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
26 RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
27 RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
28
29 /* CRU_SOFTRST_CON05 */
30 RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
31 RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
32 RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
33
34 /* CRU_SOFTRST_CON06 */
35 RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
36 RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
37 RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
38 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
39
40 /* CRU_SOFTRST_CON08 */
41 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
42 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
43 RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
44 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
45 RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
46 RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
47 RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
48 RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
49
50 /* CRU_SOFTRST_CON09 */
51 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
52 RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
53 RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
54 RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
55 RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
56 RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
57 RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
58 RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
59 RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
60 RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
61 RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
62 RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
63 RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
64 RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
65
66 /* CRU_SOFTRST_CON10 */
67 RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
68 RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
69 RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
70 RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
71 RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
72 RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
73 RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
74 RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
75 RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
76
77 /* CRU_SOFTRST_CON11 */
78 RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
79 RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
80 RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
81 RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
82 RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
83 RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
84 RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
85
86 /* CRU_SOFTRST_CON25 */
87 RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
88 RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
89 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
90 RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
91 RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
92 RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
93 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
94 RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
95 RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
96 RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
97
98 /* CRU_SOFTRST_CON26 */
99 RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
100 RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
101 RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
102 RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
103 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
104 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
105 RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
106 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
107 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
108 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
109 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
110 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
111 RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
112
113 /* CRU_SOFTRST_CON27 */
114 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
115 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
116 RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
117 RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
118 RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
119 RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
120 RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
121 RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
122 RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
123 RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
124 RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
125 RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
126 RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
127
128 /* CRU_SOFTRST_CON28 */
129 RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
130 RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
131 RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
132 RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
133 RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
134 RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
135
136 /* CRU_SOFTRST_CON30 */
137 RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
138 RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
139 RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
140 RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
141 RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
142
143 /* CRU_SOFTRST_CON32 */
144 RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
145 RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
146 RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
147 RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
148 RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
149 RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
150 RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
151 RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
152 RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
153 RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
154 RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
155 RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
156 RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
157
158 /* CRU_SOFTRST_CON33 */
159 RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
160
161 /* CRU_SOFTRST_CON34 */
162 RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
163 RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
164 RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
165 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
166
167 /* CRU_SOFTRST_CON36 */
168 RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
169 RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
170 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
171 RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
172 RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
173 RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
174 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
175 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
176 RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
177 RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
178 RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
179 RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
180
181 /* CRU_SOFTRST_CON37 */
182 RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
183 RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
184 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
185 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
186 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
187 RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
188 RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
189
190 /* CRU_SOFTRST_CON38 */
191 RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
192 RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
193 RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
194 RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
195 RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
196 RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
197 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
198 RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
199 RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
200 RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
201 RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
202
203 /* CRU_SOFTRST_CON39 */
204 RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
205 RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
206 RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
207 RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
208 RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
209 RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
210 RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
211 RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
212 RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
213 RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
214 RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
215
216 /* CRU_SOFTRST_CON40 */
217 RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
218 RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
219 RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
220 RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
221 RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
222 RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
223 RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
224 RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
225 RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
226
227 /* CRU_SOFTRST_CON41 */
228 RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
229 RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
230 RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
231 RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
232 RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
233 RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
234 RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
235 RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
236 RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
237 RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
238
239 /* CRU_SOFTRST_CON42 */
240 RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
241 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
242 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
243 RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
244 RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
245 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
246 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
247 RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
248 RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
249 RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
250 RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
251 RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
252
253 /* CRU_SOFTRST_CON43 */
254 RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
255 RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
256 RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
257 RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
258 RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
259 RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
260 RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
261 RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
262 RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
263 RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
264 RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
265 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
266 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
267
268 /* CRU_SOFTRST_CON44 */
269 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
270 RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
271 RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
272 RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
273 RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
274 RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
275 RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
276 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
277
278 /* CRU_SOFTRST_CON45 */
279 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
280 RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
281 RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
282 RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
283 RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
284 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
285 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
286 RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
287 RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
288 RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
289 RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
290 RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
291 RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
292 RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
293
294 /* CRU_SOFTRST_CON46 */
295 RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
296};
297
298int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
299{
300 return rockchip_reset_bind_lut(pdev, rk3528_register_offset,
301 reg_offset, reg_number);
302}