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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / drivers / reset / Kconfig
blob: a0d079c455575fa9c9e1febe6a38d72a77e4530a [file] [log] [blame]
Stephen Warren185ad872016-06-17 09:43:58 -0600[diff] [blame]1menu "Reset Controller Support"
2
3config DM_RESET
4 bool "Enable reset controllers using Driver Model"
5 depends on DM && OF_CONTROL
6 help
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
11 cases this API is applicable to chips outside the CPU as well,
12 although driving such reset isgnals using GPIOs may be more
13 appropriate in this case.
14
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]15config SANDBOX_RESET
16 bool "Enable the sandbox reset test driver"
17 depends on DM_MAILBOX && SANDBOX
18 help
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
21 doing anything beyond a little error checking.
22
Patrice Chotard1235aa02017-03-22 10:54:03 +0100[diff] [blame]23config STI_RESET
24 bool "Enable the STi reset"
25 depends on ARCH_STI
26 help
27 Support for reset controllers on STMicroelectronics STiH407 family SoCs.
28 Say Y if you want to control reset signals provided by system config
29 block.
30
Patrice Chotard5c121e12017-09-13 18:00:07 +0200[diff] [blame]31config STM32_RESET
32 bool "Enable the STM32 reset"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400[diff] [blame]33 depends on ARCH_STM32 || ARCH_STM32MP
Patrice Chotard5c121e12017-09-13 18:00:07 +0200[diff] [blame]34 help
35 Support for reset controllers on STMicroelectronics STM32 family SoCs.
Trevor Woernere3d9c992020-05-06 08:02:43 -0400[diff] [blame]36 This reset driver is compatible with STM32 F4/F7 and H7 SoCs.
Patrice Chotard5c121e12017-09-13 18:00:07 +0200[diff] [blame]37
Stephen Warren3017ab52016-09-13 10:45:58 -0600[diff] [blame]38config TEGRA_CAR_RESET
39 bool "Enable Tegra CAR-based reset driver"
40 depends on TEGRA_CAR
41 help
42 Enable support for manipulating Tegra's on-SoC reset signals via
43 direct register access to the Tegra CAR (Clock And Reset controller).
44
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600[diff] [blame]45config TEGRA186_RESET
46 bool "Enable Tegra186 BPMP-based reset driver"
47 depends on TEGRA186_BPMP
48 help
49 Enable support for manipulating Tegra's on-SoC reset signals via IPC
50 requests to the BPMP (Boot and Power Management Processor).
51
Christian Marangi101dce92025-03-14 19:59:23 +0100[diff] [blame]52config RESET_AIROHA
53 bool "Reset controller driver for Airoha SoCs"
54 depends on DM_RESET && ARCH_AIROHA
55 default y
56 help
57 Support for reset controller on Airoha SoCs.
58
Andreas Dannenberg4cfdf4d2018-08-27 15:57:41 +0530[diff] [blame]59config RESET_TI_SCI
60 bool "TI System Control Interface (TI SCI) reset driver"
61 depends on DM_RESET && TI_SCI_PROTOCOL
62 help
63 This enables the reset driver support over TI System Control Interface
64 available on some new TI's SoCs. If you wish to use reset resources
65 managed by the TI System Controller, say Y here. Otherwise, say N.
66
Álvaro Fernández Rojas5161bd32017-05-03 15:10:21 +0200[diff] [blame]67config RESET_BCM6345
68 bool "Reset controller driver for BCM6345"
69 depends on DM_RESET && ARCH_BMIPS
70 help
71 Support reset controller on BCM6345.
72
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900[diff] [blame]73config RESET_UNIPHIER
74 bool "Reset controller driver for UniPhier SoCs"
75 depends on ARCH_UNIPHIER
76 default y
77 help
78 Support for reset controllers on UniPhier SoCs.
79 Say Y if you want to control reset signals provided by System Control
80 block, Media I/O block, Peripheral Block.
81
Chia-Wei, Wangb39ef892020-10-15 10:25:14 +0800[diff] [blame]82config RESET_AST2500
maxims@google.com750875c2017-04-17 12:00:24 -0700[diff] [blame]83 bool "Reset controller driver for AST2500 SoCs"
Chia-Wei, Wangacc78362020-10-15 10:25:13 +0800[diff] [blame]84 depends on DM_RESET
maxims@google.com750875c2017-04-17 12:00:24 -0700[diff] [blame]85 default y if ASPEED_AST2500
86 help
Chia-Wei, Wangacc78362020-10-15 10:25:13 +0800[diff] [blame]87 Support for reset controller on AST2500 SoC.
88 Say Y if you want to control reset signals of different peripherals
89 through System Control Unit (SCU).
maxims@google.com750875c2017-04-17 12:00:24 -0700[diff] [blame]90
Chia-Wei, Wang71140512020-12-14 13:54:26 +0800[diff] [blame]91config RESET_AST2600
92 bool "Reset controller driver for AST2600 SoCs"
93 depends on DM_RESET
94 default y if ASPEED_AST2600
95 help
96 Support for reset controller on AST2600 SoC.
97 Say Y if you want to control reset signals of different peripherals
98 through System Control Unit (SCU).
99
Elaine Zhang6e9a3a72017-12-19 18:22:37 +0800[diff] [blame]100config RESET_ROCKCHIP
101 bool "Reset controller driver for Rockchip SoCs"
102 depends on DM_RESET && ARCH_ROCKCHIP && CLK
103 default y
104 help
105 Support for reset controller on rockchip SoC. The main limitation
106 though is that some reset signals, like I2C or MISC reset multiple
107 devices.
108
Eugeniy Paltsev062da422019-10-08 19:29:30 +0300[diff] [blame]109config RESET_HSDK
110 bool "Synopsys HSDK Reset Driver"
111 depends on DM_RESET && TARGET_HSDK
112 default y
113 help
114 This enables the reset controller driver for HSDK board.
115
Neil Armstrong4f03d6b2018-03-29 14:55:25 +0200[diff] [blame]116config RESET_MESON
117 bool "Reset controller driver for Amlogic Meson SoCs"
118 depends on DM_RESET && ARCH_MESON
119 imply REGMAP
120 default y
121 help
122 Support for reset controller on Amlogic Meson SoC.
123
Dinh Nguyen5427f5a2018-04-04 17:18:20 -0500[diff] [blame]124config RESET_SOCFPGA
125 bool "Reset controller driver for SoCFPGA"
126 depends on DM_RESET && ARCH_SOCFPGA
127 default y
128 help
129 Support for reset controller on SoCFPGA platform.
130
developerd48dd9a2018-12-20 16:12:51 +0800[diff] [blame]131config RESET_MEDIATEK
132 bool "Reset controller driver for MediaTek SoCs"
133 depends on DM_RESET && ARCH_MEDIATEK && CLK
134 default y
135 help
136 Support for reset controller on MediaTek SoCs.
137
developer074393a2019-09-25 17:45:29 +0800[diff] [blame]138config RESET_MTMIPS
139 bool "Reset controller driver for MediaTek MIPS platform"
140 depends on DM_RESET && ARCH_MTMIPS
141 default y
142 help
143 Support for reset controller on MediaTek MIPS platform.
144
Jim Liueb08c4b2024-01-03 15:29:33 +0800[diff] [blame]145config RESET_NPCM
146 bool "Reset controller driver for Nuvoton BMCs"
147 depends on DM_RESET && ARCH_NPCM
148 default y
149 help
150 Support for reset controller on Nuvotom BMCs.
151
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]152config RESET_SUNXI
153 bool "RESET support for Allwinner SoCs"
154 depends on DM_RESET && ARCH_SUNXI
155 default y
156 help
157 This enables support for common reset driver for
158 Allwinner SoCs.
159
Shawn Guo8aa8f302019-03-20 15:32:39 +0800[diff] [blame]160config RESET_HISILICON
161 bool "Reset controller driver for HiSilicon SoCs"
162 depends on DM_RESET
163 help
164 Support for reset controller on HiSilicon SoCs.
165
Patrick Wildtdbc644f2019-10-03 16:08:35 +0200[diff] [blame]166config RESET_IMX7
167 bool "i.MX7/8 Reset Driver"
168 depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M)
169 default y
170 help
171 Support for reset controller on i.MX7/8 SoCs.
172
Sagar Shrikant Kadam2732b2d2020-07-29 02:36:14 -0700[diff] [blame]173config RESET_SIFIVE
174 bool "Reset Driver for SiFive SoC's"
Green Wan2e5da522021-05-27 06:52:13 -0700[diff] [blame]175 depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED)
Sagar Shrikant Kadam2732b2d2020-07-29 02:36:14 -0700[diff] [blame]176 default y
177 help
178 PRCI module within SiFive SoC's provides mechanism to reset
179 different hw blocks like DDR, gemgxl. With this driver we leverage
180 U-Boot's reset framework to reset these hardware blocks.
181
Yanhong Wangb417f062023-03-29 11:42:11 +0800[diff] [blame]182config RESET_JH7110
183 bool "Reset driver for StarFive JH7110 SoC"
184 depends on DM_RESET && STARFIVE_JH7110
185 default y
186 help
187 Support for reset controller on StarFive
188 JH7110 SoCs.
189
190config SPL_RESET_JH7110
191 bool "SPL Reset driver for StarFive JH7110 SoC"
192 depends on SPL && STARFIVE_JH7110
193 default y
194 help
195 Support for reset controller on StarFive
196 JH7110 SoCs in SPL.
197
Sean Anderson0c1f6bf2020-06-24 06:41:14 -0400[diff] [blame]198config RESET_SYSCON
199 bool "Enable generic syscon reset driver support"
200 depends on DM_RESET
201 help
202 Support generic syscon mapped register reset devices.
Nicolas Saenz Julienne057bbbd2020-06-29 18:37:23 +0200[diff] [blame]203
204config RESET_RASPBERRYPI
205 bool "Raspberry Pi 4 Firmware Reset Controller Driver"
206 depends on DM_RESET && ARCH_BCM283X
207 default USB_XHCI_PCI
208 help
209 Raspberry Pi 4's co-processor controls some of the board's HW
210 initialization process, but it's up to Linux to trigger it when
211 relevant. This driver provides a reset controller capable of
212 interfacing with RPi4's co-processor and model these firmware
213 initialization routines as reset lines.
Etienne Carrierec6e9af32020-09-09 18:44:06 +0200[diff] [blame]214
215config RESET_SCMI
216 bool "Enable SCMI reset domain driver"
217 select SCMI_FIRMWARE
218 help
219 Enable this option if you want to support reset controller
220 devices exposed by a SCMI agent based on SCMI reset domain
221 protocol communication with a SCMI server.
Michal Simekf0e47692021-07-30 08:00:10 +0200[diff] [blame]222
223config RESET_ZYNQMP
T Karthik Reddya3a4cc82022-07-20 03:59:57 -0600[diff] [blame]224 bool "Reset Driver for Xilinx ZynqMP & Versal SoC's"
Michal Simekf0e47692021-07-30 08:00:10 +0200[diff] [blame]225 depends on DM_RESET && ZYNQMP_FIRMWARE
226 help
T Karthik Reddya3a4cc82022-07-20 03:59:57 -0600[diff] [blame]227 Support for reset controller on Xilinx ZynqMP & Versal SoC's. Driver
228 is only passing request via Xilinx firmware interface to TF-A and PMU
Michal Simekf0e47692021-07-30 08:00:10 +0200[diff] [blame]229 firmware.
230
Keerthy0c0bdbb2022-01-27 13:16:51 +0100[diff] [blame]231config RESET_DRA7
232 bool "Support for TI's DRA7 Reset driver"
233 depends on DM_RESET
234 help
235 Support for TI DRA7-RESET subsystem. Basic Assert/Deassert
236 is supported.
Sergiu Mogabdcfc7d2023-01-04 16:03:18 +0200[diff] [blame]237
238config RESET_AT91
239 bool "Enable support for Microchip/Atmel Reset Controller driver"
240 depends on DM_RESET && ARCH_AT91
241 help
242 This enables the Reset Controller driver support for Microchip/Atmel
243 SoCs. Mainly used to expose assert/deassert methods to other drivers
244 that require it.
Paul Barkerc8196982025-03-11 20:57:43 +0000[diff] [blame]245
246config RESET_RZG2L_USBPHY_CTRL
247 bool "Enable support for Renesas RZ/G2L USB 2.0 PHY control"
248 depends on DM_RESET
Paul Barkerced6d032025-03-11 20:57:45 +0000[diff] [blame]249 select REGULATOR_RZG2L_USBPHY
Paul Barkerc8196982025-03-11 20:57:43 +0000[diff] [blame]250 help
251 Enable support for controlling USB 2.0 PHY resets on the Renesas
252 RZ/G2L SoC. This is required for USB 2.0 functionality to work on this
253 SoC.
254
Huan Zhou10ad7982025-03-11 09:38:49 +0800[diff] [blame]255config RESET_SPACEMIT_K1
256 bool "Support for SPACEMIT's K1 Reset driver"
257 depends on DM_RESET
258 help
259 Support for SPACEMIT's K1 Reset system. Basic Assert/Deassert
260 is supported.
Stephen Warren185ad872016-06-17 09:43:58 -0600[diff] [blame]261endmenu