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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / drivers / pinctrl / mediatek / pinctrl-mt7987.c
blob: db672d26798b21cb72d6617cfc6d6c61fb55a91d [file] [log] [blame]
developere08e7052025-01-23 16:54:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2024 MediaTek Inc.
4 * Author: Tim.Kuo <tim.kuo@mediatek.com>
5 */
6
7#include <dm.h>
8#include "pinctrl-mtk-common.h"
9
10enum MT7987_PINCTRL_REG_PAGE {
11 GPIO_BASE,
12 IOCFG_RB_BASE,
13 IOCFG_LB_BASE,
14 IOCFG_RT1_BASE,
15 IOCFG_RT2_BASE,
16 IOCFG_TL_BASE,
17};
18
19/*
20 * IO_TYPE_GRP0 / IO_TYPE_GRP1
21 * MT7987 pins can be divided into two groups:
22 * - PUPD_R0_R1
23 * - PU/PD
24 * Here, we divide pins with PU/PD to be IO_TYPE_GRP0 and those with PUPD_R0_R1
25 * to be IO_TYPE_GRP1.
26 * - PUPD_R0_R1 : IO_TYPE_GRP0
27 * - PU/PD : IO_TYPE_GRP1
28 * DRV_GRP4
29 * For MT7987, thr driving of pins can start from 2mA and increase by 2mA
30 * increments up to 16mA.
31 */
32#define MT7987_TYPE0_PIN(_number, _name) \
33 MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
34
35#define MT7987_TYPE1_PIN(_number, _name) \
36 MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
37
38#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
39 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \
40 _s_bit, _x_bits, 32, 0)
41
42#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
43 _x_bits) \
44 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
45 _s_bit, _x_bits, 32, 0)
46
47#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
48 _x_bits) \
49 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
50 _s_bit, _x_bits, 32, 1)
51
52static const struct mtk_pin_field_calc mt7987_pin_mode_range[] = {
53 PIN_FIELD_GPIO(0, 49, 0x300, 0x10, 0, 4),
54};
55
56static const struct mtk_pin_field_calc mt7987_pin_dir_range[] = {
57 PIN_FIELD_GPIO(0, 49, 0x0, 0x10, 0, 1),
58};
59
60static const struct mtk_pin_field_calc mt7987_pin_di_range[] = {
61 PIN_FIELD_GPIO(0, 49, 0x200, 0x10, 0, 1),
62};
63
64static const struct mtk_pin_field_calc mt7987_pin_do_range[] = {
65 PIN_FIELD_GPIO(0, 49, 0x100, 0x10, 0, 1),
66};
67
68static const struct mtk_pin_field_calc mt7987_pin_ies_range[] = {
69 PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x20, 0x10, 3, 1),
70 PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x20, 0x10, 2, 1),
71 PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x20, 0x10, 11, 1),
72 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x20, 0x10, 2, 1),
73 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x20, 0x10, 1, 1),
74 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x20, 0x10, 3, 1),
75 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x20, 0x10, 0, 1),
76 PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x20, 0x10, 4, 1),
77 PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x10, 0x10, 2, 1),
78 PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x10, 0x10, 1, 1),
79 PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x10, 0x10, 0, 1),
80 PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x10, 0x10, 3, 1),
81 PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x10, 0x10, 4, 1),
82 PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x20, 0x10, 0, 1),
83 PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x20, 0x10, 15, 1),
84 PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x20, 0x10, 3, 1),
85 PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x20, 0x10, 7, 1),
86 PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x20, 0x10, 6, 1),
87 PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x20, 0x10, 4, 1),
88 PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x20, 0x10, 5, 1),
89 PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x20, 0x10, 8, 1),
90 PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x20, 0x10, 9, 1),
91 PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x20, 0x10, 12, 1),
92 PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x20, 0x10, 11, 1),
93 PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x20, 0x10, 10, 1),
94 PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x20, 0x10, 13, 1),
95 PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x20, 0x10, 14, 1),
96 PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x20, 0x10, 9, 1),
97 PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x20, 0x10, 7, 1),
98 PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x20, 0x10, 8, 1),
99 PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x20, 0x10, 10, 1),
100 PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x20, 0x10, 5, 1),
101 PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x20, 0x10, 6, 1),
102 PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
103 PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
104 PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x20, 0x10, 4, 1),
105 PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x20, 0x10, 3, 1),
106 PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x20, 0x10, 1, 1),
107 PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x20, 0x10, 5, 1),
108 PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x20, 0x10, 1, 1),
109 PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x20, 0x10, 2, 1),
110 PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x20, 0x10, 0, 1),
111 PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x20, 0x10, 1, 1),
112 PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x20, 0x10, 4, 1),
113 PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x20, 0x10, 5, 1),
114 PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x20, 0x10, 6, 1),
115 PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x20, 0x10, 9, 1),
116 PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x20, 0x10, 10, 1),
117 PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x20, 0x10, 7, 1),
118 PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x20, 0x10, 8, 1),
119};
120
121static const struct mtk_pin_field_calc mt7987_pin_smt_range[] = {
122 PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x90, 0x10, 3, 1),
123 PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x90, 0x10, 2, 1),
124 PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x90, 0x10, 11, 1),
125 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x90, 0x10, 2, 1),
126 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x90, 0x10, 1, 1),
127 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x90, 0x10, 3, 1),
128 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x90, 0x10, 0, 1),
129 PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x90, 0x10, 4, 1),
130 PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
131 PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
132 PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
133 PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
134 PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
135 PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0xA0, 0x10, 0, 1),
136 PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0xA0, 0x10, 15, 1),
137 PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0xA0, 0x10, 3, 1),
138 PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0xA0, 0x10, 7, 1),
139 PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0xA0, 0x10, 6, 1),
140 PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0xA0, 0x10, 4, 1),
141 PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0xA0, 0x10, 5, 1),
142 PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0xA0, 0x10, 8, 1),
143 PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0xA0, 0x10, 9, 1),
144 PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0xA0, 0x10, 12, 1),
145 PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0xA0, 0x10, 11, 1),
146 PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0xA0, 0x10, 10, 1),
147 PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0xA0, 0x10, 13, 1),
148 PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0xA0, 0x10, 14, 1),
149 PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x90, 0x10, 9, 1),
150 PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x90, 0x10, 7, 1),
151 PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x90, 0x10, 8, 1),
152 PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x90, 0x10, 10, 1),
153 PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x90, 0x10, 5, 1),
154 PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x90, 0x10, 6, 1),
155 PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
156 PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
157 PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
158 PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
159 PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
160 PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
161 PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0xA0, 0x10, 1, 1),
162 PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0xA0, 0x10, 2, 1),
163 PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x90, 0x10, 0, 1),
164 PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x90, 0x10, 1, 1),
165 PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x90, 0x10, 4, 1),
166 PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x90, 0x10, 5, 1),
167 PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x90, 0x10, 6, 1),
168 PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x90, 0x10, 9, 1),
169 PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x90, 0x10, 10, 1),
170 PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x90, 0x10, 7, 1),
171 PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x90, 0x10, 8, 1),
172};
173
174static const struct mtk_pin_field_calc mt7987_pin_pu_range[] = {
175 PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
176 PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
177 PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
178 PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
179 PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
180 PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
181};
182
183static const struct mtk_pin_field_calc mt7987_pin_pd_range[] = {
184 PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
185 PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
186 PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
187 PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
188 PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
189 PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
190};
191
192static const struct mtk_pin_field_calc mt7987_pin_drv_range[] = {
193 PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x0, 0x10, 9, 3),
194 PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x0, 0x10, 6, 3),
195 PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x10, 0x10, 3, 3),
196 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x0, 0x10, 6, 3),
197 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x0, 0x10, 3, 3),
198 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x0, 0x10, 9, 3),
199 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x0, 0x10, 0, 3),
200 PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x0, 0x10, 12, 3),
201 PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x0, 0x10, 6, 3),
202 PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x0, 0x10, 3, 3),
203 PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x0, 0x10, 0, 3),
204 PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x0, 0x10, 9, 3),
205 PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x0, 0x10, 12, 3),
206 PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x0, 0x10, 0, 3),
207 PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x10, 0x10, 15, 3),
208 PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x0, 0x10, 9, 3),
209 PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x0, 0x10, 21, 3),
210 PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x0, 0x10, 18, 3),
211 PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x0, 0x10, 12, 3),
212 PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x0, 0x10, 15, 3),
213 PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x0, 0x10, 24, 3),
214 PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x0, 0x10, 27, 3),
215 PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x10, 0x10, 6, 3),
216 PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x10, 0x10, 3, 3),
217 PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x10, 0x10, 0, 3),
218 PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x10, 0x10, 9, 3),
219 PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x10, 0x10, 12, 3),
220 PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x0, 0x10, 27, 3),
221 PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x0, 0x10, 21, 3),
222 PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x0, 0x10, 24, 3),
223 PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x10, 0x10, 0, 3),
224 PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x0, 0x10, 15, 3),
225 PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x0, 0x10, 18, 3),
226 PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x0, 0x10, 6, 3),
227 PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x0, 0x10, 0, 3),
228 PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x0, 0x10, 12, 3),
229 PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x0, 0x10, 9, 3),
230 PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x0, 0x10, 3, 3),
231 PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x0, 0x10, 15, 3),
232 PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x0, 0x10, 3, 3),
233 PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x0, 0x10, 6, 3),
234 PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x0, 0x10, 0, 3),
235 PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x0, 0x10, 3, 3),
236 PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x0, 0x10, 12, 3),
237 PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x0, 0x10, 15, 3),
238 PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x0, 0x10, 18, 3),
239 PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x0, 0x10, 27, 3),
240 PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x10, 0x10, 0, 3),
241 PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x0, 0x10, 21, 3),
242 PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x0, 0x10, 24, 3),
243};
244
245static const struct mtk_pin_field_calc mt7987_pin_pupd_range[] = {
246 PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x30, 0x10, 3, 1),
247 PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x30, 0x10, 2, 1),
248 PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x30, 0x10, 11, 1),
249 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
250 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
251 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
252 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
253 PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
254 PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x20, 0x10, 2, 1),
255 PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x20, 0x10, 1, 1),
256 PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x20, 0x10, 0, 1),
257 PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x20, 0x10, 3, 1),
258 PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x20, 0x10, 4, 1),
259 PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x30, 0x10, 0, 1),
260 PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x30, 0x10, 15, 1),
261 PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x30, 0x10, 3, 1),
262 PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x30, 0x10, 7, 1),
263 PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x30, 0x10, 6, 1),
264 PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x30, 0x10, 4, 1),
265 PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x30, 0x10, 5, 1),
266 PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x30, 0x10, 8, 1),
267 PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x30, 0x10, 9, 1),
268 PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x30, 0x10, 12, 1),
269 PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x30, 0x10, 11, 1),
270 PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x30, 0x10, 10, 1),
271 PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x30, 0x10, 13, 1),
272 PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x30, 0x10, 14, 1),
273 PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x30, 0x10, 9, 1),
274 PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x30, 0x10, 7, 1),
275 PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x30, 0x10, 8, 1),
276 PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x30, 0x10, 10, 1),
277 PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
278 PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
279
280 PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x30, 0x10, 1, 1),
281 PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x30, 0x10, 2, 1),
282 PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x30, 0x10, 0, 1),
283 PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x30, 0x10, 1, 1),
284 PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x30, 0x10, 4, 1),
285 PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x30, 0x10, 5, 1),
286 PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x30, 0x10, 6, 1),
287 PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
288 PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
289 PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
290 PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
291};
292
293static const struct mtk_pin_field_calc mt7987_pin_r0_range[] = {
294 PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x40, 0x10, 3, 1),
295 PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x40, 0x10, 2, 1),
296 PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x40, 0x10, 11, 1),
297 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
298 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
299 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
300 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
301 PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
302 PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x30, 0x10, 2, 1),
303 PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x30, 0x10, 1, 1),
304 PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x30, 0x10, 0, 1),
305 PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x30, 0x10, 3, 1),
306 PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x30, 0x10, 4, 1),
307 PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x40, 0x10, 0, 1),
308 PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x40, 0x10, 15, 1),
309 PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x40, 0x10, 3, 1),
310 PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x40, 0x10, 7, 1),
311 PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x40, 0x10, 6, 1),
312 PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x40, 0x10, 4, 1),
313 PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x40, 0x10, 5, 1),
314 PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x40, 0x10, 8, 1),
315 PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x40, 0x10, 9, 1),
316 PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x40, 0x10, 12, 1),
317 PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x40, 0x10, 11, 1),
318 PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x40, 0x10, 10, 1),
319 PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x40, 0x10, 13, 1),
320 PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x40, 0x10, 14, 1),
321 PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x40, 0x10, 9, 1),
322 PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x40, 0x10, 7, 1),
323 PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x40, 0x10, 8, 1),
324 PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x40, 0x10, 10, 1),
325 PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
326 PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x40, 0x10, 6, 1),
327
328 PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x40, 0x10, 1, 1),
329 PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x40, 0x10, 2, 1),
330 PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x40, 0x10, 0, 1),
331 PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x40, 0x10, 1, 1),
332 PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x40, 0x10, 4, 1),
333 PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x40, 0x10, 5, 1),
334 PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x40, 0x10, 6, 1),
335 PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x40, 0x10, 9, 1),
336 PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x40, 0x10, 10, 1),
337 PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x40, 0x10, 7, 1),
338 PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
339};
340
341static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = {
342 PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x50, 0x10, 3, 1),
343 PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x50, 0x10, 2, 1),
344 PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x50, 0x10, 11, 1),
345 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
346 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
347 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
348 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
349 PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
350 PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
351 PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x40, 0x10, 1, 1),
352 PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
353 PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 3, 1),
354 PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 4, 1),
355 PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x50, 0x10, 0, 1),
356 PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x50, 0x10, 15, 1),
357 PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x50, 0x10, 3, 1),
358 PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x50, 0x10, 7, 1),
359 PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x50, 0x10, 6, 1),
360 PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x50, 0x10, 4, 1),
361 PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x50, 0x10, 5, 1),
362 PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x50, 0x10, 8, 1),
363 PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x50, 0x10, 9, 1),
364 PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x50, 0x10, 12, 1),
365 PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x50, 0x10, 11, 1),
366 PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x50, 0x10, 10, 1),
367 PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x50, 0x10, 13, 1),
368 PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x50, 0x10, 14, 1),
369 PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x50, 0x10, 9, 1),
370 PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x50, 0x10, 7, 1),
371 PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x50, 0x10, 8, 1),
372 PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x50, 0x10, 10, 1),
373 PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
374 PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
375
376 PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x50, 0x10, 1, 1),
377 PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x50, 0x10, 2, 1),
378 PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x50, 0x10, 0, 1),
379 PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x50, 0x10, 1, 1),
380 PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x50, 0x10, 4, 1),
381 PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x50, 0x10, 5, 1),
382 PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x50, 0x10, 6, 1),
383 PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x50, 0x10, 9, 1),
384 PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x50, 0x10, 10, 1),
385 PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
386 PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
387};
388
389static const struct mtk_pin_reg_calc mt7987_reg_cals[] = {
390 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range),
391 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range),
392 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range),
393 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7987_pin_do_range),
394 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7987_pin_smt_range),
395 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7987_pin_ies_range),
396 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7987_pin_pu_range),
397 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7987_pin_pd_range),
398 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7987_pin_drv_range),
399 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7987_pin_pupd_range),
400 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7987_pin_r0_range),
401 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7987_pin_r1_range),
402};
403
404static const struct mtk_pin_desc mt7987_pins[] = {
405 MT7987_TYPE0_PIN(0, "GPIO_WPS"),
406 MT7987_TYPE0_PIN(1, "GPIO_RESET"),
407 MT7987_TYPE0_PIN(2, "SYS_WATCHDOG"),
408 MT7987_TYPE0_PIN(3, "JTAG_JTDO"),
409 MT7987_TYPE0_PIN(4, "JTAG_JTDI"),
410 MT7987_TYPE0_PIN(5, "JTAG_JTMS"),
411 MT7987_TYPE0_PIN(6, "JTAG_JTCLK"),
412 MT7987_TYPE0_PIN(7, "JTAG_JTRST_N"),
413 MT7987_TYPE0_PIN(8, "PCM_DTX_I2S_DOUT"),
414 MT7987_TYPE0_PIN(9, "PCM_DRX_I2S_DIN"),
415 MT7987_TYPE0_PIN(10, "PCM_CLK_I2S_BCLK"),
416 MT7987_TYPE0_PIN(11, "PCM_FS_I2S_LRCK"),
417 MT7987_TYPE0_PIN(12, "PCM_MCK_I2S_MCLK"),
418 MT7987_TYPE0_PIN(13, "PWM0"),
419 MT7987_TYPE0_PIN(14, "USB_VBUS"),
420 MT7987_TYPE0_PIN(15, "SPI0_CLK"),
421 MT7987_TYPE0_PIN(16, "SPI0_MOSI"),
422 MT7987_TYPE0_PIN(17, "SPI0_MISO"),
423 MT7987_TYPE0_PIN(18, "SPI0_CS"),
424 MT7987_TYPE0_PIN(19, "SPI0_HOLD"),
425 MT7987_TYPE0_PIN(20, "SPI0_WP"),
426 MT7987_TYPE0_PIN(21, "SPI1_CLK"),
427 MT7987_TYPE0_PIN(22, "SPI1_MOSI"),
428 MT7987_TYPE0_PIN(23, "SPI1_MISO"),
429 MT7987_TYPE0_PIN(24, "SPI1_CS"),
430 MT7987_TYPE0_PIN(25, "SPI2_CLK"),
431 MT7987_TYPE0_PIN(26, "SPI2_MOSI"),
432 MT7987_TYPE0_PIN(27, "SPI2_MISO"),
433 MT7987_TYPE0_PIN(28, "SPI2_CS"),
434 MT7987_TYPE0_PIN(29, "SPI2_HOLD"),
435 MT7987_TYPE0_PIN(30, "SPI2_WP"),
436 MT7987_TYPE0_PIN(31, "UART0_RXD"),
437 MT7987_TYPE0_PIN(32, "UART0_TXD"),
438 MT7987_TYPE1_PIN(33, "PCIE_PERESET_N_0"),
439 MT7987_TYPE1_PIN(34, "PCIE_CLK_REQ_0"),
440 MT7987_TYPE1_PIN(35, "PCIE_WAKE_N_0"),
441 MT7987_TYPE1_PIN(36, "PCIE_PERESET_N_1"),
442 MT7987_TYPE1_PIN(37, "PCIE_CLK_REQ_1"),
443 MT7987_TYPE1_PIN(38, "PCIE_WAKE_N_1"),
444 MT7987_TYPE0_PIN(39, "SMI_MDC"),
445 MT7987_TYPE0_PIN(40, "SMI_MDIO"),
446 MT7987_TYPE0_PIN(41, "GBE_INT"),
447 MT7987_TYPE0_PIN(42, "GBE_RESET"),
448 MT7987_TYPE0_PIN(43, "I2C_SCLK"),
449 MT7987_TYPE0_PIN(44, "I2C_SDATA"),
450 MT7987_TYPE0_PIN(45, "2P5G_LED0"),
451 MT7987_TYPE0_PIN(46, "UART1_RXD"),
452 MT7987_TYPE0_PIN(47, "UART1_TXD"),
453 MT7987_TYPE0_PIN(48, "UART1_CTS"),
454 MT7987_TYPE0_PIN(49, "UART1_RTS"),
455};
456
457/* watchdog */
458static const int mt7987_watchdog_pins[] = {2};
459static const int mt7987_watchdog_funcs[] = {1};
460
461/* jtag */
462static const int mt7987_jtag_pins[] = {3, 4, 5, 6, 7};
463static const int mt7987_jtag_funcs[] = {1, 1, 1, 1, 1};
464
465/* pcm */
466static const int mt7987_pcm0_0_pins[] = {3, 4, 5, 6, 7};
467static const int mt7987_pcm0_0_funcs[] = {2, 2, 2, 2, 2};
468
469static const int mt7987_pcm0_1_pins[] = {8, 9, 10, 11, 12};
470static const int mt7987_pcm0_1_funcs[] = {1, 1, 1, 1, 1};
471
472/* uart */
473static const int mt7987_uart0_pins[] = {31, 32};
474static const int mt7987_uart0_funcs[] = {1, 1};
475
476static const int mt7987_uart1_0_pins[] = {3, 4, 5, 6};
477static const int mt7987_uart1_0_funcs[] = {3, 3, 3, 3};
478
479static const int mt7987_uart1_1_pins[] = {21, 22, 23, 24};
480static const int mt7987_uart1_1_funcs[] = {3, 3, 3, 3};
481
482static const int mt7987_uart1_2_pins[] = {46, 47, 48, 49};
483static const int mt7987_uart1_2_funcs[] = {1, 1, 1, 1};
484
485static const int mt7987_uart2_0_pins[] = {8, 9, 10, 11};
486static const int mt7987_uart2_0_funcs[] = {2, 2, 2, 2};
487
488static const int mt7987_uart2_1_pins[] = {25, 26, 27, 28};
489static const int mt7987_uart2_1_funcs[] = {2, 2, 2, 2};
490
491/* pwm */
492static const int mt7987_pwm0_pins[] = {13};
493static const int mt7987_pwm0_funcs[] = {1};
494
495static const int mt7987_pwm1_0_pins[] = {7};
496static const int mt7987_pwm1_0_funcs[] = {3};
497
498static const int mt7987_pwm1_1_pins[] = {43};
499static const int mt7987_pwm1_1_funcs[] = {2};
500
501static const int mt7987_pwm2_0_pins[] = {12};
502static const int mt7987_pwm2_0_funcs[] = {2};
503
504static const int mt7987_pwm2_1_pins[] = {44};
505static const int mt7987_pwm2_1_funcs[] = {2};
506
507/* vbus */
508static const int mt7987_drv_vbus_p1_pins[] = {14};
509static const int mt7987_drv_vbus_p1_funcs[] = {1};
510
511static const int mt7987_drv_vbus_pins[] = {48};
512static const int mt7987_drv_vbus_funcs[] = {3};
513
514/* 2p5gbe_led */
515static const int mt7987_2p5gbe_led0_pins[] = {45};
516static const int mt7987_2p5gbe_led0_funcs[] = {1};
517
518static const int mt7987_2p5gbe_led1_0_pins[] = {13};
519static const int mt7987_2p5gbe_led1_0_funcs[] = {2};
520
521static const int mt7987_2p5gbe_led1_1_pins[] = {49};
522static const int mt7987_2p5gbe_led1_1_funcs[] = {3};
523
524/* mdc, mdio */
525static const int mt7987_2p5g_ext_mdc_mdio_pins[] = {23, 24};
526static const int mt7987_2p5g_ext_mdc_mdio_funcs[] = {4, 4};
527
528static const int mt7987_mdc_mdio_pins[] = {39, 40};
529static const int mt7987_mdc_mdio_funcs[] = {1, 1};
530
531/* spi */
532static const int mt7987_spi0_pins[] = {15, 16, 17, 18};
533static const int mt7987_spi0_funcs[] = {1, 1, 1, 1};
534
535static const int mt7987_spi0_wp_hold_pins[] = {19, 20};
536static const int mt7987_spi0_wp_hold_funcs[] = {1, 1};
537
538static const int mt7987_spi1_pins[] = {21, 22, 23, 24};
539static const int mt7987_spi1_funcs[] = {1, 1, 1, 1};
540
541static const int mt7987_spi1_1_pins[] = {46, 47, 48, 49};
542static const int mt7987_spi1_1_funcs[] = {2, 2, 2, 2};
543
544static const int mt7987_spi2_pins[] = {25, 26, 27, 28};
545static const int mt7987_spi2_funcs[] = {1, 1, 1, 1};
546
547static const int mt7987_spi2_wp_hold_pins[] = {29, 30};
548static const int mt7987_spi2_wp_hold_funcs[] = {1, 1};
549
550/* emmc */
551static const int mt7987_emmc_45_pins[] = {14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24};
552static const int mt7987_emmc_45_funcs[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2};
553
554/* sd */
555static const int mt7987_sd_pins[] = {15, 16, 17, 18, 23, 24};
556static const int mt7987_sd_funcs[] = {2, 2, 2, 2, 2, 2};
557
558/* i2c */
559static const int mt7987_i2c0_0_pins[] = {29, 30};
560static const int mt7987_i2c0_0_funcs[] = {2, 2};
561
562static const int mt7987_i2c0_1_pins[] = {39, 40};
563static const int mt7987_i2c0_1_funcs[] = {2, 2};
564
565static const int mt7987_i2c0_2_pins[] = {43, 44};
566static const int mt7987_i2c0_2_funcs[] = {1, 1};
567
568/* pcie */
569static const int mt7987_pcie0_pereset_pins[] = {33};
570static const int mt7987_pcie0_pereset_funcs[] = {1};
571
572static const int mt7987_pcie0_clkreq_pins[] = {34};
573static const int mt7987_pcie0_clkreq_funcs[] = {1};
574
575static const int mt7987_pcie0_wake_pins[] = {35};
576static const int mt7987_pcie0_wake_funcs[] = {1};
577
578static const int mt7987_pcie1_pereset_pins[] = {36};
579static const int mt7987_pcie1_pereset_funcs[] = {1};
580
581static const int mt7987_pcie1_clkreq_pins[] = {37};
582static const int mt7987_pcie1_clkreq_funcs[] = {1};
583
584static const int mt7987_pcie1_wake_pins[] = {38};
585static const int mt7987_pcie1_wake_funcs[] = {1};
586
587static const int mt7987_pcie_phy_i2c_pins[] = {43, 44};
588static const int mt7987_pcie_phy_i2c_funcs[] = {3, 3};
589
590/* snfi */
591static const int mt7987_snfi_pins[] = {25, 26, 27, 28, 29, 30};
592static const int mt7987_snfi_funcs[] = {3, 3, 3, 3, 3, 3};
593
594/*
595 * - int hsgmii :
596 * For pin41 and pin46, they now can only be used as gpio mode for polling
597 * event. Hence, there's no need to open their pinctrl setting.
598 * - dfd, udi :
599 * Due to dfd & udi functions are only used as detection pins for cpu during
600 * dvt testing stage, we also remove their pinctrl setting.
601 */
602
603static const struct mtk_group_desc mt7987_groups[] = {
604 PINCTRL_PIN_GROUP("watchdog", mt7987_watchdog),
605 PINCTRL_PIN_GROUP("jtag", mt7987_jtag),
606 PINCTRL_PIN_GROUP("pcm0_0", mt7987_pcm0_0),
607 PINCTRL_PIN_GROUP("pcm0_1", mt7987_pcm0_1),
608 PINCTRL_PIN_GROUP("uart0", mt7987_uart0),
609 PINCTRL_PIN_GROUP("uart1_0", mt7987_uart1_0),
610 PINCTRL_PIN_GROUP("uart1_1", mt7987_uart1_1),
611 PINCTRL_PIN_GROUP("uart1_2", mt7987_uart1_2),
612 PINCTRL_PIN_GROUP("uart2_0", mt7987_uart2_0),
613 PINCTRL_PIN_GROUP("uart2_1", mt7987_uart2_1),
614 PINCTRL_PIN_GROUP("pwm0", mt7987_pwm0),
615 PINCTRL_PIN_GROUP("pwm1_0", mt7987_pwm1_0),
616 PINCTRL_PIN_GROUP("pwm1_1", mt7987_pwm1_1),
617 PINCTRL_PIN_GROUP("pwm2_0", mt7987_pwm2_0),
618 PINCTRL_PIN_GROUP("pwm2_1", mt7987_pwm2_1),
619 PINCTRL_PIN_GROUP("drv_vbus_p1", mt7987_drv_vbus_p1),
620 PINCTRL_PIN_GROUP("drv_vbus", mt7987_drv_vbus),
621 PINCTRL_PIN_GROUP("2p5gbe_led0", mt7987_2p5gbe_led0),
622 PINCTRL_PIN_GROUP("2p5gbe_led1_0", mt7987_2p5gbe_led1_0),
623 PINCTRL_PIN_GROUP("2p5gbe_led1_1", mt7987_2p5gbe_led1_1),
624 PINCTRL_PIN_GROUP("2p5g_ext_mdc_mdio", mt7987_2p5g_ext_mdc_mdio),
625 PINCTRL_PIN_GROUP("mdc_mdio", mt7987_mdc_mdio),
626 PINCTRL_PIN_GROUP("spi0", mt7987_spi0),
627 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7987_spi0_wp_hold),
628 PINCTRL_PIN_GROUP("spi1", mt7987_spi1),
629 PINCTRL_PIN_GROUP("spi1_1", mt7987_spi1_1),
630 PINCTRL_PIN_GROUP("spi2", mt7987_spi2),
631 PINCTRL_PIN_GROUP("spi2_wp_hold", mt7987_spi2_wp_hold),
632 PINCTRL_PIN_GROUP("emmc_45", mt7987_emmc_45),
633 PINCTRL_PIN_GROUP("sd", mt7987_sd),
634 PINCTRL_PIN_GROUP("i2c0_0", mt7987_i2c0_0),
635 PINCTRL_PIN_GROUP("i2c0_1", mt7987_i2c0_1),
636 PINCTRL_PIN_GROUP("i2c0_2", mt7987_i2c0_2),
637 PINCTRL_PIN_GROUP("pcie_phy_i2c", mt7987_pcie_phy_i2c),
638 PINCTRL_PIN_GROUP("pcie0_pereset", mt7987_pcie0_pereset),
639 PINCTRL_PIN_GROUP("pcie0_clkreq", mt7987_pcie0_clkreq),
640 PINCTRL_PIN_GROUP("pcie0_wake", mt7987_pcie0_wake),
641 PINCTRL_PIN_GROUP("pcie1_pereset", mt7987_pcie1_pereset),
642 PINCTRL_PIN_GROUP("pcie1_clkreq", mt7987_pcie1_clkreq),
643 PINCTRL_PIN_GROUP("pcie1_wake", mt7987_pcie1_wake),
644 PINCTRL_PIN_GROUP("snfi", mt7987_snfi),
645};
646
647static const struct mtk_io_type_desc mt7987_io_type_desc[] = {
648 [IO_TYPE_GRP0] = {
649 .name = "18OD33",
650 .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
651 .drive_set = mtk_pinconf_drive_set_v1,
652 .input_enable = mtk_pinconf_input_enable_v1,
653 },
654 [IO_TYPE_GRP1] = {
655 .name = "18A01",
656 .bias_set = mtk_pinconf_bias_set_pu_pd,
657 .drive_set = mtk_pinconf_drive_set_v1,
658 .input_enable = mtk_pinconf_input_enable_v1,
659 },
660};
661
662static const char *const mt7987_wdt_groups[] = {"watchdog",};
663static const char *const mt7987_jtag_groups[] = {"jtag",};
664static const char *const mt7987_pcm_groups[] = {"pcm0_0", "pcm0_1"};
665static const char *const mt7987_uart_groups[] = {"uart0", "uart1_0", "uart1_1",
666 "uart1_2", "uart2_0", "uart2_1",};
667static const char *const mt7987_pwm_groups[] = {"pwm0", "pwm1_0", "pwm1_1", "pwm2_0",
668 "pwm2_1",};
669static const char *const mt7987_usb_groups[] = {"drv_vbus_p1", "drv_vbus",};
670static const char *const mt7987_led_groups[] = {"2p5gbe_led0", "2p5gbe_led1_0",
671 "2p5gbe_led1_1",};
672static const char *const mt7987_ethernet_groups[] = {"2p5g_ext_mdc_mdio", "mdc_mdio",};
673static const char *const mt7987_spi_groups[] = {"spi0", "spi0_wp_hold", "spi1",
674 "spi1_1", "spi2", "spi2_wp_hold",};
675static const char *const mt7987_flash_groups[] = {"emmc_45", "snfi", "sd",};
676static const char *const mt7987_i2c_groups[] = {"i2c0_0", "i2c0_1", "i2c0_2",};
677static const char *const mt7987_pcie_groups[] = {"pcie_phy_i2c", "pcie0_pereset",
678 "pcie0_clkreq", "pcie0_wake",
679 "pcie1_pereset", "pcie1_clkreq",
680 "pcie1_wake",};
681
682static const struct mtk_function_desc mt7987_functions[] = {
683 {"wdt", mt7987_wdt_groups, ARRAY_SIZE(mt7987_wdt_groups)},
684 {"jtag", mt7987_jtag_groups, ARRAY_SIZE(mt7987_jtag_groups)},
685 {"pcm", mt7987_pcm_groups, ARRAY_SIZE(mt7987_pcm_groups)},
686 {"uart", mt7987_uart_groups, ARRAY_SIZE(mt7987_uart_groups)},
687 {"pwm", mt7987_pwm_groups, ARRAY_SIZE(mt7987_pwm_groups)},
688 {"usb", mt7987_usb_groups, ARRAY_SIZE(mt7987_usb_groups)},
689 {"led", mt7987_led_groups, ARRAY_SIZE(mt7987_led_groups)},
690 {"eth", mt7987_ethernet_groups, ARRAY_SIZE(mt7987_ethernet_groups)},
691 {"spi", mt7987_spi_groups, ARRAY_SIZE(mt7987_spi_groups)},
692 {"flash", mt7987_flash_groups, ARRAY_SIZE(mt7987_flash_groups)},
693 {"i2c", mt7987_i2c_groups, ARRAY_SIZE(mt7987_i2c_groups)},
694 {"pcie", mt7987_pcie_groups, ARRAY_SIZE(mt7987_pcie_groups)},
695};
696
697static const char *const mt7987_pinctrl_register_base_names[] = {
698 "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", "iocfg_rt2", "iocfg_tl",
699};
700
701static const struct mtk_pinctrl_soc mt7987_data = {
702 .name = "mt7987_pinctrl",
703 .reg_cal = mt7987_reg_cals,
704 .pins = mt7987_pins,
705 .npins = ARRAY_SIZE(mt7987_pins),
706 .grps = mt7987_groups,
707 .ngrps = ARRAY_SIZE(mt7987_groups),
708 .funcs = mt7987_functions,
709 .nfuncs = ARRAY_SIZE(mt7987_functions),
710 .io_type = mt7987_io_type_desc,
711 .ntype = ARRAY_SIZE(mt7987_io_type_desc),
712 .gpio_mode = 0,
713 .base_names = mt7987_pinctrl_register_base_names,
714 .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names),
715 .base_calc = 1,
716};
717
718static int mtk_pinctrl_mt7987_probe(struct udevice *dev)
719{
720 return mtk_pinctrl_common_probe(dev, &mt7987_data);
721}
722
723static const struct udevice_id mt7987_pctrl_match[] = {
724 {.compatible = "mediatek,mt7987-pinctrl"},
725 { /* sentinel */ }
726};
727
728U_BOOT_DRIVER(mt7987_pinctrl) = {
729 .name = "mt7987_pinctrl",
730 .id = UCLASS_PINCTRL,
731 .of_match = mt7987_pctrl_match,
732 .ops = &mtk_pinctrl_ops,
733 .bind = mtk_pinctrl_common_bind,
734 .probe = mtk_pinctrl_mt7987_probe,
735 .priv_auto = sizeof(struct mtk_pinctrl_priv),
736};