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Masahiro Yamadaf8efa632015-08-27 12:44:29 +09001#
2# PINCTRL infrastructure and drivers
3#
4
5menu "Pin controllers"
6
7config PINCTRL
8 bool "Support pin controllers"
9 depends on DM
10 help
11 This enables the basic support for pinctrl framework. You may want
12 to enable some more options depending on what you want to do.
13
14config PINCTRL_FULL
15 bool "Support full pin controllers"
16 depends on PINCTRL && OF_CONTROL
17 default y
18 help
19 This provides Linux-compatible device tree interface for the pinctrl
20 subsystem. This feature depends on device tree configuration because
21 it parses a device tree to look for the pinctrl device which the
22 peripheral device is associated with.
23
24 If this option is disabled (it is the only possible choice for non-DT
25 boards), the pinctrl core provides no systematic mechanism for
26 identifying peripheral devices, applying needed pinctrl settings.
27 It is totally up to the implementation of each low-level driver.
28 You can save memory footprint in return for some limitations.
29
30config PINCTRL_GENERIC
31 bool "Support generic pin controllers"
32 depends on PINCTRL_FULL
33 default y
34 help
35 Say Y here if you want to use the pinctrl subsystem through the
36 generic DT interface. If enabled, some functions become available
37 to parse common properties such as "pins", "groups", "functions" and
38 some pin configuration parameters. It would be easier if you only
39 need the generic DT interface for pin muxing and pin configuration.
40 If you need to handle vendor-specific DT properties, you can disable
41 this option and implement your own set_state callback in the pinctrl
42 operations.
43
44config PINMUX
45 bool "Support pin multiplexing controllers"
46 depends on PINCTRL_GENERIC
47 default y
48 help
49 This option enables pin multiplexing through the generic pinctrl
Marek BehĂșn44f62e92018-03-02 09:56:00 +010050 framework. Most SoCs have their own multiplexing arrangement where
51 a single pin can be used for several functions. An SoC pinctrl driver
52 allows the required function to be selected for each pin.
Simon Glass8d6510d2015-08-30 16:55:12 -060053 The driver is typically controlled by the device tree.
Masahiro Yamadaf8efa632015-08-27 12:44:29 +090054
55config PINCONF
56 bool "Support pin configuration controllers"
57 depends on PINCTRL_GENERIC
58 help
59 This option enables pin configuration through the generic pinctrl
60 framework.
61
Patrick Delaunaybcdb1042019-08-02 14:48:00 +020062config PINCONF_RECURSIVE
63 bool "Support recursive binding for pin configuration nodes"
64 depends on PINCTRL_FULL
65 default n if ARCH_STM32MP
66 default y
67 help
68 In the Linux pinctrl binding, the pin configuration nodes need not be
69 direct children of the pin controller device (may be grandchildren for
70 example). It is define is each individual pin controller device.
71 Say Y here if you want to keep this behavior with the pinconfig
Yuan Fang973a9792021-09-08 19:06:48 +080072 u-class: all sub are recursively bounded.
Patrick Delaunaybcdb1042019-08-02 14:48:00 +020073 If the option is disabled, this behavior is deactivated and only
74 the direct children of pin controller will be assumed as pin
75 configuration; you can save memory footprint when this feature is
76 no needed.
77
Masahiro Yamadaf8efa632015-08-27 12:44:29 +090078config SPL_PINCTRL
Philipp Tomsich2b1c2042017-07-26 12:27:42 +020079 bool "Support pin controllers in SPL"
Masahiro Yamadaf8efa632015-08-27 12:44:29 +090080 depends on SPL && SPL_DM
81 help
82 This option is an SPL-variant of the PINCTRL option.
83 See the help of PINCTRL for details.
84
Simon Glass5edf3f32019-12-06 21:41:45 -070085config TPL_PINCTRL
86 bool "Support pin controllers in TPL"
87 depends on TPL && TPL_DM
88 help
89 This option is an TPL variant of the PINCTRL option.
90 See the help of PINCTRL for details.
91
Simon Glasse7ca7da2022-04-30 00:56:53 -060092config VPL_PINCTRL
93 bool "Support pin controllers in VPL"
94 depends on VPL && VPL_DM
95 help
96 This option is an VPL variant of the PINCTRL option.
97 See the help of PINCTRL for details.
98
Masahiro Yamadaf8efa632015-08-27 12:44:29 +090099config SPL_PINCTRL_FULL
100 bool "Support full pin controllers in SPL"
101 depends on SPL_PINCTRL && SPL_OF_CONTROL
Vikas Manocha50218ae2017-05-28 12:55:10 -0700102 default n if TARGET_STM32F746_DISCO
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900103 default y
104 help
Simon Glasse7ca7da2022-04-30 00:56:53 -0600105 This option is an SPL variant of the PINCTRL_FULL option.
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900106 See the help of PINCTRL_FULL for details.
107
Simon Glass5edf3f32019-12-06 21:41:45 -0700108config TPL_PINCTRL_FULL
109 bool "Support full pin controllers in TPL"
110 depends on TPL_PINCTRL && TPL_OF_CONTROL
111 help
Simon Glasse7ca7da2022-04-30 00:56:53 -0600112 This option is a TPL variant of the PINCTRL_FULL option.
113 See the help of PINCTRL_FULL for details.
114
115config VPL_PINCTRL_FULL
116 bool "Support full pin controllers in VPL"
117 depends on VPL_PINCTRL && VPL_OF_CONTROL
118 help
119 This option is a VPL variant of the PINCTRL_FULL option.
Simon Glass5edf3f32019-12-06 21:41:45 -0700120 See the help of PINCTRL_FULL for details.
121
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900122config SPL_PINCTRL_GENERIC
123 bool "Support generic pin controllers in SPL"
124 depends on SPL_PINCTRL_FULL
125 default y
126 help
127 This option is an SPL-variant of the PINCTRL_GENERIC option.
128 See the help of PINCTRL_GENERIC for details.
129
Quentin Schulz22980e42024-11-06 12:29:41 +0100130config TPL_PINCTRL_GENERIC
131 bool "Support generic pin controllers in TPL"
132 depends on TPL_PINCTRL_FULL
133 default y
134 help
135 This option is a TPL-variant of the PINCTRL_GENERIC option.
136 See the help of PINCTRL_GENERIC for details.
137
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900138config SPL_PINMUX
139 bool "Support pin multiplexing controllers in SPL"
140 depends on SPL_PINCTRL_GENERIC
141 default y
142 help
143 This option is an SPL-variant of the PINMUX option.
144 See the help of PINMUX for details.
Simon Glass8d6510d2015-08-30 16:55:12 -0600145 The pinctrl subsystem can add a substantial overhead to the SPL
146 image since it typically requires quite a few tables either in the
147 driver or in the device tree. If this is acceptable and you need
148 to adjust pin multiplexing in SPL in order to boot into U-Boot,
149 enable this option. You will need to enable device tree in SPL
150 for this to work.
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900151
152config SPL_PINCONF
153 bool "Support pin configuration controllers in SPL"
154 depends on SPL_PINCTRL_GENERIC
155 help
156 This option is an SPL-variant of the PINCONF option.
157 See the help of PINCONF for details.
158
Patrick Delaunaybcdb1042019-08-02 14:48:00 +0200159config SPL_PINCONF_RECURSIVE
160 bool "Support recursive binding for pin configuration nodes in SPL"
161 depends on SPL_PINCTRL_FULL
162 default n if ARCH_STM32MP
163 default y
164 help
165 This option is an SPL-variant of the PINCONF_RECURSIVE option.
166 See the help of PINCONF_RECURSIVE for details.
167
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900168if PINCTRL || SPL_PINCTRL
169
Mark Kettenisc9329762021-11-02 18:21:57 +0100170config PINCTRL_APPLE
171 bool "Apple pinctrl driver"
172 depends on DM && PINCTRL_GENERIC && ARCH_APPLE
173 default y
174 help
175 Support pin multiplexing on Apple SoCs.
176
177 The driver is controlled by a device tree node which contains
178 both the GPIO definitions and pin control functions for each
179 available multiplex function.
180
Greg Malysad7e90d62025-02-26 12:30:23 -0500181config PINCTRL_ADI
182 bool "ADI pinctrl driver"
183 depends on DM && ARCH_SC5XX
184 help
185 This driver enables pinctrl support on SC5xx processors. This
186 driver covers only the pin configuration functionality, and
187 GPIO functionality is contained in the separate GPIO driver.
188
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200189config PINCTRL_AR933X
Wills Wang77ae2382016-03-16 16:59:55 +0800190 bool "QCA/Athores ar933x pin control driver"
191 depends on DM && SOC_AR933X
192 help
193 Support pin multiplexing control on QCA/Athores ar933x SoCs.
194 The driver is controlled by a device tree node which contains
195 both the GPIO definitions and pin control functions for each
196 available multiplex function.
197
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200198config PINCTRL_AT91
199 bool "AT91 pinctrl driver"
200 depends on DM
201 help
202 This option is to enable the AT91 pinctrl driver for AT91 PIO
203 controller.
204
205 AT91 PIO controller is a combined gpio-controller, pin-mux and
206 pin-config module. Each I/O pin may be dedicated as a general-purpose
207 I/O or be assigned to a function of an embedded peripheral. Each I/O
208 pin has a glitch filter providing rejection of glitches lower than
209 one-half of peripheral clock cycle and a debouncing filter providing
210 rejection of unwanted pulses from key or push button operations. You
211 can also control the multi-driver capability, pull-up and pull-down
212 feature on each I/O pin.
213
214config PINCTRL_AT91PIO4
215 bool "AT91 PIO4 pinctrl driver"
216 depends on DM
217 help
218 This option is to enable the AT91 pinctrl driver for AT91 PIO4
219 controller which is available on SAMA5D2 SoC.
220
Simon Glass837a66a2019-12-06 21:42:53 -0700221config PINCTRL_INTEL
222 bool "Standard Intel pin-control and pin-mux driver"
223 help
224 Recent Intel chips such as Apollo Lake (APL) use a common pin control
225 and GPIO scheme. The settings for this come from an SoC-specific
226 driver which must be separately enabled. The driver supports setting
227 pins on start-up and changing the GPIO attributes.
228
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200229config PINCTRL_PIC32
230 bool "Microchip PIC32 pin-control and pin-mux driver"
231 depends on DM && MACH_PIC32
232 default y
233 help
234 Supports individual pin selection and configuration for each
235 remappable peripheral available on Microchip PIC32
236 SoCs. This driver is controlled by a device tree node which
Chris Packham3fede312019-01-13 22:13:26 +1300237 contains both GPIO definition and pin control functions.
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200238
239config PINCTRL_QCA953X
Wills Wanga56de4c2016-03-16 16:59:56 +0800240 bool "QCA/Athores qca953x pin control driver"
241 depends on DM && SOC_QCA953X
242 help
243 Support pin multiplexing control on QCA/Athores qca953x SoCs.
Wills Wanga56de4c2016-03-16 16:59:56 +0800244
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200245 The driver is controlled by a device tree node which contains both
246 the GPIO definitions and pin control functions for each available
247 multiplex function.
248
Heiko Schocher3b07a132020-02-03 10:23:53 +0100249config PINCTRL_QE
250 bool "QE based pinctrl driver, like on mpc83xx"
251 depends on DM
252 help
253 This option is to enable the QE pinctrl driver for QE based io
254 controller.
255
Andy Yan96c3da92017-06-01 18:00:10 +0800256config PINCTRL_ROCKCHIP_RV1108
257 bool "Rockchip rv1108 pin control driver"
258 depends on DM
259 help
260 Support pin multiplexing control on Rockchip rv1108 SoC.
261
262 The driver is controlled by a device tree node which contains
263 both the GPIO definitions and pin control functions for each
264 available multiplex function.
265
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900266config PINCTRL_SANDBOX
267 bool "Sandbox pinctrl driver"
268 depends on SANDBOX
269 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200270 This enables pinctrl driver for sandbox.
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900271
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200272 Currently, this driver actually does nothing but print debug
273 messages when pinctrl operations are invoked.
274
275config PINCTRL_SINGLE
276 bool "Single register pin-control and pin-multiplex driver"
277 depends on DM
Purna Chandra Mandaldb4fbfc2016-01-28 15:30:12 +0530278 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200279 This enables pinctrl driver for systems using a single register for
280 pin configuration and multiplexing. TI's AM335X SoCs are examples of
281 such systems.
282
283 Depending on the platform make sure to also enable OF_TRANSLATE and
284 eventually SPL_OF_TRANSLATE to get correct address translations.
Purna Chandra Mandaldb4fbfc2016-01-28 15:30:12 +0530285
Patrice Chotard32cf0462017-02-21 13:37:10 +0100286config PINCTRL_STI
287 bool "STMicroelectronics STi pin-control and pin-mux driver"
288 depends on DM && ARCH_STI
289 default y
290 help
Patrick Delaunaya6b185e2022-05-20 18:38:10 +0200291 Support pin multiplexing control on STMicroelectronics STi SoCs.
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200292
Patrice Chotard32cf0462017-02-21 13:37:10 +0100293 The driver is controlled by a device tree node which contains both
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200294 the GPIO definitions and pin control functions for each available
295 multiplex function.
Patrice Chotard32cf0462017-02-21 13:37:10 +0100296
Vikas Manocha07e9e412017-02-12 10:25:49 -0800297config PINCTRL_STM32
298 bool "ST STM32 pin control driver"
299 depends on DM
300 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200301 Supports pin multiplexing control on stm32 SoCs.
Vikas Manocha07e9e412017-02-12 10:25:49 -0800302
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200303 The driver is controlled by a device tree node which contains both
304 the GPIO definitions and pin control functions for each available
305 multiplex function.
Felix Brack7bc23542017-03-22 11:26:44 +0100306
Patrick Delaunayd65291b2019-03-11 11:13:15 +0100307config PINCTRL_STMFX
308 bool "STMicroelectronics STMFX I2C GPIO expander pinctrl driver"
309 depends on DM && PINCTRL_FULL
310 help
311 I2C driver for STMicroelectronics Multi-Function eXpander (STMFX)
312 GPIO expander.
313 Supports pin multiplexing control on stm32 SoCs.
314
315 The driver is controlled by a device tree node which contains both
316 the GPIO definitions and pin control functions for each available
317 multiplex function.
318
319config SPL_PINCTRL_STMFX
320 bool "STMicroelectronics STMFX I2C GPIO expander pinctrl driver in SPL"
321 depends on SPL_PINCTRL_FULL
322 help
323 This option is an SPL-variant of the SPL_PINCTRL_STMFX option.
324 See the help of PINCTRL_STMFX for details.
325
maxims@google.com54651aa2017-04-17 12:00:27 -0700326config ASPEED_AST2500_PINCTRL
Michal Simek8d4e7e22020-07-23 09:00:40 +0200327 bool "Aspeed AST2500 pin control driver"
328 depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
329 default y
330 help
331 Support pin multiplexing control on Aspeed ast2500 SoC. The driver
332 uses Generic Pinctrl framework and is compatible with the Linux
333 driver, i.e. it uses the same device tree configuration.
maxims@google.com54651aa2017-04-17 12:00:27 -0700334
Ryan Chen1efbd142021-11-02 10:17:52 +0800335config ASPEED_AST2600_PINCTRL
336 bool "Aspeed AST2600 pin control driver"
337 depends on DM && PINCTRL_GENERIC && ASPEED_AST2600
338 default y
339 help
340 Support pin multiplexing control on Aspeed ast2600 SoC. The driver
341 uses Generic Pinctrl framework and is compatible with the Linux
342 driver, i.e. it uses the same device tree configuration.
343
Sean Anderson087dfce2020-09-14 11:01:58 -0400344config PINCTRL_K210
345 bool "Kendryte K210 Fully-Programmable Input/Output Array driver"
346 depends on DM && PINCTRL_GENERIC
347 help
348 Support pin multiplexing on the K210. The "FPIOA" can remap any
349 supported function to any multifunctional IO pin. It can also perform
350 basic GPIO functions, such as reading the current value of a pin.
Ashok Reddy Soma52a32812022-02-23 15:23:05 +0100351
352config PINCTRL_ZYNQMP
353 bool "Xilinx ZynqMP pin control driver"
354 depends on DM && PINCTRL_GENERIC && ARCH_ZYNQMP
355 default y
356 help
357 Support pin multiplexing control on Xilinx ZynqMP. The driver uses
358 Generic Pinctrl framework and is compatible with the Linux driver,
359 i.e. it uses the same device tree configuration.
360
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900361endif
362
Philipp Tomsich126493f2019-02-01 15:11:48 +0100363source "drivers/pinctrl/broadcom/Kconfig"
364source "drivers/pinctrl/exynos/Kconfig"
Simon Glass837a66a2019-12-06 21:42:53 -0700365source "drivers/pinctrl/intel/Kconfig"
developer84c7a632018-11-15 10:07:58 +0800366source "drivers/pinctrl/mediatek/Kconfig"
Philipp Tomsich126493f2019-02-01 15:11:48 +0100367source "drivers/pinctrl/meson/Kconfig"
368source "drivers/pinctrl/mscc/Kconfig"
developere1947812019-09-25 17:45:26 +0800369source "drivers/pinctrl/mtmips/Kconfig"
Philipp Tomsich126493f2019-02-01 15:11:48 +0100370source "drivers/pinctrl/mvebu/Kconfig"
Stefan Boschbe278c12020-07-10 19:07:30 +0200371source "drivers/pinctrl/nexell/Kconfig"
Jim Liud949c122022-05-17 16:30:32 +0800372source "drivers/pinctrl/nuvoton/Kconfig"
Peng Fane2fd36cc2016-02-03 10:06:07 +0800373source "drivers/pinctrl/nxp/Kconfig"
Caleb Connolly506eb532023-11-14 12:55:40 +0000374source "drivers/pinctrl/qcom/Kconfig"
Marek Vasut3066a062017-09-15 21:13:55 +0200375source "drivers/pinctrl/renesas/Kconfig"
Philipp Tomsich2b19e902019-02-01 15:15:38 +0100376source "drivers/pinctrl/rockchip/Kconfig"
Samuel Hollande3095022021-08-12 20:09:43 -0500377source "drivers/pinctrl/sunxi/Kconfig"
Svyatoslav Ryhelc53f4c02023-11-26 17:54:03 +0200378source "drivers/pinctrl/tegra/Kconfig"
Masahiro Yamada847e618b82015-09-11 20:17:32 +0900379source "drivers/pinctrl/uniphier/Kconfig"
Kuan Lim Leeec2b8f22023-03-29 11:42:15 +0800380source "drivers/pinctrl/starfive/Kconfig"
Masahiro Yamada847e618b82015-09-11 20:17:32 +0900381
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900382endmenu