blob: 06f20895accfb4732943cea6b6191bda405b0cfb [file] [log] [blame]
Joseph Chen72c11232025-04-07 22:46:49 +00001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 * Author: Joseph Chen <chenjh@rock-chips.com>
5 */
6
7#include <bitfield.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <syscon.h>
12#include <asm/arch-rockchip/clock.h>
13#include <asm/arch-rockchip/cru_rk3528.h>
14#include <asm/arch-rockchip/hardware.h>
15#include <dm/device-internal.h>
16#include <dm/lists.h>
17#include <dt-bindings/clock/rockchip,rk3528-cru.h>
18#include <linux/delay.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
23
24/*
25 * PLL attention.
26 *
27 * [FRAC PLL]: GPLL, PPLL, DPLL
28 * - frac mode: refdiv can be 1 or 2 only
29 * - int mode: refdiv has no special limit
30 * - VCO range: [950, 3800] MHZ
31 *
32 * [INT PLL]: CPLL, APLL
33 * - int mode: refdiv can be 1 or 2 only
34 * - VCO range: [475, 1900] MHZ
35 *
36 * [PPLL]: normal mode only.
37 *
38 */
39static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
40 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
41 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
50 RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
53 RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
54 RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
55 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
56 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
57 RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
58 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
59 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
60 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
61 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
62 RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
63 { /* sentinel */ },
64};
65
66static struct rockchip_pll_clock rk3528_pll_clks[] = {
67 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
68 RK3528_MODE_CON, 0, 10, 0, rk3528_pll_rates),
69
70 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
71 RK3528_MODE_CON, 2, 10, 0, rk3528_pll_rates),
72
73 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
74 RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates),
75
76 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
77 RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
78
79 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
80 RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates),
81};
82
83#define RK3528_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \
84{ \
85 .rate = _rate##U, \
86 .aclk_div = (_aclk_m_core), \
87 .pclk_div = (_pclk_dbg), \
88}
89
90/* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
91static struct rockchip_cpu_rate_table rk3528_cpu_rates[] = {
92 RK3528_CPUCLK_RATE(1896000000, 1, 13),
93 RK3528_CPUCLK_RATE(1800000000, 1, 12),
94 RK3528_CPUCLK_RATE(1704000000, 1, 11),
95 RK3528_CPUCLK_RATE(1608000000, 1, 11),
96 RK3528_CPUCLK_RATE(1512000000, 1, 11),
97 RK3528_CPUCLK_RATE(1416000000, 1, 9),
98 RK3528_CPUCLK_RATE(1296000000, 1, 8),
99 RK3528_CPUCLK_RATE(1200000000, 1, 8),
100 RK3528_CPUCLK_RATE(1188000000, 1, 8),
101 RK3528_CPUCLK_RATE(1092000000, 1, 7),
102 RK3528_CPUCLK_RATE(1008000000, 1, 6),
103 RK3528_CPUCLK_RATE(1000000000, 1, 6),
104 RK3528_CPUCLK_RATE(996000000, 1, 6),
105 RK3528_CPUCLK_RATE(960000000, 1, 6),
106 RK3528_CPUCLK_RATE(912000000, 1, 6),
107 RK3528_CPUCLK_RATE(816000000, 1, 5),
108 RK3528_CPUCLK_RATE(600000000, 1, 3),
109 RK3528_CPUCLK_RATE(594000000, 1, 3),
110 RK3528_CPUCLK_RATE(408000000, 1, 2),
111 RK3528_CPUCLK_RATE(312000000, 1, 2),
112 RK3528_CPUCLK_RATE(216000000, 1, 1),
113 RK3528_CPUCLK_RATE(96000000, 1, 0),
114};
115
116/*
117 *
118 * rational_best_approximation(31415, 10000,
119 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
120 *
121 * you may look at given_numerator as a fixed point number,
122 * with the fractional part size described in given_denominator.
123 *
124 * for theoretical background, see:
125 * http://en.wikipedia.org/wiki/Continued_fraction
126 */
127static void rational_best_approximation(unsigned long given_numerator,
128 unsigned long given_denominator,
129 unsigned long max_numerator,
130 unsigned long max_denominator,
131 unsigned long *best_numerator,
132 unsigned long *best_denominator)
133{
134 unsigned long n, d, n0, d0, n1, d1;
135
136 n = given_numerator;
137 d = given_denominator;
138 n0 = 0;
139 d1 = 0;
140 n1 = 1;
141 d0 = 1;
142 for (;;) {
143 unsigned long t, a;
144
145 if (n1 > max_numerator || d1 > max_denominator) {
146 n1 = n0;
147 d1 = d0;
148 break;
149 }
150 if (d == 0)
151 break;
152 t = d;
153 a = n / d;
154 d = n % d;
155 n = t;
156 t = n0 + a * n1;
157 n0 = n1;
158 n1 = t;
159 t = d0 + a * d1;
160 d0 = d1;
161 d1 = t;
162 }
163 *best_numerator = n1;
164 *best_denominator = d1;
165}
166
167static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate)
168{
169 const struct rockchip_cpu_rate_table *rate;
170 struct rk3528_cru *cru = priv->cru;
171 ulong old_rate;
172
173 rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate);
174 if (!rate) {
175 printf("%s unsupported rate\n", __func__);
176 return -EINVAL;
177 }
178
179 /*
180 * set up dependent divisors for DBG and ACLK clocks.
181 */
182 old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL);
183 if (old_rate > new_rate) {
184 if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
185 priv->cru, APLL, new_rate))
186 return -EINVAL;
187
188 rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
189 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
190
191 rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
192 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
193 } else if (old_rate < new_rate) {
194 rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
195 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
196
197 rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
198 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
199
200 if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
201 priv->cru, APLL, new_rate))
202 return -EINVAL;
203 }
204
205 return 0;
206}
207
208static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv,
209 ulong clk_id)
210{
211 struct rk3528_cru *cru = priv->cru;
212 u32 div, mask, shift;
213 void *reg;
214
215 switch (clk_id) {
216 case CLK_PPLL_50M_MATRIX:
217 case CLK_GMAC1_RMII_VPU:
218 mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
219 shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
220 reg = &cru->pcieclksel_con[1];
221 break;
222
223 case CLK_PPLL_100M_MATRIX:
224 mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
225 shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
226 reg = &cru->pcieclksel_con[1];
227 break;
228
229 case CLK_PPLL_125M_MATRIX:
230 case CLK_GMAC1_SRC_VPU:
231 mask = CLK_MATRIX_125M_SRC_DIV_MASK;
232 shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
233 reg = &cru->clksel_con[60];
234 break;
235
236 case CLK_GMAC1_VPU_25M:
237 mask = CLK_MATRIX_25M_SRC_DIV_MASK;
238 shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
239 reg = &cru->clksel_con[60];
240 break;
241 default:
242 return -ENOENT;
243 }
244
245 div = (readl(reg) & mask) >> shift;
246
247 return DIV_TO_RATE(priv->ppll_hz, div);
248}
249
250static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv,
251 ulong clk_id, ulong rate)
252{
253 struct rk3528_cru *cru = priv->cru;
254 u32 id, div, mask, shift;
255 u8 is_pciecru = 0;
256
257 switch (clk_id) {
258 case CLK_PPLL_50M_MATRIX:
259 id = 1;
260 mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
261 shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
262 is_pciecru = 1;
263 break;
264
265 case CLK_PPLL_100M_MATRIX:
266 id = 1;
267 mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
268 shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
269 is_pciecru = 1;
270 break;
271
272 case CLK_PPLL_125M_MATRIX:
273 id = 60;
274 mask = CLK_MATRIX_125M_SRC_DIV_MASK;
275 shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
276 break;
277 case CLK_GMAC1_VPU_25M:
278 id = 60;
279 mask = CLK_MATRIX_25M_SRC_DIV_MASK;
280 shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
281 break;
282 default:
283 return -ENOENT;
284 }
285
286 div = DIV_ROUND_UP(priv->ppll_hz, rate);
287 if (is_pciecru)
288 rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift);
289 else
290 rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift);
291
292 return rk3528_ppll_matrix_get_rate(priv, clk_id);
293}
294
295static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv,
296 ulong clk_id)
297{
298 struct rk3528_cru *cru = priv->cru;
299 u32 sel, div, mask, shift, con;
300 u32 sel_mask = 0, sel_shift;
301 u8 is_gpll_parent = 1;
302 u8 is_halfdiv = 0;
303 ulong prate;
304
305 switch (clk_id) {
306 case CLK_MATRIX_50M_SRC:
307 con = 0;
308 mask = CLK_MATRIX_50M_SRC_DIV_MASK;
309 shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
310 is_gpll_parent = 0;
311 break;
312
313 case CLK_MATRIX_100M_SRC:
314 con = 0;
315 mask = CLK_MATRIX_100M_SRC_DIV_MASK;
316 shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
317 is_gpll_parent = 0;
318 break;
319
320 case CLK_MATRIX_150M_SRC:
321 con = 1;
322 mask = CLK_MATRIX_150M_SRC_DIV_MASK;
323 shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
324 break;
325
326 case CLK_MATRIX_200M_SRC:
327 con = 1;
328 mask = CLK_MATRIX_200M_SRC_DIV_MASK;
329 shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
330 break;
331
332 case CLK_MATRIX_250M_SRC:
333 con = 1;
334 mask = CLK_MATRIX_250M_SRC_DIV_MASK;
335 shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
336 sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
337 sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
338 break;
339
340 case CLK_MATRIX_300M_SRC:
341 con = 2;
342 mask = CLK_MATRIX_300M_SRC_DIV_MASK;
343 shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
344 break;
345
346 case CLK_MATRIX_339M_SRC:
347 con = 2;
348 mask = CLK_MATRIX_339M_SRC_DIV_MASK;
349 shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
350 is_halfdiv = 1;
351 break;
352
353 case CLK_MATRIX_400M_SRC:
354 con = 2;
355 mask = CLK_MATRIX_400M_SRC_DIV_MASK;
356 shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
357 break;
358
359 case CLK_MATRIX_500M_SRC:
360 con = 3;
361 mask = CLK_MATRIX_500M_SRC_DIV_MASK;
362 shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
363 sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
364 sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
365 break;
366
367 case CLK_MATRIX_600M_SRC:
368 con = 4;
369 mask = CLK_MATRIX_600M_SRC_DIV_MASK;
370 shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
371 break;
372
373 case ACLK_BUS_VOPGL_ROOT:
374 case ACLK_BUS_VOPGL_BIU:
375 con = 43;
376 mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
377 shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
378 break;
379
380 default:
381 return -ENOENT;
382 }
383
384 if (sel_mask) {
385 sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift;
386 if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO
387 prate = priv->gpll_hz;
388 else
389 prate = priv->cpll_hz;
390 } else {
391 if (is_gpll_parent)
392 prate = priv->gpll_hz;
393 else
394 prate = priv->cpll_hz;
395 }
396
397 div = (readl(&cru->clksel_con[con]) & mask) >> shift;
398
399 /* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */
400 return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div);
401}
402
403static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv,
404 ulong clk_id, ulong rate)
405{
406 struct rk3528_cru *cru = priv->cru;
407 u32 sel, div, mask, shift, con;
408 u32 sel_mask = 0, sel_shift;
409 u8 is_gpll_parent = 1;
410 u8 is_halfdiv = 0;
411 ulong prate = 0;
412
413 switch (clk_id) {
414 case CLK_MATRIX_50M_SRC:
415 con = 0;
416 mask = CLK_MATRIX_50M_SRC_DIV_MASK;
417 shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
418 is_gpll_parent = 0;
419 break;
420
421 case CLK_MATRIX_100M_SRC:
422 con = 0;
423 mask = CLK_MATRIX_100M_SRC_DIV_MASK;
424 shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
425 is_gpll_parent = 0;
426 break;
427
428 case CLK_MATRIX_150M_SRC:
429 con = 1;
430 mask = CLK_MATRIX_150M_SRC_DIV_MASK;
431 shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
432 break;
433
434 case CLK_MATRIX_200M_SRC:
435 con = 1;
436 mask = CLK_MATRIX_200M_SRC_DIV_MASK;
437 shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
438 break;
439
440 case CLK_MATRIX_250M_SRC:
441 con = 1;
442 mask = CLK_MATRIX_250M_SRC_DIV_MASK;
443 shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
444 sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
445 sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
446 break;
447
448 case CLK_MATRIX_300M_SRC:
449 con = 2;
450 mask = CLK_MATRIX_300M_SRC_DIV_MASK;
451 shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
452 break;
453
454 case CLK_MATRIX_339M_SRC:
455 con = 2;
456 mask = CLK_MATRIX_339M_SRC_DIV_MASK;
457 shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
458 is_halfdiv = 1;
459 break;
460
461 case CLK_MATRIX_400M_SRC:
462 con = 2;
463 mask = CLK_MATRIX_400M_SRC_DIV_MASK;
464 shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
465 break;
466
467 case CLK_MATRIX_500M_SRC:
468 con = 3;
469 mask = CLK_MATRIX_500M_SRC_DIV_MASK;
470 shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
471 sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
472 sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
473 break;
474
475 case CLK_MATRIX_600M_SRC:
476 con = 4;
477 mask = CLK_MATRIX_600M_SRC_DIV_MASK;
478 shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
479 break;
480
481 case ACLK_BUS_VOPGL_ROOT:
482 case ACLK_BUS_VOPGL_BIU:
483 con = 43;
484 mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
485 shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
486 break;
487
488 default:
489 return -ENOENT;
490 }
491
492 if (sel_mask) {
493 if (priv->gpll_hz % rate == 0) {
494 sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO
495 prate = priv->gpll_hz;
496 } else {
497 sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX;
498 prate = priv->cpll_hz;
499 }
500 } else {
501 if (is_gpll_parent)
502 prate = priv->gpll_hz;
503 else
504 prate = priv->cpll_hz;
505 }
506
507 if (is_halfdiv)
508 /* NOTE: '+1' to balance the following rk_clrsetreg() 'div-1' */
509 div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1;
510 else
511 div = DIV_ROUND_UP(prate, rate);
512
513 rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift);
514 if (sel_mask)
515 rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift);
516
517 return rk3528_cgpll_matrix_get_rate(priv, clk_id);
518}
519
520static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
521{
522 struct rk3528_cru *cru = priv->cru;
523 u32 id, sel, con, mask, shift;
524 u8 is_pmucru = 0;
525 ulong rate;
526
527 switch (clk_id) {
528 case CLK_I2C0:
529 id = 79;
530 mask = CLK_I2C0_SEL_MASK;
531 shift = CLK_I2C0_SEL_SHIFT;
532 break;
533
534 case CLK_I2C1:
535 id = 79;
536 mask = CLK_I2C1_SEL_MASK;
537 shift = CLK_I2C1_SEL_SHIFT;
538 break;
539
540 case CLK_I2C2:
541 id = 0;
542 mask = CLK_I2C2_SEL_MASK;
543 shift = CLK_I2C2_SEL_SHIFT;
544 is_pmucru = 1;
545 break;
546
547 case CLK_I2C3:
548 id = 63;
549 mask = CLK_I2C3_SEL_MASK;
550 shift = CLK_I2C3_SEL_SHIFT;
551 break;
552
553 case CLK_I2C4:
554 id = 85;
555 mask = CLK_I2C4_SEL_MASK;
556 shift = CLK_I2C4_SEL_SHIFT;
557 break;
558
559 case CLK_I2C5:
560 id = 63;
561 mask = CLK_I2C5_SEL_MASK;
562 shift = CLK_I2C5_SEL_SHIFT;
563 break;
564
565 case CLK_I2C6:
566 id = 64;
567 mask = CLK_I2C6_SEL_MASK;
568 shift = CLK_I2C6_SEL_SHIFT;
569 break;
570
571 case CLK_I2C7:
572 id = 86;
573 mask = CLK_I2C7_SEL_MASK;
574 shift = CLK_I2C7_SEL_SHIFT;
575 break;
576
577 default:
578 return -ENOENT;
579 }
580
581 if (is_pmucru)
582 con = readl(&cru->pmuclksel_con[id]);
583 else
584 con = readl(&cru->clksel_con[id]);
585 sel = (con & mask) >> shift;
586 if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC)
587 rate = 200 * MHz;
588 else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC)
589 rate = 100 * MHz;
590 else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC)
591 rate = 50 * MHz;
592 else
593 rate = OSC_HZ;
594
595 return rate;
596}
597
598static ulong rk3528_i2c_set_clk(struct rk3528_clk_priv *priv, ulong clk_id,
599 ulong rate)
600{
601 struct rk3528_cru *cru = priv->cru;
602 u32 id, sel, mask, shift;
603 u8 is_pmucru = 0;
604
605 if (rate >= 198 * MHz)
606 sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC;
607 else if (rate >= 99 * MHz)
608 sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC;
609 else if (rate >= 50 * MHz)
610 sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC;
611 else
612 sel = CLK_I2C3_SEL_XIN_OSC0_FUNC;
613
614 switch (clk_id) {
615 case CLK_I2C0:
616 id = 79;
617 mask = CLK_I2C0_SEL_MASK;
618 shift = CLK_I2C0_SEL_SHIFT;
619 break;
620
621 case CLK_I2C1:
622 id = 79;
623 mask = CLK_I2C1_SEL_MASK;
624 shift = CLK_I2C1_SEL_SHIFT;
625 break;
626
627 case CLK_I2C2:
628 id = 0;
629 mask = CLK_I2C2_SEL_MASK;
630 shift = CLK_I2C2_SEL_SHIFT;
631 is_pmucru = 1;
632 break;
633
634 case CLK_I2C3:
635 id = 63;
636 mask = CLK_I2C3_SEL_MASK;
637 shift = CLK_I2C3_SEL_SHIFT;
638 break;
639
640 case CLK_I2C4:
641 id = 85;
642 mask = CLK_I2C4_SEL_MASK;
643 shift = CLK_I2C4_SEL_SHIFT;
644 break;
645
646 case CLK_I2C5:
647 id = 63;
648 mask = CLK_I2C5_SEL_MASK;
649 shift = CLK_I2C5_SEL_SHIFT;
650 break;
651
652 case CLK_I2C6:
653 id = 64;
654 mask = CLK_I2C6_SEL_MASK;
655 shift = CLK_I2C6_SEL_SHIFT;
656 break;
657
658 case CLK_I2C7:
659 id = 86;
660 mask = CLK_I2C7_SEL_MASK;
661 shift = CLK_I2C7_SEL_SHIFT;
662 break;
663
664 default:
665 return -ENOENT;
666 }
667
668 if (is_pmucru)
669 rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift);
670 else
671 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
672
673 return rk3528_i2c_get_clk(priv, clk_id);
674}
675
676static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
677{
678 struct rk3528_cru *cru = priv->cru;
679 u32 id, sel, con, mask, shift;
680 ulong rate;
681
682 switch (clk_id) {
683 case CLK_SPI0:
684 id = 79;
685 mask = CLK_SPI0_SEL_MASK;
686 shift = CLK_SPI0_SEL_SHIFT;
687 break;
688
689 case CLK_SPI1:
690 id = 63;
691 mask = CLK_SPI1_SEL_MASK;
692 shift = CLK_SPI1_SEL_SHIFT;
693 break;
694 default:
695 return -ENOENT;
696 }
697
698 con = readl(&cru->clksel_con[id]);
699 sel = (con & mask) >> shift;
700 if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC)
701 rate = 200 * MHz;
702 else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC)
703 rate = 100 * MHz;
704 else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC)
705 rate = 50 * MHz;
706 else
707 rate = OSC_HZ;
708
709 return rate;
710}
711
712static ulong rk3528_spi_set_clk(struct rk3528_clk_priv *priv,
713 ulong clk_id, ulong rate)
714{
715 struct rk3528_cru *cru = priv->cru;
716 u32 id, sel, mask, shift;
717
718 if (rate >= 198 * MHz)
719 sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC;
720 else if (rate >= 99 * MHz)
721 sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC;
722 else if (rate >= 50 * MHz)
723 sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC;
724 else
725 sel = CLK_SPI1_SEL_XIN_OSC0_FUNC;
726
727 switch (clk_id) {
728 case CLK_SPI0:
729 id = 79;
730 mask = CLK_SPI0_SEL_MASK;
731 shift = CLK_SPI0_SEL_SHIFT;
732 break;
733
734 case CLK_SPI1:
735 id = 63;
736 mask = CLK_SPI1_SEL_MASK;
737 shift = CLK_SPI1_SEL_SHIFT;
738 break;
739 default:
740 return -ENOENT;
741 }
742
743 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
744
745 return rk3528_spi_get_clk(priv, clk_id);
746}
747
748static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
749{
750 struct rk3528_cru *cru = priv->cru;
751 u32 id, sel, con, mask, shift;
752 ulong rate;
753
754 switch (clk_id) {
755 case CLK_PWM0:
756 id = 44;
757 mask = CLK_PWM0_SEL_MASK;
758 shift = CLK_PWM0_SEL_SHIFT;
759 break;
760
761 case CLK_PWM1:
762 id = 44;
763 mask = CLK_PWM1_SEL_MASK;
764 shift = CLK_PWM1_SEL_SHIFT;
765 break;
766
767 default:
768 return -ENOENT;
769 }
770
771 con = readl(&cru->clksel_con[id]);
772 sel = (con & mask) >> shift;
773 if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC)
774 rate = 100 * MHz;
775 if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)
776 rate = 50 * MHz;
777 else
778 rate = OSC_HZ;
779
780 return rate;
781}
782
783static ulong rk3528_pwm_set_clk(struct rk3528_clk_priv *priv,
784 ulong clk_id, ulong rate)
785{
786 struct rk3528_cru *cru = priv->cru;
787 u32 id, sel, mask, shift;
788
789 if (rate >= 99 * MHz)
790 sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC;
791 else if (rate >= 50 * MHz)
792 sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC;
793 else
794 sel = CLK_PWM0_SEL_XIN_OSC0_FUNC;
795
796 switch (clk_id) {
797 case CLK_PWM0:
798 id = 44;
799 mask = CLK_PWM0_SEL_MASK;
800 shift = CLK_PWM0_SEL_SHIFT;
801 break;
802
803 case CLK_PWM1:
804 id = 44;
805 mask = CLK_PWM1_SEL_MASK;
806 shift = CLK_PWM1_SEL_SHIFT;
807 break;
808
809 default:
810 return -ENOENT;
811 }
812
813 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
814
815 return rk3528_pwm_get_clk(priv, clk_id);
816}
817
818static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
819{
820 struct rk3528_cru *cru = priv->cru;
821 u32 div, con;
822
823 con = readl(&cru->clksel_con[74]);
824 switch (clk_id) {
825 case CLK_SARADC:
826 div = (con & CLK_SARADC_DIV_MASK) >>
827 CLK_SARADC_DIV_SHIFT;
828 break;
829
830 case CLK_TSADC_TSEN:
831 div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
832 CLK_TSADC_TSEN_DIV_SHIFT;
833 break;
834
835 case CLK_TSADC:
836 div = (con & CLK_TSADC_DIV_MASK) >>
837 CLK_TSADC_DIV_SHIFT;
838 break;
839
840 default:
841 return -ENOENT;
842 }
843
844 return DIV_TO_RATE(OSC_HZ, div);
845}
846
847static ulong rk3528_adc_set_clk(struct rk3528_clk_priv *priv,
848 ulong clk_id, ulong rate)
849{
850 struct rk3528_cru *cru = priv->cru;
851 u32 div, mask, shift;
852
853 switch (clk_id) {
854 case CLK_SARADC:
855 mask = CLK_SARADC_DIV_MASK;
856 shift = CLK_SARADC_DIV_SHIFT;
857 break;
858
859 case CLK_TSADC_TSEN:
860 mask = CLK_TSADC_TSEN_DIV_MASK;
861 shift = CLK_TSADC_TSEN_DIV_SHIFT;
862 break;
863
864 case CLK_TSADC:
865 mask = CLK_TSADC_DIV_MASK;
866 shift = CLK_TSADC_DIV_SHIFT;
867 break;
868
869 default:
870 return -ENOENT;
871 }
872
873 div = DIV_ROUND_UP(OSC_HZ, rate);
874 rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift);
875
876 return rk3528_adc_get_clk(priv, clk_id);
877}
878
879static ulong rk3528_sdmmc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
880{
881 struct rk3528_cru *cru = priv->cru;
882 u32 div, sel, con;
883 ulong prate;
884
885 con = readl(&cru->clksel_con[85]);
886 div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >>
887 CCLK_SRC_SDMMC0_DIV_SHIFT;
888 sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >>
889 CCLK_SRC_SDMMC0_SEL_SHIFT;
890
891 if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX)
892 prate = priv->gpll_hz;
893 else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX)
894 prate = priv->cpll_hz;
895 else
896 prate = OSC_HZ;
897
898 return DIV_TO_RATE(prate, div);
899}
900
901static ulong rk3528_sdmmc_set_clk(struct rk3528_clk_priv *priv,
902 ulong clk_id, ulong rate)
903{
904 struct rk3528_cru *cru = priv->cru;
905 u32 div, sel;
906
907 if (OSC_HZ % rate == 0) {
908 div = DIV_ROUND_UP(OSC_HZ, rate);
909 sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC;
910 } else if ((priv->cpll_hz % rate) == 0) {
911 div = DIV_ROUND_UP(priv->cpll_hz, rate);
912 sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX;
913 } else {
914 div = DIV_ROUND_UP(priv->gpll_hz, rate);
915 sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX;
916 }
917
918 assert(div - 1 <= 63);
919 rk_clrsetreg(&cru->clksel_con[85],
920 CCLK_SRC_SDMMC0_SEL_MASK |
921 CCLK_SRC_SDMMC0_DIV_MASK,
922 sel << CCLK_SRC_SDMMC0_SEL_SHIFT |
923 (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT);
924
925 return rk3528_sdmmc_get_clk(priv, clk_id);
926}
927
928static ulong rk3528_sfc_get_clk(struct rk3528_clk_priv *priv)
929{
930 struct rk3528_cru *cru = priv->cru;
931 u32 div, sel, con, parent;
932
933 con = readl(&cru->clksel_con[61]);
934 div = (con & SCLK_SFC_DIV_MASK) >>
935 SCLK_SFC_DIV_SHIFT;
936 sel = (con & SCLK_SFC_SEL_MASK) >>
937 SCLK_SFC_SEL_SHIFT;
938 if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX)
939 parent = priv->gpll_hz;
940 else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX)
941 parent = priv->cpll_hz;
942 else
943 parent = OSC_HZ;
944
945 return DIV_TO_RATE(parent, div);
946}
947
948static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
949{
950 struct rk3528_cru *cru = priv->cru;
951 int div, sel;
952
953 if (OSC_HZ % rate == 0) {
954 div = DIV_ROUND_UP(OSC_HZ, rate);
955 sel = SCLK_SFC_SEL_XIN_OSC0_FUNC;
956 } else if ((priv->cpll_hz % rate) == 0) {
957 div = DIV_ROUND_UP(priv->cpll_hz, rate);
958 sel = SCLK_SFC_SEL_CLK_CPLL_MUX;
959 } else {
960 div = DIV_ROUND_UP(priv->gpll_hz, rate);
961 sel = SCLK_SFC_SEL_CLK_GPLL_MUX;
962 }
963
964 assert(div - 1 <= 63);
965 rk_clrsetreg(&cru->clksel_con[61],
966 SCLK_SFC_SEL_MASK |
967 SCLK_SFC_DIV_MASK,
968 sel << SCLK_SFC_SEL_SHIFT |
969 (div - 1) << SCLK_SFC_DIV_SHIFT);
970
971 return rk3528_sfc_get_clk(priv);
972}
973
974static ulong rk3528_emmc_get_clk(struct rk3528_clk_priv *priv)
975{
976 struct rk3528_cru *cru = priv->cru;
977 u32 div, sel, con, parent;
978
979 con = readl(&cru->clksel_con[62]);
980 div = (con & CCLK_SRC_EMMC_DIV_MASK) >>
981 CCLK_SRC_EMMC_DIV_SHIFT;
982 sel = (con & CCLK_SRC_EMMC_SEL_MASK) >>
983 CCLK_SRC_EMMC_SEL_SHIFT;
984
985 if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX)
986 parent = priv->gpll_hz;
987 else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX)
988 parent = priv->cpll_hz;
989 else
990 parent = OSC_HZ;
991
992 return DIV_TO_RATE(parent, div);
993}
994
995static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
996{
997 struct rk3528_cru *cru = priv->cru;
998 u32 div, sel;
999
1000 if (OSC_HZ % rate == 0) {
1001 div = DIV_ROUND_UP(OSC_HZ, rate);
1002 sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC;
1003 } else if ((priv->cpll_hz % rate) == 0) {
1004 div = DIV_ROUND_UP(priv->cpll_hz, rate);
1005 sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX;
1006 } else {
1007 div = DIV_ROUND_UP(priv->gpll_hz, rate);
1008 sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX;
1009 }
1010
1011 assert(div - 1 <= 63);
1012 rk_clrsetreg(&cru->clksel_con[62],
1013 CCLK_SRC_EMMC_SEL_MASK |
1014 CCLK_SRC_EMMC_DIV_MASK,
1015 sel << CCLK_SRC_EMMC_SEL_SHIFT |
1016 (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT);
1017
1018 return rk3528_emmc_get_clk(priv);
1019}
1020
1021static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
1022{
1023 struct rk3528_cru *cru = priv->cru;
1024 u32 div_mask, div_shift;
1025 u32 sel_mask, sel_shift;
1026 u32 id, con, sel, div;
1027 ulong prate;
1028
1029 switch (clk_id) {
1030 case DCLK_VOP0:
1031 id = 32;
1032 sel_mask = DCLK_VOP_SRC0_SEL_MASK;
1033 sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
1034 /* FIXME if need src: clk_hdmiphy_pixel_io */
1035 div_mask = DCLK_VOP_SRC0_DIV_MASK;
1036 div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
1037 break;
1038
1039 case DCLK_VOP1:
1040 id = 33;
1041 sel_mask = DCLK_VOP_SRC1_SEL_MASK;
1042 sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
1043 div_mask = DCLK_VOP_SRC1_DIV_MASK;
1044 div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
1045 break;
1046
1047 default:
1048 return -ENOENT;
1049 }
1050
1051 con = readl(&cru->clksel_con[id]);
1052 div = (con & div_mask) >> div_shift;
1053 sel = (con & sel_mask) >> sel_shift;
1054 if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX)
1055 prate = priv->gpll_hz;
1056 else
1057 prate = priv->cpll_hz;
1058
1059 return DIV_TO_RATE(prate, div);
1060}
1061
1062static ulong rk3528_dclk_vop_set_clk(struct rk3528_clk_priv *priv,
1063 ulong clk_id, ulong rate)
1064{
1065 struct rk3528_cru *cru = priv->cru;
1066 u32 div_mask, div_shift;
1067 u32 sel_mask, sel_shift;
1068 u32 id, sel, div;
1069 ulong prate;
1070
1071 switch (clk_id) {
1072 case DCLK_VOP0:
1073 id = 32;
1074 sel_mask = DCLK_VOP_SRC0_SEL_MASK;
1075 sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
1076 /* FIXME if need src: clk_hdmiphy_pixel_io */
1077 div_mask = DCLK_VOP_SRC0_DIV_MASK;
1078 div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
1079 break;
1080
1081 case DCLK_VOP1:
1082 id = 33;
1083 sel_mask = DCLK_VOP_SRC1_SEL_MASK;
1084 sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
1085 div_mask = DCLK_VOP_SRC1_DIV_MASK;
1086 div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
1087 break;
1088
1089 default:
1090 return -ENOENT;
1091 }
1092
1093 if ((priv->gpll_hz % rate) == 0) {
1094 prate = priv->gpll_hz;
1095 sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask;
1096 } else {
1097 prate = priv->cpll_hz;
1098 sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask;
1099 }
1100
1101 div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask;
1102 rk_clrsetreg(&cru->clksel_con[id], sel, div);
1103
1104 return rk3528_dclk_vop_get_clk(priv, clk_id);
1105}
1106
1107static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id)
1108{
1109 struct rk3528_cru *cru = priv->cru;
1110 u32 sel_shift, sel_mask, div_shift, div_mask;
1111 u32 sel, id, con, frac_div, div;
1112 ulong m, n, rate;
1113
1114 switch (clk_id) {
1115 case SCLK_UART0:
1116 id = 6;
1117 sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
1118 sel_mask = SCLK_UART0_SRC_SEL_MASK;
1119 div_shift = CLK_UART0_SRC_DIV_SHIFT;
1120 div_mask = CLK_UART0_SRC_DIV_MASK;
1121 break;
1122
1123 case SCLK_UART1:
1124 id = 8;
1125 sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
1126 sel_mask = SCLK_UART1_SRC_SEL_MASK;
1127 div_shift = CLK_UART1_SRC_DIV_SHIFT;
1128 div_mask = CLK_UART1_SRC_DIV_MASK;
1129 break;
1130
1131 case SCLK_UART2:
1132 id = 10;
1133 sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
1134 sel_mask = SCLK_UART2_SRC_SEL_MASK;
1135 div_shift = CLK_UART2_SRC_DIV_SHIFT;
1136 div_mask = CLK_UART2_SRC_DIV_MASK;
1137 break;
1138
1139 case SCLK_UART3:
1140 id = 12;
1141 sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
1142 sel_mask = SCLK_UART3_SRC_SEL_MASK;
1143 div_shift = CLK_UART3_SRC_DIV_SHIFT;
1144 div_mask = CLK_UART3_SRC_DIV_MASK;
1145 break;
1146
1147 case SCLK_UART4:
1148 id = 14;
1149 sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
1150 sel_mask = SCLK_UART4_SRC_SEL_MASK;
1151 div_shift = CLK_UART4_SRC_DIV_SHIFT;
1152 div_mask = CLK_UART4_SRC_DIV_MASK;
1153 break;
1154
1155 case SCLK_UART5:
1156 id = 16;
1157 sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
1158 sel_mask = SCLK_UART5_SRC_SEL_MASK;
1159 div_shift = CLK_UART5_SRC_DIV_SHIFT;
1160 div_mask = CLK_UART5_SRC_DIV_MASK;
1161 break;
1162
1163 case SCLK_UART6:
1164 id = 18;
1165 sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
1166 sel_mask = SCLK_UART6_SRC_SEL_MASK;
1167 div_shift = CLK_UART6_SRC_DIV_SHIFT;
1168 div_mask = CLK_UART6_SRC_DIV_MASK;
1169 break;
1170
1171 case SCLK_UART7:
1172 id = 20;
1173 sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
1174 sel_mask = SCLK_UART7_SRC_SEL_MASK;
1175 div_shift = CLK_UART7_SRC_DIV_SHIFT;
1176 div_mask = CLK_UART7_SRC_DIV_MASK;
1177 break;
1178
1179 default:
1180 return -ENOENT;
1181 }
1182
1183 con = readl(&cru->clksel_con[id - 2]);
1184 div = (con & div_mask) >> div_shift;
1185
1186 con = readl(&cru->clksel_con[id]);
1187 sel = (con & sel_mask) >> sel_shift;
1188
1189 if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) {
1190 rate = DIV_TO_RATE(priv->gpll_hz, div);
1191 } else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) {
1192 frac_div = readl(&cru->clksel_con[id - 1]);
1193 n = (frac_div & 0xffff0000) >> 16;
1194 m = frac_div & 0x0000ffff;
1195 rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m;
1196 } else {
1197 rate = OSC_HZ;
1198 }
1199
1200 return rate;
1201}
1202
1203static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv,
1204 ulong clk_id, ulong rate)
1205{
1206 struct rk3528_cru *cru = priv->cru;
1207 u32 sel_shift, sel_mask, div_shift, div_mask;
1208 u32 sel, id, div;
1209 ulong m = 0, n = 0, val;
1210
1211 if (rate == OSC_HZ) {
1212 sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC;
1213 div = DIV_ROUND_UP(OSC_HZ, rate);
1214 } else if (priv->gpll_hz % rate == 0) {
1215 sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC;
1216 div = DIV_ROUND_UP(priv->gpll_hz, rate);
1217 } else {
1218 sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC;
1219 div = 2;
1220 rational_best_approximation(rate, priv->gpll_hz / div,
1221 GENMASK(16 - 1, 0),
1222 GENMASK(16 - 1, 0),
1223 &n, &m);
1224 }
1225
1226 switch (clk_id) {
1227 case SCLK_UART0:
1228 id = 6;
1229 sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
1230 sel_mask = SCLK_UART0_SRC_SEL_MASK;
1231 div_shift = CLK_UART0_SRC_DIV_SHIFT;
1232 div_mask = CLK_UART0_SRC_DIV_MASK;
1233 break;
1234
1235 case SCLK_UART1:
1236 id = 8;
1237 sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
1238 sel_mask = SCLK_UART1_SRC_SEL_MASK;
1239 div_shift = CLK_UART1_SRC_DIV_SHIFT;
1240 div_mask = CLK_UART1_SRC_DIV_MASK;
1241 break;
1242
1243 case SCLK_UART2:
1244 id = 10;
1245 sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
1246 sel_mask = SCLK_UART2_SRC_SEL_MASK;
1247 div_shift = CLK_UART2_SRC_DIV_SHIFT;
1248 div_mask = CLK_UART2_SRC_DIV_MASK;
1249 break;
1250
1251 case SCLK_UART3:
1252 id = 12;
1253 sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
1254 sel_mask = SCLK_UART3_SRC_SEL_MASK;
1255 div_shift = CLK_UART3_SRC_DIV_SHIFT;
1256 div_mask = CLK_UART3_SRC_DIV_MASK;
1257 break;
1258
1259 case SCLK_UART4:
1260 id = 14;
1261 sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
1262 sel_mask = SCLK_UART4_SRC_SEL_MASK;
1263 div_shift = CLK_UART4_SRC_DIV_SHIFT;
1264 div_mask = CLK_UART4_SRC_DIV_MASK;
1265 break;
1266
1267 case SCLK_UART5:
1268 id = 16;
1269 sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
1270 sel_mask = SCLK_UART5_SRC_SEL_MASK;
1271 div_shift = CLK_UART5_SRC_DIV_SHIFT;
1272 div_mask = CLK_UART5_SRC_DIV_MASK;
1273 break;
1274
1275 case SCLK_UART6:
1276 id = 18;
1277 sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
1278 sel_mask = SCLK_UART6_SRC_SEL_MASK;
1279 div_shift = CLK_UART6_SRC_DIV_SHIFT;
1280 div_mask = CLK_UART6_SRC_DIV_MASK;
1281 break;
1282
1283 case SCLK_UART7:
1284 id = 20;
1285 sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
1286 sel_mask = SCLK_UART7_SRC_SEL_MASK;
1287 div_shift = CLK_UART7_SRC_DIV_SHIFT;
1288 div_mask = CLK_UART7_SRC_DIV_MASK;
1289 break;
1290
1291 default:
1292 return -ENOENT;
1293 }
1294
1295 rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift);
1296 rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift);
1297 if (m && n) {
1298 val = n << 16 | m;
1299 writel(val, &cru->clksel_con[id - 1]);
1300 }
1301
1302 return rk3528_uart_get_rate(priv, clk_id);
1303}
1304
1305static ulong rk3528_clk_get_rate(struct clk *clk)
1306{
1307 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
1308 ulong rate = 0;
1309
1310 if (!priv->gpll_hz || !priv->cpll_hz) {
1311 printf("%s: gpll=%lu, cpll=%ld\n",
1312 __func__, priv->gpll_hz, priv->cpll_hz);
1313 return -ENOENT;
1314 }
1315
1316 switch (clk->id) {
1317 case PLL_APLL:
1318 case ARMCLK:
1319 rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru,
1320 APLL);
1321 break;
1322 case PLL_CPLL:
1323 rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru,
1324 CPLL);
1325 break;
1326 case PLL_GPLL:
1327 rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru,
1328 GPLL);
1329 break;
1330
1331 case PLL_PPLL:
1332 rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru,
1333 PPLL);
1334 break;
1335 case PLL_DPLL:
1336 rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru,
1337 DPLL);
1338 break;
1339
1340 case TCLK_EMMC:
1341 case TCLK_WDT_NS:
1342 rate = OSC_HZ;
1343 break;
1344 case CLK_I2C0:
1345 case CLK_I2C1:
1346 case CLK_I2C2:
1347 case CLK_I2C3:
1348 case CLK_I2C4:
1349 case CLK_I2C5:
1350 case CLK_I2C6:
1351 case CLK_I2C7:
1352 rate = rk3528_i2c_get_clk(priv, clk->id);
1353 break;
1354 case CLK_SPI0:
1355 case CLK_SPI1:
1356 rate = rk3528_spi_get_clk(priv, clk->id);
1357 break;
1358 case CLK_PWM0:
1359 case CLK_PWM1:
1360 rate = rk3528_pwm_get_clk(priv, clk->id);
1361 break;
1362 case CLK_SARADC:
1363 case CLK_TSADC:
1364 case CLK_TSADC_TSEN:
1365 rate = rk3528_adc_get_clk(priv, clk->id);
1366 break;
1367 case CCLK_SRC_EMMC:
1368 rate = rk3528_emmc_get_clk(priv);
1369 break;
1370 case HCLK_SDMMC0:
1371 case CCLK_SRC_SDMMC0:
1372 rate = rk3528_sdmmc_get_clk(priv, clk->id);
1373 break;
1374 case SCLK_SFC:
1375 rate = rk3528_sfc_get_clk(priv);
1376 break;
1377 case DCLK_VOP0:
1378 case DCLK_VOP1:
1379 rate = rk3528_dclk_vop_get_clk(priv, clk->id);
1380 break;
1381 case DCLK_CVBS:
1382 rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4;
1383 break;
1384 case DCLK_4X_CVBS:
1385 rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1);
1386 break;
1387 case SCLK_UART0:
1388 case SCLK_UART1:
1389 case SCLK_UART2:
1390 case SCLK_UART3:
1391 case SCLK_UART4:
1392 case SCLK_UART5:
1393 case SCLK_UART6:
1394 case SCLK_UART7:
1395 rate = rk3528_uart_get_rate(priv, clk->id);
1396 break;
1397 case CLK_MATRIX_50M_SRC:
1398 case CLK_MATRIX_100M_SRC:
1399 case CLK_MATRIX_150M_SRC:
1400 case CLK_MATRIX_200M_SRC:
1401 case CLK_MATRIX_250M_SRC:
1402 case CLK_MATRIX_300M_SRC:
1403 case CLK_MATRIX_339M_SRC:
1404 case CLK_MATRIX_400M_SRC:
1405 case CLK_MATRIX_500M_SRC:
1406 case CLK_MATRIX_600M_SRC:
1407 case ACLK_BUS_VOPGL_BIU:
1408 rate = rk3528_cgpll_matrix_get_rate(priv, clk->id);
1409 break;
1410 case CLK_PPLL_50M_MATRIX:
1411 case CLK_PPLL_100M_MATRIX:
1412 case CLK_PPLL_125M_MATRIX:
1413 case CLK_GMAC1_VPU_25M:
1414 case CLK_GMAC1_RMII_VPU:
1415 case CLK_GMAC1_SRC_VPU:
1416 rate = rk3528_ppll_matrix_get_rate(priv, clk->id);
1417 break;
1418 default:
1419 return -ENOENT;
1420 }
1421
1422 return rate;
1423};
1424
1425static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
1426{
1427 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
1428 ulong ret = 0;
1429
1430 if (!priv->gpll_hz) {
1431 printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
1432 return -ENOENT;
1433 }
1434
1435 switch (clk->id) {
1436 case PLL_APLL:
1437 case ARMCLK:
1438 if (priv->armclk_hz)
1439 rk3528_armclk_set_clk(priv, rate);
1440 priv->armclk_hz = rate;
1441 break;
1442 case PLL_CPLL:
1443 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
1444 CPLL, rate);
1445 priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL],
1446 priv->cru, CPLL);
1447 break;
1448 case PLL_GPLL:
1449 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
1450 GPLL, rate);
1451 priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL],
1452 priv->cru, GPLL);
1453 break;
1454 case PLL_PPLL:
1455 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
1456 PPLL, rate);
1457 priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
1458 priv->cru, PPLL);
1459 break;
1460 case TCLK_EMMC:
1461 case TCLK_WDT_NS:
1462 return (rate == OSC_HZ) ? 0 : -EINVAL;
1463 case CLK_I2C0:
1464 case CLK_I2C1:
1465 case CLK_I2C2:
1466 case CLK_I2C3:
1467 case CLK_I2C4:
1468 case CLK_I2C5:
1469 case CLK_I2C6:
1470 case CLK_I2C7:
1471 ret = rk3528_i2c_set_clk(priv, clk->id, rate);
1472 break;
1473 case CLK_SPI0:
1474 case CLK_SPI1:
1475 ret = rk3528_spi_set_clk(priv, clk->id, rate);
1476 break;
1477 case CLK_PWM0:
1478 case CLK_PWM1:
1479 ret = rk3528_pwm_set_clk(priv, clk->id, rate);
1480 break;
1481 case CLK_SARADC:
1482 case CLK_TSADC:
1483 case CLK_TSADC_TSEN:
1484 ret = rk3528_adc_set_clk(priv, clk->id, rate);
1485 break;
1486 case HCLK_SDMMC0:
1487 case CCLK_SRC_SDMMC0:
1488 ret = rk3528_sdmmc_set_clk(priv, clk->id, rate);
1489 break;
1490 case SCLK_SFC:
1491 ret = rk3528_sfc_set_clk(priv, rate);
1492 break;
1493 case CCLK_SRC_EMMC:
1494 ret = rk3528_emmc_set_clk(priv, rate);
1495 break;
1496 case DCLK_VOP0:
1497 case DCLK_VOP1:
1498 ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate);
1499 break;
1500 case SCLK_UART0:
1501 case SCLK_UART1:
1502 case SCLK_UART2:
1503 case SCLK_UART3:
1504 case SCLK_UART4:
1505 case SCLK_UART5:
1506 case SCLK_UART6:
1507 case SCLK_UART7:
1508 ret = rk3528_uart_set_rate(priv, clk->id, rate);
1509 break;
1510 case CLK_MATRIX_50M_SRC:
1511 case CLK_MATRIX_100M_SRC:
1512 case CLK_MATRIX_150M_SRC:
1513 case CLK_MATRIX_200M_SRC:
1514 case CLK_MATRIX_250M_SRC:
1515 case CLK_MATRIX_300M_SRC:
1516 case CLK_MATRIX_339M_SRC:
1517 case CLK_MATRIX_400M_SRC:
1518 case CLK_MATRIX_500M_SRC:
1519 case CLK_MATRIX_600M_SRC:
1520 case ACLK_BUS_VOPGL_BIU:
1521 ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate);
1522 break;
1523 case CLK_PPLL_50M_MATRIX:
1524 case CLK_PPLL_100M_MATRIX:
1525 case CLK_PPLL_125M_MATRIX:
1526 case CLK_GMAC1_VPU_25M:
1527 ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate);
1528 break;
1529 case CLK_GMAC1_RMII_VPU:
1530 case CLK_GMAC1_SRC_VPU:
1531 /* dummy set */
1532 ret = rk3528_ppll_matrix_get_rate(priv, clk->id);
1533 break;
1534
1535 /* Might occur in cru assigned-clocks, can be ignored here */
1536 case ACLK_BUS_VOPGL_ROOT:
1537 case BCLK_EMMC:
1538 case XIN_OSC0_DIV:
1539 ret = 0;
1540 break;
1541 default:
1542 return -ENOENT;
1543 }
1544
1545 return ret;
1546};
1547
1548static struct clk_ops rk3528_clk_ops = {
1549 .get_rate = rk3528_clk_get_rate,
1550 .set_rate = rk3528_clk_set_rate,
1551};
1552
1553#ifdef CONFIG_XPL_BUILD
1554
1555#define COREGRF_BASE 0xff300000
1556#define PVTPLL_CON0_L 0x0
1557#define PVTPLL_CON0_H 0x4
1558
1559static int rk3528_cpu_pvtpll_set_rate(struct rk3528_clk_priv *priv, ulong rate)
1560{
1561 struct rk3528_cru *cru = priv->cru;
1562 u32 length;
1563
1564 if (rate >= 1200000000)
1565 length = 8;
1566 else if (rate >= 1008000000)
1567 length = 11;
1568 else
1569 length = 17;
1570
1571 /* set pclk dbg div to 9 */
1572 rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
1573 9 << RK3528_DIV_PCLK_DBG_SHIFT);
1574 /* set aclk_m_core div to 1 */
1575 rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
1576 1 << RK3528_DIV_ACLK_M_CORE_SHIFT);
1577
1578 /* set ring sel = 1 */
1579 writel(0x07000000 | (1 << 8), COREGRF_BASE + PVTPLL_CON0_L);
1580 /* set length */
1581 writel(0x007f0000 | length, COREGRF_BASE + PVTPLL_CON0_H);
1582 /* enable pvtpll */
1583 writel(0x00020002, COREGRF_BASE + PVTPLL_CON0_L);
1584 /* start monitor */
1585 writel(0x00010001, COREGRF_BASE + PVTPLL_CON0_L);
1586
1587 /* set core mux pvtpll */
1588 writel(0x00010001, &cru->clksel_con[40]);
1589 writel(0x00100010, &cru->clksel_con[39]);
1590
1591 /* set pclk dbg div to 8 */
1592 rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
1593 8 << RK3528_DIV_PCLK_DBG_SHIFT);
1594
1595 return 0;
1596}
1597#endif
1598
1599static int rk3528_clk_init(struct rk3528_clk_priv *priv)
1600{
1601 int ret;
1602
1603 priv->sync_kernel = false;
1604
1605#ifdef CONFIG_XPL_BUILD
1606 /*
1607 * BOOTROM:
1608 * CPU 1902/2(postdiv1)=546M
1609 * CPLL 996/2(postdiv1)=498M
1610 * GPLL 1188/2(postdiv1)=594M
1611 * |-- clk_matrix_200m_src_div=1 => rate: 300M
1612 * |-- clk_matrix_300m_src_div=2 => rate: 200M
1613 *
1614 * Avoid overclocking when change GPLL rate:
1615 * Change clk_matrix_200m_src_div to 5.
1616 * Change clk_matrix_300m_src_div to 3.
1617 */
1618 writel(0x01200120, &priv->cru->clksel_con[1]);
1619 writel(0x00030003, &priv->cru->clksel_con[2]);
1620
1621 if (!priv->armclk_enter_hz) {
1622 priv->armclk_enter_hz =
1623 rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
1624 priv->cru, APLL);
1625 priv->armclk_init_hz = priv->armclk_enter_hz;
1626 }
1627
1628 if (priv->armclk_init_hz != APLL_HZ) {
1629 ret = rk3528_armclk_set_clk(priv, APLL_HZ);
1630 if (!ret)
1631 priv->armclk_init_hz = APLL_HZ;
1632 }
1633
1634 if (!rk3528_cpu_pvtpll_set_rate(priv, CPU_PVTPLL_HZ)) {
1635 debug("cpu pvtpll %d KHz\n", CPU_PVTPLL_HZ / 1000);
1636 priv->armclk_init_hz = CPU_PVTPLL_HZ;
1637 }
1638#endif
1639
1640 if (priv->cpll_hz != CPLL_HZ) {
1641 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
1642 CPLL, CPLL_HZ);
1643 if (!ret)
1644 priv->cpll_hz = CPLL_HZ;
1645 }
1646
1647 if (priv->gpll_hz != GPLL_HZ) {
1648 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
1649 GPLL, GPLL_HZ);
1650 if (!ret)
1651 priv->gpll_hz = GPLL_HZ;
1652 }
1653
1654 if (priv->ppll_hz != PPLL_HZ) {
1655 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
1656 PPLL, PPLL_HZ);
1657 if (!ret)
1658 priv->ppll_hz = PPLL_HZ;
1659 }
1660
1661#ifdef CONFIG_XPL_BUILD
1662 /* Init to override bootrom config */
1663 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_50M_SRC, 50000000);
1664 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_100M_SRC, 100000000);
1665 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_150M_SRC, 150000000);
1666 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_200M_SRC, 200000000);
1667 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_250M_SRC, 250000000);
1668 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_300M_SRC, 300000000);
1669 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_339M_SRC, 340000000);
1670 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_400M_SRC, 400000000);
1671 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_500M_SRC, 500000000);
1672 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_600M_SRC, 600000000);
1673 rk3528_cgpll_matrix_set_rate(priv, ACLK_BUS_VOPGL_BIU, 500000000);
1674
1675 /* The default rate is 100Mhz, it's not friendly for remote IR module */
1676 rk3528_pwm_set_clk(priv, CLK_PWM0, 24000000);
1677 rk3528_pwm_set_clk(priv, CLK_PWM1, 24000000);
1678#endif
1679 return 0;
1680}
1681
1682static int rk3528_clk_probe(struct udevice *dev)
1683{
1684 struct rk3528_clk_priv *priv = dev_get_priv(dev);
1685 int ret;
1686
1687 ret = rk3528_clk_init(priv);
1688 if (ret)
1689 return ret;
1690
1691 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1692 ret = clk_set_defaults(dev, 1);
1693 if (ret)
1694 debug("%s clk_set_defaults failed %d\n", __func__, ret);
1695 else
1696 priv->sync_kernel = true;
1697
1698 return 0;
1699}
1700
1701static int rk3528_clk_ofdata_to_platdata(struct udevice *dev)
1702{
1703 struct rk3528_clk_priv *priv = dev_get_priv(dev);
1704
1705 priv->cru = dev_read_addr_ptr(dev);
1706
1707 return 0;
1708}
1709
1710static int rk3528_clk_bind(struct udevice *dev)
1711{
1712 struct udevice *sys_child;
1713 struct sysreset_reg *priv;
1714 int ret;
1715
1716 /* The reset driver does not have a device node, so bind it here */
1717 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1718 &sys_child);
1719 if (ret) {
1720 debug("Warning: No sysreset driver: ret=%d\n", ret);
1721 } else {
1722 priv = malloc(sizeof(struct sysreset_reg));
1723 priv->glb_srst_fst_value = offsetof(struct rk3528_cru,
1724 glb_srst_fst);
1725 priv->glb_srst_snd_value = offsetof(struct rk3528_cru,
1726 glb_srst_snd);
1727 dev_set_priv(sys_child, priv);
1728 }
1729
1730#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1731 ret = offsetof(struct rk3528_cru, softrst_con[0]);
1732 ret = rk3528_reset_bind_lut(dev, ret, 47);
1733 if (ret)
1734 debug("Warning: software reset driver bind failed\n");
1735#endif
1736
1737 return 0;
1738}
1739
1740static const struct udevice_id rk3528_clk_ids[] = {
1741 { .compatible = "rockchip,rk3528-cru" },
1742 { }
1743};
1744
1745U_BOOT_DRIVER(rockchip_rk3528_cru) = {
1746 .name = "rockchip_rk3528_cru",
1747 .id = UCLASS_CLK,
1748 .of_match = rk3528_clk_ids,
1749 .priv_auto = sizeof(struct rk3528_clk_priv),
1750 .of_to_plat = rk3528_clk_ofdata_to_platdata,
1751 .ops = &rk3528_clk_ops,
1752 .bind = rk3528_clk_bind,
1753 .probe = rk3528_clk_probe,
1754};