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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vikas Manocha1b51c932016-02-11 15:47:20 -08002/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02003 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha1b51c932016-02-11 15:47:20 -08005 */
6
Tom Rinidec7ea02024-05-20 13:35:03 -06007#include <config.h>
Vikas Manocha096be332017-04-10 15:02:54 -07008#include <dm.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Patrice Chotardd8c77552019-02-22 15:04:44 +010011#include <miiphy.h>
12#include <phy_interface.h>
Vikas Manocha096be332017-04-10 15:02:54 -070013#include <ram.h>
Simon Glass36736182019-11-14 12:57:24 -070014#include <serial.h>
Vikas Manocha50218ae2017-05-28 12:55:10 -070015#include <spl.h>
yannick fertre030af822018-03-02 15:59:28 +010016#include <splash.h>
yannick fertre030af822018-03-02 15:59:28 +010017#include <video.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060018#include <asm/global_data.h>
Vikas Manocha1b51c932016-02-11 15:47:20 -080019#include <asm/io.h>
20#include <asm/armv7m.h>
21#include <asm/arch/stm32.h>
Michael Kurz812962b2017-01-22 16:04:27 +010022#include <asm/arch/syscfg.h>
Vikas Manocha9c7573e2017-04-10 15:03:00 -070023#include <asm/gpio.h>
Simon Glassdbd79542020-05-10 11:40:11 -060024#include <linux/delay.h>
Vikas Manocha1b51c932016-02-11 15:47:20 -080025
26DECLARE_GLOBAL_DATA_PTR;
27
Toshifumi NISHINAGA18bd7632016-07-08 01:02:25 +090028int dram_init(void)
29{
Simon Glass49c24a82024-09-29 19:49:47 -060030#ifndef CONFIG_XPL_BUILD
Patrice Chotardb75feec2018-08-03 13:09:55 +020031 int rv;
Vikas Manocha50218ae2017-05-28 12:55:10 -070032 struct udevice *dev;
Vikas Manocha096be332017-04-10 15:02:54 -070033 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
34 if (rv) {
35 debug("DRAM init failed: %d\n", rv);
36 return rv;
37 }
Vikas Manochab6fd9eb2017-04-10 15:03:01 -070038
Vikas Manocha50218ae2017-05-28 12:55:10 -070039#endif
Patrice Chotardb75feec2018-08-03 13:09:55 +020040 return fdtdec_setup_mem_size_base();
Vikas Manochab6fd9eb2017-04-10 15:03:01 -070041}
42
43int dram_init_banksize(void)
44{
Patrice Chotardb75feec2018-08-03 13:09:55 +020045 return fdtdec_setup_memory_banksize();
Toshifumi NISHINAGA18bd7632016-07-08 01:02:25 +090046}
47
Simon Glass49c24a82024-09-29 19:49:47 -060048#ifdef CONFIG_XPL_BUILD
Vikas Manochab785bb42017-05-28 12:55:13 -070049#ifdef CONFIG_SPL_OS_BOOT
50int spl_start_uboot(void)
51{
52 debug("SPL: booting kernel\n");
53 /* break into full u-boot on 'c' */
54 return serial_tstc() && serial_getc() == 'c';
55}
56#endif
57
Vikas Manocha50218ae2017-05-28 12:55:10 -070058int spl_dram_init(void)
59{
60 struct udevice *dev;
61 int rv;
62 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
63 if (rv)
64 debug("DRAM init failed: %d\n", rv);
65 return rv;
66}
67void spl_board_init(void)
68{
Vikas Manocha50218ae2017-05-28 12:55:10 -070069 preloader_console_init();
Giulio Benetti09d018f2021-04-04 20:21:35 +020070 spl_dram_init();
Vikas Manocha50218ae2017-05-28 12:55:10 -070071 arch_cpu_init(); /* to configure mpu for sdram rw permissions */
72}
73u32 spl_boot_device(void)
74{
Vikas Manochaf0e32c02017-05-28 12:55:14 -070075 return BOOT_DEVICE_XIP;
Vikas Manocha50218ae2017-05-28 12:55:10 -070076}
Vikas Manocha50218ae2017-05-28 12:55:10 -070077#endif
Vikas Manocha1b51c932016-02-11 15:47:20 -080078
79int board_init(void)
80{
Patrice Chotarde2d564e2018-01-18 14:10:05 +010081#ifdef CONFIG_ETH_DESIGNWARE
Marek Behúnbc194772022-04-07 00:33:01 +020082 ofnode node;
Patrice Chotardd8c77552019-02-22 15:04:44 +010083
Marek Behúnbc194772022-04-07 00:33:01 +020084 node = ofnode_by_compatible(ofnode_null(), "st,stm32-dwmac");
85 if (!ofnode_valid(node))
Patrice Chotardd8c77552019-02-22 15:04:44 +010086 return -1;
87
Marek Behúnbc194772022-04-07 00:33:01 +020088 switch (ofnode_read_phy_mode(node)) {
Patrice Chotardd8c77552019-02-22 15:04:44 +010089 case PHY_INTERFACE_MODE_RMII:
90 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
91 break;
92 case PHY_INTERFACE_MODE_MII:
93 STM32_SYSCFG->pmc &= ~SYSCFG_PMC_MII_RMII_SEL;
94 break;
95 default:
Marek Behúnbc194772022-04-07 00:33:01 +020096 printf("Unsupported PHY interface!\n");
Patrice Chotardd8c77552019-02-22 15:04:44 +010097 }
Patrice Chotarde2d564e2018-01-18 14:10:05 +010098#endif
99
Vikas Manocha1b51c932016-02-11 15:47:20 -0800100 return 0;
101}