Blame - arch/x86/cpu/i386/call64.S - filogic/uboot

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Tom Rini	10e4779	2018-05-06 17:58:06 -0400	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	2	/*
				3	* (C) Copyright 2014 Google, Inc
				4	* Copyright (C) 1991, 1992, 1993 Linus Torvalds
				5	*
				6	* Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	7	*/
				8
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	9	#include <asm/msr-index.h>
Simon Glass	e00a033	2025-03-15 14:25:38 +0000	[diff] [blame]	10	#include <asm/processor.h>
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	11	#include <asm/processor-flags.h>
				12
				13	.code32
Sam Edwards	7cc2ef9	2025-03-15 15:18:05 -0700	[diff] [blame]	14	.section .text_call64, "ax"
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	15	.globl cpu_call64
				16	cpu_call64:
				17	/*
				18	* cpu_call64(ulong pgtable, ulong setup_base, ulong target)
				19	*
				20	* eax - pgtable
				21	* edx - setup_base
				22	* ecx - target
				23	*/
				24	cli
Simon Glass	355dae2	2025-03-15 14:25:39 +0000	[diff] [blame]	25	pushl $0 /* top 64-bits of target */
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	26	push %ecx /* arg2 = target */
				27	push %edx /* arg1 = setup_base */
				28	mov %eax, %ebx
				29
Simon Glass	46faeea	2025-03-15 14:25:37 +0000	[diff] [blame]	30	# disable paging
				31	movl %cr0, %eax
				32	andl $~X86_CR0_PG, %eax
				33	movl %eax, %cr0
				34
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	35	/* Enable PAE mode */
Simon Glass	355dae2	2025-03-15 14:25:39 +0000	[diff] [blame]	36	movl %cr4, %eax
				37	orl $X86_CR4_PAE, %eax
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	38	movl %eax, %cr4
				39
				40	/* Enable the boot page tables */
				41	leal (%ebx), %eax
				42	movl %eax, %cr3
				43
				44	/* Enable Long mode in EFER (Extended Feature Enable Register) */
				45	movl $MSR_EFER, %ecx
				46	rdmsr
				47	btsl $_EFER_LME, %eax
				48	wrmsr
				49
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	50	/*
				51	* Setup for the jump to 64bit mode
				52	*
				53	* When the jump is performed we will be in long mode but
				54	* in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
				55	* (and in turn EFER.LMA = 1). To jump into 64bit mode we use
				56	* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
				57	* We place all of the values on our mini stack so lret can
				58	* used to perform that far jump. See the gdt below.
				59	*/
				60	pop %esi /* setup_base */
				61
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	62	/* Enter paged protected Mode, activating Long Mode */
Simon Glass	46faeea	2025-03-15 14:25:37 +0000	[diff] [blame]	63	movl %cr0, %eax
				64	orl $X86_CR0_PG, %eax
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	65	movl %eax, %cr0
				66
				67	/* Jump from 32bit compatibility mode into 64bit mode. */
Simon Glass	355dae2	2025-03-15 14:25:39 +0000	[diff] [blame]	68	ljmp $(X86_GDT_ENTRY_64BIT_CS * X86_GDT_ENTRY_SIZE), $lret_target
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	69
Simon Glass	355dae2	2025-03-15 14:25:39 +0000	[diff] [blame]	70	.code64
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	71	lret_target:
Simon Glass	355dae2	2025-03-15 14:25:39 +0000	[diff] [blame]	72	pop %rax /* target */
				73	jmp %rax / Jump to the 64-bit target */
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	74
Bin Meng	17b7b60	2019-01-31 08:22:13 -0800	[diff] [blame]	75	.globl call64_stub_size
				76	call64_stub_size:
				77	.long . - cpu_call64
				78
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	79	.data
Simon Glass	1e32ede	2017-01-16 07:04:15 -0700	[diff] [blame]	80	.align 16
				81	.globl gdt64
				82	gdt64:
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	83	gdt:
Simon Glass	f2d1a11	2015-07-31 09:31:30 -0600	[diff] [blame]	84	.word gdt_end - gdt - 1
				85	.long gdt /* Fixed up by code above */
Simon Glass	463fac2	2014-10-10 08:21:55 -0600	[diff] [blame]	86	.word 0
				87	.quad 0x0000000000000000 /* NULL descriptor */
				88	.quad 0x00af9a000000ffff /* __KERNEL_CS */
				89	.quad 0x00cf92000000ffff /* __KERNEL_DS */
				90	.quad 0x0080890000000000 /* TS descriptor */
				91	.quad 0x0000000000000000 /* TS continued */
				92	gdt_end: