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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / x86 / cpu / apollolake / Kconfig
blob: 5dd866ffcfe48c1560f5d4a4e38cb9b96c8d183c [file] [log] [blame]
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]1# SPDX-License-Identifier: GPL-2.0
2#
3# Copyright 2019 Google LLC
4#
5
6config INTEL_APOLLOLAKE
7 bool
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]8 select HAVE_FSP
9 select ARCH_MISC_INIT
10 select USE_CAR
Simon Glassc6eeff92021-02-23 05:35:42 -0500[diff] [blame]11 select INTEL_SOC
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]12 select INTEL_PMC
13 select TPL_X86_TSC_TIMER_NATIVE
Simon Glassff67f232021-08-08 12:20:10 -0600[diff] [blame]14 select SPL_PCH
15 select TPL_PCH
Simon Glass741ce462020-09-22 12:44:51 -0600[diff] [blame]16 select PCIEX_LENGTH_256MB
Simon Glassff67f232021-08-08 12:20:10 -0600[diff] [blame]17 select PCH
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]18 select P2SB
Simon Glass4a30bbb2020-07-17 08:48:16 -0600[diff] [blame]19 select SMP_AP_WORK
Simon Glassc32fbb62020-09-22 12:45:15 -0600[diff] [blame]20 select INTEL_GMA_SWSMISCI
Simon Glass6fe570a2020-09-22 12:44:53 -0600[diff] [blame]21 select ACPI_GNVS_EXTERNAL
Simon Glass37ad5f32020-12-22 19:30:25 -0700[diff] [blame]22 select TPL_OF_PLATDATA_PARENT
Simon Glass02849162021-03-15 17:25:52 +1300[diff] [blame]23 select TPL_OF_PLATDATA_INST
24 select TPL_READ_ONLY
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]25 imply ENABLE_MRC_CACHE
26 imply AHCI_PCI
27 imply SCSI
28 imply SCSI_AHCI
29 imply SPI_FLASH
30 imply USB
31 imply USB_EHCI_HCD
32 imply TPL
33 imply SPL
34 imply TPL_X86_16BIT_INIT
35 imply TPL_OF_PLATDATA
36 imply ACPI_PMC
37 imply MMC
38 imply DM_MMC
39 imply MMC_PCI
40 imply MMC_SDHCI
41 imply CMD_MMC
42 imply VIDEO_FSP
43 imply PINCTRL_INTEL
44 imply PINCTRL_INTEL_APL
45 imply HAVE_VBT
46 imply HAVE_X86_FIT
47 imply INTEL_GPIO
48 imply SMP
Wolfgang Wallnerb5460dd2020-02-03 14:06:45 +0100[diff] [blame]49 imply HAVE_ITSS
Wolfgang Wallner21fae582020-02-04 09:04:56 +0100[diff] [blame]50 imply HAVE_P2SB
Simon Glass4a2c26a2020-02-06 09:54:54 -0700[diff] [blame]51 imply CLK
52 imply CMD_CLK
53 imply CLK_INTEL
Simon Glassc0619742020-02-06 09:55:02 -0700[diff] [blame]54 imply ACPI_GPE
Simon Glass057427c2020-09-22 12:45:03 -0600[diff] [blame]55 imply INTEL_GMA_ACPI
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]56
57if INTEL_APOLLOLAKE
58
59config DCACHE_RAM_BASE
60 default 0xfef00000
61
62config DCACHE_RAM_SIZE
63 default 0xc0000
64
65config DCACHE_RAM_MRC_VAR_SIZE
66 default 0xb0000
67
68config CPU_SPECIFIC_OPTIONS
69 def_bool y
70 select SMM_TSEG
71 select X86_RAMTEST
72
73config SMM_TSEG_SIZE
74 hex
75 default 0x800000
76
77config MMCONF_BASE_ADDRESS
78 hex
79 default 0xe0000000
80
81config TPL_SIZE_LIMIT
82 default 0x7800
83
84config CPU_ADDR_BITS
85 default 39
86
87config APL_SPI_FLASH_BOOT
88 bool "Support booting with SPI-flash driver instead memory-mapped SPI"
89 select TPL_SPI_FLASH_SUPPORT
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]90 select TPL_SPI
Simon Glassecdc4b32020-10-03 11:31:38 -0600[diff] [blame]91 select TPL_DM_SPI
92 select TPL_DM_SPI_FLASH
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]93 help
94 This enables SPI and SPI flash in TPL. Without the this only
95 available boot method is to use memory-mapped SPI. Since this is
96 actually fast and produces a TPL which is 7KB smaller, memory-mapped
97 SPI is the default.
98
99config APL_BOOT_FROM_FAST_SPI_FLASH
100 bool "Boot using SPI flash driver"
101 select APL_SPI_FLASH_BOOT
102 help
103 This option is separate from APL_SPI_FLASH_BOOT since it is useful to
104 be able to compare booting speed with the same build. Enable this to
105 use the SPI-flash driver to load SPL, U-Boot and FSP-M. For technical
106 reasons FSP-S is currently always loaded from memory-mapped SPI. See
107 Apollo Lake's arch_fsp_init_r() for details about that.
108
109config VBT_ADDR
110 default 0xff3f1000
111
112endif