Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / mach-socfpga / mmu-arm64_s10.c
blob: 1dc44ab47972bac02215514e8e5a8478c9272e05 [file] [log] [blame]
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]3 * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]4 *
5 */
6
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]7#include <asm/armv8/mmu.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]8#include <asm/global_data.h>
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]9
10DECLARE_GLOBAL_DATA_PTR;
11
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]12#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
13static struct mm_region socfpga_agilex5_mem_map[] = {
14 {
15 /* OCRAM 512KB */
16 .virt = 0x00000000UL,
17 .phys = 0x00000000UL,
18 .size = 0x00080000UL,
19 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
20 PTE_BLOCK_NON_SHARE,
21 }, {
22 /* DEVICE */
23 .virt = 0x10808000UL,
24 .phys = 0x10808000UL,
25 .size = 0x0F7F8000UL,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 PTE_BLOCK_NON_SHARE |
28 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
29 }, {
30 /* FPGA 1.5GB */
31 .virt = 0x20000000UL,
32 .phys = 0x20000000UL,
33 .size = 0x60000000UL,
34 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
35 PTE_BLOCK_NON_SHARE |
36 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
37 }, {
38 /* FPGA 15GB */
39 .virt = 0x440000000UL,
40 .phys = 0x440000000UL,
41 .size = 0x3C0000000UL,
42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
43 PTE_BLOCK_NON_SHARE |
44 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
45 }, {
46 /* FPGA 240GB */
47 .virt = 0x4400000000UL,
48 .phys = 0x4400000000UL,
49 .size = 0x3C00000000UL,
50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51 PTE_BLOCK_NON_SHARE |
52 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
53 }, {
54 /* MEM 2GB */
55 .virt = 0x80000000UL,
56 .phys = 0x80000000UL,
57 .size = 0x80000000UL,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
59 PTE_BLOCK_INNER_SHARE,
60 }, {
Tingting Meng4130afa2025-03-10 15:29:41 +0800[diff] [blame]61 /* MEM 30GB */
62 .virt = 0x880000000UL,
63 .phys = 0x880000000UL,
64 .size = 0x780000000UL,
65 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
66 PTE_BLOCK_INNER_SHARE,
67 }, {
68 /* MEM 480GB */
69 .virt = 0x8800000000UL,
70 .phys = 0x8800000000UL,
71 .size = 0x7800000000UL,
72 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
73 PTE_BLOCK_INNER_SHARE,
74 }, {
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]75 /* List terminator */
76 },
77};
78
79struct mm_region *mem_map = socfpga_agilex5_mem_map;
80
81#else
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]82static struct mm_region socfpga_stratix10_mem_map[] = {
83 {
84 /* MEM 2GB*/
85 .virt = 0x0UL,
86 .phys = 0x0UL,
87 .size = 0x80000000UL,
88 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
89 PTE_BLOCK_INNER_SHARE,
90 }, {
91 /* FPGA 1.5GB */
92 .virt = 0x80000000UL,
93 .phys = 0x80000000UL,
94 .size = 0x60000000UL,
95 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
96 PTE_BLOCK_NON_SHARE |
97 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
98 }, {
99 /* DEVICE 142MB */
100 .virt = 0xF7000000UL,
101 .phys = 0xF7000000UL,
102 .size = 0x08E00000UL,
103 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
104 PTE_BLOCK_NON_SHARE |
105 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
106 }, {
107 /* OCRAM 1MB but available 256KB */
108 .virt = 0xFFE00000UL,
109 .phys = 0xFFE00000UL,
110 .size = 0x00100000UL,
111 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
112 PTE_BLOCK_INNER_SHARE,
113 }, {
114 /* DEVICE 32KB */
115 .virt = 0xFFFC0000UL,
116 .phys = 0xFFFC0000UL,
117 .size = 0x00008000UL,
118 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
119 PTE_BLOCK_NON_SHARE |
120 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
121 }, {
122 /* MEM 124GB */
123 .virt = 0x0100000000UL,
124 .phys = 0x0100000000UL,
125 .size = 0x1F00000000UL,
126 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
127 PTE_BLOCK_INNER_SHARE,
128 }, {
129 /* DEVICE 4GB */
130 .virt = 0x2000000000UL,
131 .phys = 0x2000000000UL,
132 .size = 0x0100000000UL,
133 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
134 PTE_BLOCK_NON_SHARE |
135 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
136 }, {
137 /* List terminator */
138 },
139};
140
141struct mm_region *mem_map = socfpga_stratix10_mem_map;
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]142#endif