blob: 3bc482331c7e7e5bb40270dab8fe6a2d8a986dad [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kever Yang5db9e672017-06-23 16:11:05 +08002/*
3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
Kever Yang5db9e672017-06-23 16:11:05 +08004 */
5
Tom Rinidec7ea02024-05-20 13:35:03 -06006#include <config.h>
Kever Yang5db9e672017-06-23 16:11:05 +08007#include <dm.h>
Simon Glass6980b6b2019-11-14 12:57:45 -07008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Kever Yang5db9e672017-06-23 16:11:05 +080010#include <ram.h>
Quentin Schulz6ba06862024-04-25 12:46:24 +020011#include <asm/armv8/mmu.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Kever Yang5db9e672017-06-23 16:11:05 +080013#include <asm/io.h>
Kever Yange47db832019-11-15 11:04:33 +080014#include <asm/arch-rockchip/sdram.h>
Kever Yang5db9e672017-06-23 16:11:05 +080015#include <dm/uclass-internal.h>
16
17DECLARE_GLOBAL_DATA_PTR;
Kever Yangdfc8a7d2019-07-22 20:02:02 +080018
19#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
20
21struct tos_parameter_t {
22 u32 version;
23 u32 checksum;
24 struct {
25 char name[8];
26 s64 phy_addr;
27 u32 size;
28 u32 flags;
29 } tee_mem;
30 struct {
31 char name[8];
32 s64 phy_addr;
33 u32 size;
34 u32 flags;
35 } drm_mem;
36 s64 reserve[8];
37};
38
Quentin Schulz6ba06862024-04-25 12:46:24 +020039#ifdef CONFIG_ARM64
40/* Tag size and offset */
41#define ATAGS_SIZE SZ_8K
42#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
43#define ATAGS_PHYS_BASE (CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
44#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
45
46/* ATAGS memory structures */
47
48enum tag_magic {
49 ATAG_NONE,
50 ATAG_CORE = 0x54410001,
51 ATAG_SERIAL = 0x54410050,
52 ATAG_DDR_MEM = 0x54410052,
53 ATAG_MAX = 0x544100ff,
54};
55
56/*
57 * An ATAG contains the following data:
58 * - header
59 * u32 size // sizeof(header + tag data) / sizeof(u32)
60 * u32 magic
61 * - tag data
62 */
63
64struct tag_header {
65 u32 size;
66 u32 magic;
67} __packed;
68
69/*
70 * DDR_MEM tag bank is storing data this way:
71 * - address0
72 * - address1
73 * - [...]
74 * - addressX
75 * - size0
76 * - size1
77 * - [...]
78 * - sizeX
79 *
80 * with X being tag_ddr_mem.count - 1.
81 */
82struct tag_ddr_mem {
83 u32 count;
84 u32 version;
85 u64 bank[20];
86 u32 flags;
87 u32 data[2];
88 u32 hash;
89} __packed;
90
91static u32 js_hash(const void *buf, u32 len)
92{
93 u32 i, hash = 0x47C6A7E6;
94
95 if (!buf || !len)
96 return hash;
97
98 for (i = 0; i < len; i++)
99 hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
100
101 return hash;
102}
103
104static int rockchip_dram_init_banksize(void)
105{
106 const struct tag_header *tag_h = NULL;
107 u32 *addr = (void *)ATAGS_PHYS_BASE;
108 struct tag_ddr_mem *ddr_info;
109 u32 calc_hash;
110 u8 i, j;
111
112 if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
Xuhui Lin43623c22025-04-15 23:51:16 +0200113 !IS_ENABLED(CONFIG_ROCKCHIP_RK3576) &&
Jonas Karlmanc704a432025-04-07 22:46:48 +0000114 !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) &&
115 !IS_ENABLED(CONFIG_ROCKCHIP_RK3528))
Quentin Schulz6ba06862024-04-25 12:46:24 +0200116 return -ENOTSUPP;
117
118 if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
119 return -ENOTSUPP;
120
121 /* Find DDR_MEM tag */
122 while (addr < (u32 *)ATAGS_PHYS_END) {
123 tag_h = (const struct tag_header *)addr;
124
125 if (!tag_h->size) {
126 debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
127 return -ENODATA;
128 }
129
130 if (tag_h->magic == ATAG_DDR_MEM)
131 break;
132
133 switch (tag_h->magic) {
134 case ATAG_NONE:
135 case ATAG_CORE:
136 case ATAG_SERIAL ... ATAG_MAX:
137 addr += tag_h->size;
138 continue;
139 default:
140 debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
141 tag_h->magic, addr);
142 return -EINVAL;
143 }
144 }
145
146 if (addr >= (u32 *)ATAGS_PHYS_END ||
147 (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
148 debug("End of ATAGS, no DDR_MEM found\n");
149 return -ENODATA;
150 }
151
152 /* Data is right after the magic member of the tag_header struct */
153 ddr_info = (struct tag_ddr_mem *)(&tag_h->magic + 1);
154 if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) {
155 debug("Too many ATAG banks, got (%d) but max allowed (%d)\n",
156 ddr_info->count, CONFIG_NR_DRAM_BANKS);
157 return -ENOMEM;
158 }
159
160 if (!ddr_info->hash) {
161 debug("No hash for tag (0x%08x)\n", tag_h->magic);
162 } else {
163 calc_hash = js_hash(addr, sizeof(u32) * (tag_h->size - 1));
164
165 if (calc_hash != ddr_info->hash) {
166 debug("Incorrect hash for tag (0x%08x), got (0x%08x) expected (0x%08x)\n",
167 tag_h->magic, ddr_info->hash, calc_hash);
168 return -EINVAL;
169 }
170 }
171
172 /*
173 * Rockchip guaranteed DDR_MEM is ordered so no need to worry about
174 * bi_dram order.
175 */
176 for (i = 0, j = 0; i < ddr_info->count; i++, j++) {
177 phys_size_t size = ddr_info->bank[(i + ddr_info->count)];
178 phys_addr_t start_addr = ddr_info->bank[i];
179 struct mm_region *tmp_mem_map = mem_map;
180 phys_addr_t end_addr;
181
182 /*
183 * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
184 * have it, so force this space as reserved.
185 */
Heiko Stuebner0e6452b2025-04-15 23:51:14 +0200186 if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {
187 size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
188 start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
Quentin Schulz6ba06862024-04-25 12:46:24 +0200189 }
190
191 /*
192 * Put holes for reserved memory areas from mem_map.
193 *
194 * Only check for at most one overlap with one reserved memory
195 * area.
196 */
197 while (tmp_mem_map->size) {
198 const phys_addr_t rsrv_start = tmp_mem_map->phys;
199 const phys_size_t rsrv_size = tmp_mem_map->size;
200 const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
201
202 /*
203 * DRAM memories are expected by Arm to be marked as
204 * Normal Write-back cacheable, Inner shareable[1], so
205 * let's filter on that to put holes in non-DRAM areas.
206 *
207 * [1] https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
208 */
209 const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
210 PTE_BLOCK_INNER_SHARE;
211 /*
212 * (AttrIndx | SH) in Lower Attributes of Block
213 * Descriptor[2].
214 * [2] https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
215 */
216 const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9, 8);
217
218 if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
219 tmp_mem_map++;
220 continue;
221 }
222
223 /*
224 * If the start of the DDR_MEM tag is in a reserved
225 * memory area, move start address and resize.
226 */
227 if (start_addr >= rsrv_start && start_addr < rsrv_end) {
228 if (rsrv_end - start_addr > size) {
229 debug("Would be negative memory size\n");
230 return -EINVAL;
231 }
232
Heiko Stuebner0e6452b2025-04-15 23:51:14 +0200233 size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
Quentin Schulz6ba06862024-04-25 12:46:24 +0200234 start_addr = rsrv_end;
235 break;
236 }
237
238 if (start_addr < rsrv_start) {
239 end_addr = start_addr + size;
240
241 if (end_addr <= rsrv_start) {
242 tmp_mem_map++;
243 continue;
244 }
245
246 /*
247 * If the memory area overlaps a reserved memory
248 * area with start address outside of reserved
249 * memory area and...
250 *
251 * ... ends in the middle of reserved memory
252 * area, resize.
253 */
254 if (end_addr <= rsrv_end) {
255 size = rsrv_start - start_addr;
256 break;
257 }
258
259 /*
260 * ... ends after the reserved memory area,
261 * split the region in two, one for before the
262 * reserved memory area and one for after.
263 */
264 gd->bd->bi_dram[j].start = start_addr;
265 gd->bd->bi_dram[j].size = rsrv_start - start_addr;
266
267 j++;
268
269 size = end_addr - rsrv_end;
270 start_addr = rsrv_end;
271
272 break;
273 }
274
275 tmp_mem_map++;
276 }
277
278 if (j > CONFIG_NR_DRAM_BANKS) {
279 debug("Too many banks, max allowed (%d)\n",
280 CONFIG_NR_DRAM_BANKS);
281 return -ENOMEM;
282 }
283
284 gd->bd->bi_dram[j].start = start_addr;
285 gd->bd->bi_dram[j].size = size;
286 }
287
288 return 0;
289}
290#endif
291
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800292int dram_init_banksize(void)
293{
Jonas Karlmandd4d16f2023-02-07 17:27:11 +0000294 size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
295 size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top));
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800296
297#ifdef CONFIG_ARM64
Quentin Schulz6ba06862024-04-25 12:46:24 +0200298 int ret = rockchip_dram_init_banksize();
299
300 if (!ret)
301 return ret;
302
303 debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n",
304 ret);
305
Heiko Stuebner0e6452b2025-04-15 23:51:14 +0200306 /* Reserve 2M for ATF bl31 */
307 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800308 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
Jonas Karlmandd4d16f2023-02-07 17:27:11 +0000309
310 /* Add usable memory beyond the blob of space for peripheral near 4GB */
311 if (ram_top > SZ_4G && top < SZ_4G) {
312 gd->bd->bi_dram[1].start = SZ_4G;
313 gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
Jonas Karlman83cb8462025-01-30 22:07:11 +0000314 } else if (ram_top > SZ_4G && top == SZ_4G) {
315 gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
Jonas Karlmandd4d16f2023-02-07 17:27:11 +0000316 }
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800317#else
Patrick Delaunaya7ca4802021-09-02 11:56:16 +0200318#ifdef CONFIG_SPL_OPTEE_IMAGE
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800319 struct tos_parameter_t *tos_parameter;
320
Tom Rinibb4dd962022-11-16 13:10:37 -0500321 tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE +
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800322 TRUST_PARAMETER_OFFSET);
323
324 if (tos_parameter->tee_mem.flags == 1) {
Tom Rinibb4dd962022-11-16 13:10:37 -0500325 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800326 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
Tom Rinibb4dd962022-11-16 13:10:37 -0500327 - CFG_SYS_SDRAM_BASE;
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800328 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
329 tos_parameter->tee_mem.size;
Alex Beee3a34942020-07-15 01:03:31 +0200330 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800331 } else {
Tom Rinibb4dd962022-11-16 13:10:37 -0500332 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800333 gd->bd->bi_dram[0].size = 0x8400000;
334 /* Reserve 32M for OPTEE with TA */
Tom Rinibb4dd962022-11-16 13:10:37 -0500335 gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800336 + gd->bd->bi_dram[0].size + 0x2000000;
Alex Beee3a34942020-07-15 01:03:31 +0200337 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800338 }
339#else
Tom Rinibb4dd962022-11-16 13:10:37 -0500340 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
Kever Yangdfc8a7d2019-07-22 20:02:02 +0800341 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
342#endif
343#endif
344
345 return 0;
346}
347
Kever Yang5db9e672017-06-23 16:11:05 +0800348size_t rockchip_sdram_size(phys_addr_t reg)
349{
Kever Yang117585a2019-11-15 11:04:35 +0800350 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
Kever Yang5db9e672017-06-23 16:11:05 +0800351 size_t chipsize_mb = 0;
352 size_t size_mb = 0;
353 u32 ch;
Kever Yang117585a2019-11-15 11:04:35 +0800354 u32 cs1_col = 0;
355 u32 bg = 0;
356 u32 dbw, dram_type;
Kever Yang4c0c6e42019-11-15 11:04:36 +0800357 u32 sys_reg2 = readl(reg);
Kever Yang117585a2019-11-15 11:04:35 +0800358 u32 sys_reg3 = readl(reg + 4);
Kever Yang4c0c6e42019-11-15 11:04:36 +0800359 u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
Kever Yang5db9e672017-06-23 16:11:05 +0800360 & SYS_REG_NUM_CH_MASK);
Jonas Karlmanf570c252023-02-07 17:27:10 +0000361 u32 version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) &
362 SYS_REG_VERSION_MASK;
Kever Yang5db9e672017-06-23 16:11:05 +0800363
Kever Yang4c0c6e42019-11-15 11:04:36 +0800364 dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
Jonas Karlmanf570c252023-02-07 17:27:10 +0000365 if (version >= 3)
366 dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
367 SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
Kever Yang4c0c6e42019-11-15 11:04:36 +0800368 debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
Jonas Karlmanf570c252023-02-07 17:27:10 +0000369 debug("%s %x %x\n", __func__, (u32)reg + 4, sys_reg3);
Kever Yang5db9e672017-06-23 16:11:05 +0800370 for (ch = 0; ch < ch_num; ch++) {
Kever Yang4c0c6e42019-11-15 11:04:36 +0800371 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
Kever Yang5db9e672017-06-23 16:11:05 +0800372 SYS_REG_RANK_MASK);
Kever Yang4c0c6e42019-11-15 11:04:36 +0800373 cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
Kever Yang117585a2019-11-15 11:04:35 +0800374 SYS_REG_COL_MASK);
375 cs1_col = cs0_col;
YouMin Chen618bddb2023-12-12 15:56:41 +0800376 if (dram_type == LPDDR5)
377 /* LPDDR5: 0:8bank(bk=3), 1:16bank(bk=4) */
378 bk = 3 + ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) &
379 SYS_REG_BK_MASK);
380 else
381 /* Other: 0:8bank(bk=3), 1:4bank(bk=2) */
382 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) &
383 SYS_REG_BK_MASK);
Jonas Karlmanf570c252023-02-07 17:27:10 +0000384 if (version >= 2) {
Kever Yang117585a2019-11-15 11:04:35 +0800385 cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
386 SYS_REG_CS1_COL_MASK);
387 if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
Kever Yang4c0c6e42019-11-15 11:04:36 +0800388 SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
Kever Yang117585a2019-11-15 11:04:35 +0800389 SYS_REG_CS0_ROW_SHIFT(ch) &
390 SYS_REG_CS0_ROW_MASK) == 7)
391 cs0_row = 12;
392 else
Kever Yang4c0c6e42019-11-15 11:04:36 +0800393 cs0_row = 13 + (sys_reg2 >>
Kever Yang117585a2019-11-15 11:04:35 +0800394 SYS_REG_CS0_ROW_SHIFT(ch) &
395 SYS_REG_CS0_ROW_MASK) +
396 ((sys_reg3 >>
397 SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
398 SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
399 if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
Kever Yang4c0c6e42019-11-15 11:04:36 +0800400 SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
Kever Yang117585a2019-11-15 11:04:35 +0800401 SYS_REG_CS1_ROW_SHIFT(ch) &
402 SYS_REG_CS1_ROW_MASK) == 7)
403 cs1_row = 12;
404 else
Kever Yang4c0c6e42019-11-15 11:04:36 +0800405 cs1_row = 13 + (sys_reg2 >>
Kever Yang117585a2019-11-15 11:04:35 +0800406 SYS_REG_CS1_ROW_SHIFT(ch) &
407 SYS_REG_CS1_ROW_MASK) +
408 ((sys_reg3 >>
409 SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
410 SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
411 } else {
Kever Yang4c0c6e42019-11-15 11:04:36 +0800412 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
Kever Yang5db9e672017-06-23 16:11:05 +0800413 SYS_REG_CS0_ROW_MASK);
Kever Yang4c0c6e42019-11-15 11:04:36 +0800414 cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
Kever Yang5db9e672017-06-23 16:11:05 +0800415 SYS_REG_CS1_ROW_MASK);
Kever Yang117585a2019-11-15 11:04:35 +0800416 }
Kever Yang4c0c6e42019-11-15 11:04:36 +0800417 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
Kever Yang5db9e672017-06-23 16:11:05 +0800418 SYS_REG_BW_MASK));
Kever Yang4c0c6e42019-11-15 11:04:36 +0800419 row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
Kever Yang5db9e672017-06-23 16:11:05 +0800420 SYS_REG_ROW_3_4_MASK;
Kever Yang117585a2019-11-15 11:04:35 +0800421 if (dram_type == DDR4) {
Kever Yang4c0c6e42019-11-15 11:04:36 +0800422 dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
Kever Yang117585a2019-11-15 11:04:35 +0800423 SYS_REG_DBW_MASK;
424 bg = (dbw == 2) ? 2 : 1;
425 }
426 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
Kever Yang5db9e672017-06-23 16:11:05 +0800427
428 if (rank > 1)
Kever Yang117585a2019-11-15 11:04:35 +0800429 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
430 (cs0_col - cs1_col));
Kever Yang5db9e672017-06-23 16:11:05 +0800431 if (row_3_4)
432 chipsize_mb = chipsize_mb * 3 / 4;
433 size_mb += chipsize_mb;
Kever Yang117585a2019-11-15 11:04:35 +0800434 if (rank > 1)
435 debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
436 cs1_row %d bw %d row_3_4 %d\n",
437 rank, cs0_col, cs1_col, bk, cs0_row,
438 cs1_row, bw, row_3_4);
439 else
440 debug("rank %d cs0_col %d bk %d cs0_row %d\
441 bw %d row_3_4 %d\n",
442 rank, cs0_col, bk, cs0_row,
443 bw, row_3_4);
Kever Yang5db9e672017-06-23 16:11:05 +0800444 }
445
Kever Yange10e9062018-12-28 09:56:48 +0800446 /*
447 * This is workaround for issue we can't get correct size for 4GB ram
448 * in 32bit system and available before we really need ram space
449 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
450 * The size of 4GB is '0x1 00000000', and this value will be truncated
451 * to 0 in 32bit system, and system can not get correct ram size.
452 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
453 * and we are now setting SDRAM_MAX_SIZE as max available space for
454 * ram in 4GB, so we can use this directly to workaround the issue.
455 * TODO:
456 * 1. update correct value for SDRAM_MAX_SIZE as what dram
457 * controller sees.
458 * 2. update board_get_usable_ram_top() and dram_init_banksize()
459 * to reserve memory for peripheral space after previous update.
460 */
Jonas Karlmandd4d16f2023-02-07 17:27:11 +0000461 if (!IS_ENABLED(CONFIG_ARM64) && size_mb > (SDRAM_MAX_SIZE >> 20))
Kever Yange10e9062018-12-28 09:56:48 +0800462 size_mb = (SDRAM_MAX_SIZE >> 20);
463
Kever Yang5db9e672017-06-23 16:11:05 +0800464 return (size_t)size_mb << 20;
465}
466
467int dram_init(void)
468{
469 struct ram_info ram;
470 struct udevice *dev;
471 int ret;
472
473 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
474 if (ret) {
475 debug("DRAM init failed: %d\n", ret);
476 return ret;
477 }
478 ret = ram_get_info(dev, &ram);
479 if (ret) {
480 debug("Cannot get DRAM size: %d\n", ret);
481 return ret;
482 }
Jonas Karlmanc7575e42025-01-30 22:07:13 +0000483 gd->ram_base = ram.base;
Kever Yang5db9e672017-06-23 16:11:05 +0800484 gd->ram_size = ram.size;
485 debug("SDRAM base=%lx, size=%lx\n",
486 (unsigned long)ram.base, (unsigned long)ram.size);
487
488 return 0;
489}
490
Heinrich Schuchardt51a9aac2023-08-12 20:16:58 +0200491phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
Kever Yang5db9e672017-06-23 16:11:05 +0800492{
Jonas Karlman4345e392025-01-30 22:07:12 +0000493 /* Make sure U-Boot only uses the space below the 4G address boundary */
494 u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G);
Kever Yang5db9e672017-06-23 16:11:05 +0800495
496 return (gd->ram_top > top) ? top : gd->ram_top;
497}