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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / include / asm / arch-rockchip / cru_rk3576.h
blob: c51750beff28ae08126e92d4c96bf06fac858e50 [file] [log] [blame]
Elaine Zhang7f7e3232025-04-15 23:51:18 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 */
6
7#ifndef _ASM_ARCH_CRU_RK3576_H
8#define _ASM_ARCH_CRU_RK3576_H
9
10#define MHz 1000000
11#define KHz 1000
12#define OSC_HZ (24 * MHz)
13
14#define CPU_PVTPLL_HZ (1008 * MHz)
15#define LPLL_HZ (816 * MHz)
16#define GPLL_HZ (1188 * MHz)
17#define CPLL_HZ (1000 * MHz)
18#define PPLL_HZ (1100 * MHz)
19#define GMAC0_PTP_REFCLK_IN (24 * MHz)
20#define GMAC1_PTP_REFCLK_IN (24 * MHz)
21
22/* RK3576 pll id */
23enum rk3576_pll_id {
24 BPLL,
25 LPLL,
26 DPLL,
27 CPLL,
28 GPLL,
29 VPLL,
30 AUPLL,
31 SPLL,
32 PPLL,
33 PLL_COUNT,
34};
35
36struct rk3576_clk_priv {
37 struct rk3576_cru *cru;
38 ulong ppll_hz;
39 ulong gpll_hz;
40 ulong cpll_hz;
41 ulong vpll_hz;
42 ulong aupll_hz;
43 ulong spll_hz;
44 ulong lpll_hz;
45 ulong bpll_hz;
46 ulong armclk_hz;
47 ulong armclk_enter_hz;
48 ulong armclk_init_hz;
49 bool sync_kernel;
50 bool set_armclk_rate;
51};
52
53struct rk3576_pll {
54 unsigned int con0;
55 unsigned int con1;
56 unsigned int con2;
57 unsigned int con3;
58 unsigned int con4;
59 unsigned int reserved0[3];
60};
61
62struct rk3576_cru {
63 struct rk3576_pll pll[18];
64 unsigned int reserved0[16];/* Address Offset: 0x0240 */
65 unsigned int mode_con00;/* Address Offset: 0x0280 */
66 unsigned int reserved1[31];/* Address Offset: 0x0284 */
67 unsigned int clksel_con[181]; /* Address Offset: 0x0300 */
68 unsigned int reserved2[139];/* Address Offset: 0x05d4 */
69 unsigned int clkgate_con[80];/* Address Offset: 0x0800 */
70 unsigned int reserved3[48];/* Address Offset: 0x0938 */
71 unsigned int softrst_con[80];/* Address Offset: 0x0400 */
72 unsigned int reserved4[48];/* Address Offset: 0x0b38 */
73 unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */
74 unsigned int glb_rst_st;/* Address Offset: 0x0c04 */
75 unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */
76 unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */
77 unsigned int glb_rst_con;/* Address Offset: 0x0c10 */
78 unsigned int reserved5[43];/* Address Offset: 0x0c14 */
79 unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */
80 unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */
81 unsigned int reserved8[32137];/* Address Offset: 0x0c38 */
82 unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */
83 unsigned int reserved9[298];/* Address Offset: 0x20358 */
84 unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */
85 unsigned int reserved10[32440];/* Address Offset: 0x20820 */
86 unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */
87};
88
89check_member(rk3576_cru, mode_con00, 0x280);
90check_member(rk3576_cru, pmuclksel_con[1], 0x20304);
91
92struct pll_rate_table {
93 unsigned long rate;
94 unsigned int m;
95 unsigned int p;
96 unsigned int s;
97 unsigned int k;
98};
99
100#define RK3576_PHP_CRU_BASE 0x8000
101#define RK3576_PMU_CRU_BASE 0x20000
102#define RK3576_BIGCORE_CRU_BASE 0x38000
103#define RK3576_LITCORE_CRU_BASE 0x40000
104#define RK3576_CCI_CRU_BASE 0x48000
105#define RK3576_CRU_BASE 0x27200000
106#define RK3576_SCRU_BASE 0x27214000
107
108#define RK3576_BIGCORE_GRF_BASE 0x2600C000
109#define RK3576_LITCORE_GRF_BASE 0x2600E000
110#define RK3576_CCI_GRF_BASE 0x26010000
111
112#define RK3576_PLL_CON(x) ((x) * 0x4)
113#define RK3576_MODE_CON0 0x280
114#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
115#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
116#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
117#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
118#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
119#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
120#define RK3576_GLB_CNT_TH 0xc00
121#define RK3576_GLB_SRST_FST 0xc08
122#define RK3576_GLB_SRST_SND 0xc0c
123#define RK3576_GLB_RST_CON 0xc10
124#define RK3576_GLB_RST_ST 0xc04
125#define RK3576_SDIO_CON0 0xC24
126#define RK3576_SDIO_CON1 0xC28
127#define RK3576_SDMMC_CON0 0xC30
128#define RK3576_SDMMC_CON1 0xC34
129
130#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
131#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
132#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
133
134#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
135#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
136#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
137#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
138
139#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
140#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
141#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
142
143#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
144#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
145#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
146#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
147#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
148#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
149#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
150#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
151
152enum {
153 /* CRU_CLK_SEL8_CON */
154 PCLK_TOP_SEL_SHIFT = 7,
155 PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT,
156 PCLK_TOP_SEL_100M = 0,
157 PCLK_TOP_SEL_50M,
158 PCLK_TOP_SEL_OSC,
159
160 /* CRU_CLK_SEL9_CON */
161 ACLK_TOP_SEL_SHIFT = 5,
162 ACLK_TOP_SEL_MASK = 3 << ACLK_TOP_SEL_SHIFT,
163 ACLK_TOP_SEL_GPLL = 0,
164 ACLK_TOP_SEL_CPLL,
165 ACLK_TOP_SEL_AUPLL,
166 ACLK_TOP_DIV_SHIFT = 0,
167 ACLK_TOP_DIV_MASK = 0x1f << ACLK_TOP_DIV_SHIFT,
168
169 /* CRU_CLK_SEL10_CON */
170 ACLK_TOP_MID_SEL_SHIFT = 5,
171 ACLK_TOP_MID_SEL_MASK = 1 << ACLK_TOP_MID_SEL_SHIFT,
172 ACLK_TOP_MID_SEL_GPLL = 0,
173 ACLK_TOP_MID_SEL_CPLL,
174 ACLK_TOP_MID_DIV_SHIFT = 0,
175 ACLK_TOP_MID_DIV_MASK = 0x1f << ACLK_TOP_MID_DIV_SHIFT,
176
177 /* CRU_CLK_SEL19_CON */
178 HCLK_TOP_SEL_SHIFT = 2,
179 HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT,
180 HCLK_TOP_SEL_200M = 0,
181 HCLK_TOP_SEL_100M,
182 HCLK_TOP_SEL_50M,
183 HCLK_TOP_SEL_OSC,
184
185 /* CRU_CLK_SEL25_CON */
186 CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
187 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
188 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
189 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
190
191 /* CRU_CLK_SEL26_CON */
192 CLK_UART_SRC_SEL_SHIFT = 0,
193 CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT,
194 CLK_UART_SRC_SEL_GPLL = 0,
195 CLK_UART_SRC_SEL_CPLL,
196 CLK_UART_SRC_SEL_AUPLL,
197 CLK_UART_SRC_SEL_OSC,
198
199 /* CRU_CLK_SEL27_CON */
200 CLK_UART1_SRC_SEL_SHIFT = 13,
201 CLK_UART1_SRC_SEL_MASK = 0x7 << CLK_UART1_SRC_SEL_SHIFT,
202 CLK_UART1_SRC_DIV_SHIFT = 5,
203 CLK_UART1_SRC_DIV_MASK = 0xff << CLK_UART1_SRC_DIV_SHIFT,
204
205 /* CRU_CLK_SEL30_CON */
206 CLK_GMAC0_125M_DIV_SHIFT = 10,
207 CLK_GMAC0_125M_DIV_MASK = 0x1f << CLK_GMAC0_125M_DIV_SHIFT,
208
209 /* CRU_CLK_SEL31_CON */
210 CLK_GMAC1_125M_DIV_SHIFT = 0,
211 CLK_GMAC1_125M_DIV_MASK = 0x1f << CLK_GMAC1_125M_DIV_SHIFT,
212
213 /* CRU_CLK_SEL33_CON */
214 REF_CLK0_OUT_PLL_SEL_SHIFT = 8,
215 REF_CLK0_OUT_PLL_SEL_MASK = 7 << REF_CLK0_OUT_PLL_SEL_SHIFT,
216 REF_CLK0_OUT_PLL_SEL_GPLL = 0,
217 REF_CLK0_OUT_PLL_SEL_CPLL,
218 REF_CLK0_OUT_PLL_SEL_SPLL,
219 REF_CLK0_OUT_PLL_SEL_AUPLL,
220 REF_CLK0_OUT_PLL_SEL_LPLL,
221 REF_CLK0_OUT_PLL_SEL_OSC,
222 REF_CLK0_OUT_PLL_DIV_SHIFT = 0,
223 REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT,
224
225 /* CRU_CLK_SEL55_CON */
226 ACLK_BUS_ROOT_SEL_SHIFT = 9,
227 ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT,
228 ACLK_BUS_ROOT_SEL_GPLL = 0,
229 ACLK_BUS_ROOT_SEL_CPLL,
230 ACLK_BUS_ROOT_DIV_SHIFT = 4,
231 ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT,
232 PCLK_BUS_ROOT_SEL_SHIFT = 2,
233 PCLK_BUS_ROOT_SEL_MASK = 3 << PCLK_BUS_ROOT_SEL_SHIFT,
234 PCLK_BUS_ROOT_SEL_100M = 0,
235 PCLK_BUS_ROOT_SEL_50M,
236 PCLK_BUS_ROOT_SEL_OSC,
237 HCLK_BUS_ROOT_SEL_SHIFT = 0,
238 HCLK_BUS_ROOT_SEL_MASK = 3 << HCLK_BUS_ROOT_SEL_SHIFT,
239 HCLK_BUS_ROOT_SEL_200M = 0,
240 HCLK_BUS_ROOT_SEL_100M,
241 HCLK_BUS_ROOT_SEL_50M,
242 HCLK_BUS_ROOT_SEL_OSC,
243
244 /* CRU_CLK_SEL57_CON */
245 CLK_I2C8_SEL_SHIFT = 14,
246 CLK_I2C8_SEL_MASK = 3 << CLK_I2C8_SEL_SHIFT,
247 CLK_I2C7_SEL_SHIFT = 12,
248 CLK_I2C7_SEL_MASK = 3 << CLK_I2C7_SEL_SHIFT,
249 CLK_I2C6_SEL_SHIFT = 10,
250 CLK_I2C6_SEL_MASK = 3 << CLK_I2C6_SEL_SHIFT,
251 CLK_I2C5_SEL_SHIFT = 8,
252 CLK_I2C5_SEL_MASK = 3 << CLK_I2C5_SEL_SHIFT,
253 CLK_I2C4_SEL_SHIFT = 6,
254 CLK_I2C4_SEL_MASK = 3 << CLK_I2C4_SEL_SHIFT,
255 CLK_I2C3_SEL_SHIFT = 4,
256 CLK_I2C3_SEL_MASK = 3 << CLK_I2C3_SEL_SHIFT,
257 CLK_I2C2_SEL_SHIFT = 2,
258 CLK_I2C2_SEL_MASK = 3 << CLK_I2C2_SEL_SHIFT,
259 CLK_I2C1_SEL_SHIFT = 0,
260 CLK_I2C1_SEL_MASK = 3 << CLK_I2C1_SEL_SHIFT,
261 CLK_I2C_SEL_200M = 0,
262 CLK_I2C_SEL_100M,
263 CLK_I2C_SEL_50M,
264 CLK_I2C_SEL_OSC,
265
266 /* CRU_CLK_SEL58_CON */
267 CLK_SARADC_SEL_SHIFT = 12,
268 CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT,
269 CLK_SARADC_SEL_GPLL = 0,
270 CLK_SARADC_SEL_OSC,
271 CLK_SARADC_DIV_SHIFT = 4,
272 CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT,
273 CLK_I2C9_SEL_SHIFT = 0,
274 CLK_I2C9_SEL_MASK = 3 << CLK_I2C9_SEL_SHIFT,
275
276 /* CRU_CLK_SEL59_CON */
277 CLK_TSADC_DIV_SHIFT = 0,
278 CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT,
279
280 /* CRU_CLK_SEL60_CON */
281 CLK_UART_SEL_SHIFT = 8,
282 CLK_UART_SEL_MASK = 7 << CLK_UART_SEL_SHIFT,
283 CLK_UART_SEL_GPLL = 0,
284 CLK_UART_SEL_CPLL,
285 CLK_UART_SEL_AUPLL,
286 CLK_UART_SEL_OSC,
287 CLK_UART_SEL_FRAC0,
288 CLK_UART_SEL_FRAC1,
289 CLK_UART_SEL_FRAC2,
290 CLK_UART_DIV_SHIFT = 0,
291 CLK_UART_DIV_MASK = 0xff << CLK_UART_DIV_SHIFT,
292
293 /* CRU_CLK_SEL70_CON */
294 CLK_SPI0_SEL_SHIFT = 13,
295 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
296 CLK_SPI_SEL_200M = 0,
297 CLK_SPI_SEL_100M,
298 CLK_SPI_SEL_50M,
299 CLK_SPI_SEL_OSC,
300
301 /* CRU_CLK_SEL71_CON */
302 CLK_PWM1_SEL_SHIFT = 8,
303 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
304 CLK_SPI4_SEL_SHIFT = 6,
305 CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT,
306 CLK_SPI3_SEL_SHIFT = 4,
307 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
308 CLK_SPI2_SEL_SHIFT = 2,
309 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
310 CLK_SPI1_SEL_SHIFT = 0,
311 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
312 CLK_PWM_SEL_100M = 0,
313 CLK_PWM_SEL_50M,
314 CLK_PWM_SEL_OSC,
315
316 /* CRU_CLK_SEL72_CON */
317 DCLK_DECOM_SEL_SHIFT = 5,
318 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT,
319 DCLK_DECOM_SEL_GPLL = 0,
320 DCLK_DECOM_SEL_SPLL,
321 DCLK_DECOM_DIV_SHIFT = 0,
322 DCLK_DECOM_DIV_MASK = 0x1f << DCLK_DECOM_DIV_SHIFT,
323
324 /* CRU_CLK_SEL74_CON */
325 CLK_PWM2_SEL_SHIFT = 6,
326 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
327
328 /* CRU_CLK_SEL89_CON */
329 CCLK_EMMC_SEL_SHIFT = 14,
330 CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT,
331 CCLK_EMMC_SEL_GPLL = 0,
332 CCLK_EMMC_SEL_CPLL,
333 CCLK_EMMC_SEL_OSC,
334 CCLK_EMMC_DIV_SHIFT = 8,
335 CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT,
336 SCLK_FSPI_SEL_SHIFT = 6,
337 SCLK_FSPI_SEL_MASK = 3 << SCLK_FSPI_SEL_SHIFT,
338 SCLK_FSPI_SEL_GPLL = 0,
339 SCLK_FSPI_SEL_CPLL,
340 SCLK_FSPI_SEL_OSC,
341 SCLK_FSPI_DIV_SHIFT = 0,
342 SCLK_FSPI_DIV_MASK = 0x3f << SCLK_FSPI_DIV_SHIFT,
343
344 /* CRU_CLK_SEL90_CON */
345 BCLK_EMMC_SEL_SHIFT = 0,
346 BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT,
347 BCLK_EMMC_SEL_200M = 0,
348 BCLK_EMMC_SEL_100M,
349 BCLK_EMMC_SEL_50M,
350 BCLK_EMMC_SEL_OSC,
351
352 /* CRU_CLK_SEL104_CON */
353 CLK_GMAC1_PTP_SEL_SHIFT = 13,
354 CLK_GMAC1_PTP_SEL_MASK = 3 << CLK_GMAC1_PTP_SEL_SHIFT,
355 CLK_GMAC1_PTP_SEL_GPLL = 0,
356 CLK_GMAC1_PTP_SEL_CPLL,
357 CLK_GMAC1_PTP_SEL_REFIN,
358 CLK_GMAC1_PTP_DIV_SHIFT = 8,
359 CLK_GMAC1_PTP_DIV_MASK = 0x1f << CLK_GMAC1_PTP_DIV_SHIFT,
360 CCLK_SDIO_SRC_SEL_SHIFT = 6,
361 CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT,
362 CCLK_SDIO_SRC_SEL_GPLL = 0,
363 CCLK_SDIO_SRC_SEL_CPLL,
364 CCLK_SDIO_SRC_SEL_OSC,
365 CCLK_SDIO_SRC_DIV_SHIFT = 0,
366 CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT,
367
368 /* CRU_CLK_SEL105_CON */
369 CCLK_SDMMC0_SRC_SEL_SHIFT = 13,
370 CCLK_SDMMC0_SRC_SEL_MASK = 3 << CCLK_SDMMC0_SRC_SEL_SHIFT,
371 CCLK_SDMMC0_SRC_SEL_GPLL = 0,
372 CCLK_SDMMC0_SRC_SEL_CPLL,
373 CCLK_SDMMC0_SRC_SEL_OSC,
374 CCLK_SDMMC0_SRC_DIV_SHIFT = 7,
375 CCLK_SDMMC0_SRC_DIV_MASK = 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT,
376 CLK_GMAC0_PTP_SEL_SHIFT = 5,
377 CLK_GMAC0_PTP_SEL_MASK = 3 << CLK_GMAC0_PTP_SEL_SHIFT,
378 CLK_GMAC0_PTP_SEL_GPLL = 0,
379 CLK_GMAC0_PTP_SEL_CPLL,
380 CLK_GMAC0_PTP_SEL_REFIN,
381 CLK_GMAC0_PTP_DIV_SHIFT = 0,
382 CLK_GMAC0_PTP_DIV_MASK = 0x1f << CLK_GMAC0_PTP_DIV_SHIFT,
383
384 /* CRU_CLK_SEL123_CON */
385 DCLK_EBC_SEL_SHIFT = 12,
386 DCLK_EBC_SEL_MASK = 7 << DCLK_EBC_SEL_SHIFT,
387 DCLK_EBC_SEL_GPLL = 0,
388 DCLK_EBC_SEL_CPLL,
389 DCLK_EBC_SEL_VPLL,
390 DCLK_EBC_SEL_AUPLL,
391 DCLK_EBC_SEL_LPLL,
392 DCLK_EBC_SEL_FRAC_SRC,
393 DCLK_EBC_SEL_OSC,
394 DCLK_EBC_DIV_SHIFT = 3,
395 DCLK_EBC_DIV_MASK = 0x1ff << DCLK_EBC_DIV_SHIFT,
396 DCLK_EBC_FRAC_SRC_SEL_SHIFT = 0,
397 DCLK_EBC_FRAC_SRC_SEL_MASK = 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT,
398 DCLK_EBC_FRAC_SRC_SEL_GPLL = 0,
399 DCLK_EBC_FRAC_SRC_SEL_CPLL,
400 DCLK_EBC_FRAC_SRC_SEL_VPLL,
401 DCLK_EBC_FRAC_SRC_SEL_AUPLL,
402 DCLK_EBC_FRAC_SRC_SEL_OSC,
403
404 /* CRU_CLK_SEL144_CON */
405 PCLK_VOP_ROOT_SEL_SHIFT = 12,
406 PCLK_VOP_ROOT_SEL_MASK = 3 << PCLK_VOP_ROOT_SEL_SHIFT,
407 PCLK_VOP_ROOT_SEL_100M = 0,
408 PCLK_VOP_ROOT_SEL_50M,
409 PCLK_VOP_ROOT_SEL_OSC,
410 HCLK_VOP_ROOT_SEL_SHIFT = 10,
411 HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT,
412 HCLK_VOP_ROOT_SEL_200M = 0,
413 HCLK_VOP_ROOT_SEL_100M,
414 HCLK_VOP_ROOT_SEL_50M,
415 HCLK_VOP_ROOT_SEL_OSC,
416 ACLK_VOP_ROOT_SEL_SHIFT = 5,
417 ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT,
418 ACLK_VOP_ROOT_SEL_GPLL = 0,
419 ACLK_VOP_ROOT_SEL_CPLL,
420 ACLK_VOP_ROOT_SEL_AUPLL,
421 ACLK_VOP_ROOT_SEL_SPLL,
422 ACLK_VOP_ROOT_SEL_LPLL,
423 ACLK_VOP_ROOT_DIV_SHIFT = 0,
424 ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT,
425
426 /* CRU_CLK_SEL145_CON */
427 DCLK0_VOP_SRC_SEL_SHIFT = 8,
428 DCLK0_VOP_SRC_SEL_MASK = 7 << DCLK0_VOP_SRC_SEL_SHIFT,
429 DCLK_VOP_SRC_SEL_GPLL = 0,
430 DCLK_VOP_SRC_SEL_CPLL,
431 DCLK_VOP_SRC_SEL_VPLL,
432 DCLK_VOP_SRC_SEL_BPLL,
433 DCLK_VOP_SRC_SEL_LPLL,
434 DCLK0_VOP_SRC_DIV_SHIFT = 0,
435 DCLK0_VOP_SRC_DIV_MASK = 0xff << DCLK0_VOP_SRC_DIV_SHIFT,
436
437 /* CRU_CLK_SEL147_CON */
438 DCLK2_VOP_SEL_SHIFT = 13,
439 DCLK2_VOP_SEL_MASK = 1 << DCLK2_VOP_SEL_SHIFT,
440 DCLK1_VOP_SEL_SHIFT = 12,
441 DCLK1_VOP_SEL_MASK = 1 << DCLK1_VOP_SEL_SHIFT,
442 DCLK0_VOP_SEL_SHIFT = 11,
443 DCLK0_VOP_SEL_MASK = 1 << DCLK0_VOP_SEL_SHIFT,
444
445 /* CRU_CLK_SEL149_CON */
446 ACLK_VO0_ROOT_SEL_SHIFT = 5,
447 ACLK_VO0_ROOT_SEL_MASK = 3 << ACLK_VO0_ROOT_SEL_SHIFT,
448 ACLK_VO0_ROOT_SEL_GPLL = 0,
449 ACLK_VO0_ROOT_SEL_CPLL,
450 ACLK_VO0_ROOT_SEL_LPLL,
451 ACLK_VO0_ROOT_SEL_BPLL,
452 ACLK_VO0_ROOT_DIV_SHIFT = 0,
453 ACLK_VO0_ROOT_DIV_MASK = 0x1f << ACLK_VO0_ROOT_DIV_SHIFT,
454
455 /* CRU_CLK_SEL151_CON */
456 CLK_DSIHOST0_SEL_SHIFT = 7,
457 CLK_DSIHOST0_SEL_MASK = 7 << CLK_DSIHOST0_SEL_SHIFT,
458 CLK_DSIHOST0_SEL_GPLL = 0,
459 CLK_DSIHOST0_SEL_CPLL,
460 CLK_DSIHOST0_SEL_SPLL,
461 CLK_DSIHOST0_SEL_VPLL,
462 CLK_DSIHOST0_SEL_BPLL,
463 CLK_DSIHOST0_SEL_LPLL,
464 CLK_DSIHOST0_DIV_SHIFT = 0,
465 CLK_DSIHOST0_DIV_MASK = 0x7f << CLK_DSIHOST0_DIV_SHIFT,
466
467 /* PMUCRU_CLK_SEL5_CON */
468 CLK_PMU1PWM_SEL_SHIFT = 2,
469 CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT,
470
471 /* PMUCRU_CLK_SEL6_CON */
472 CLK_I2C0_SEL_SHIFT = 7,
473 CLK_I2C0_SEL_MASK = 3 << CLK_I2C0_SEL_SHIFT,
474
475 /* PMUCRU_CLK_SEL8_CON */
476 CLK_UART1_SEL_SHIFT = 0,
477 CLK_UART1_SEL_MASK = 1 << CLK_UART1_SEL_SHIFT,
478 CLK_UART1_SEL_TOP = 0,
479 CLK_UART1_SEL_OSC,
480
481 /* LITCRU_CLK_SEL0_CON */
482 CLK_LITCORE_SEL_SHIFT = 12,
483 CLK_LITCORE_SEL_MASK = 3 << CLK_LITCORE_SEL_SHIFT,
484 CLK_LITCORE_SEL_LPLL = 0,
485 CLK_LITCORE_SEL_GPLL,
486 CLK_LITCORE_SEL_PVTPLL,
487 CLK_LITCORE_DIV_SHIFT = 7,
488 CLK_LITCORE_DIV_MASK = 0x1f << CLK_LITCORE_DIV_SHIFT,
489
490};
491#endif