Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / include / asm / arch-rockchip / cru_rk3528.h
blob: b4020958a04645b7653e289278646cd2b2ff8c4b [file] [log] [blame]
Joseph Chen72c11232025-04-07 22:46:49 +0000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 * Author: Joseph Chen <chenjh@rock-chips.com>
5 */
6
7#ifndef _ASM_ARCH_CRU_RK3528_H
8#define _ASM_ARCH_CRU_RK3528_H
9
10#define MHz 1000000
11#define KHz 1000
12#define OSC_HZ (24 * MHz)
13
14#define CPU_PVTPLL_HZ (1200 * MHz)
15#define APLL_HZ (600 * MHz)
16#define GPLL_HZ (1188 * MHz)
17#define CPLL_HZ (996 * MHz)
18#define PPLL_HZ (1000 * MHz)
19
20/* RK3528 pll id */
21enum rk3528_pll_id {
22 APLL,
23 CPLL,
24 GPLL,
25 PPLL,
26 DPLL,
27 PLL_COUNT,
28};
29
30struct rk3528_clk_priv {
31 struct rk3528_cru *cru;
32 unsigned long ppll_hz;
33 unsigned long gpll_hz;
34 unsigned long cpll_hz;
35 unsigned long armclk_hz;
36 unsigned long armclk_enter_hz;
37 unsigned long armclk_init_hz;
38 bool sync_kernel;
39};
40
41struct rk3528_pll {
42 unsigned int con0;
43 unsigned int con1;
44 unsigned int con2;
45 unsigned int con3;
46 unsigned int con4;
47 unsigned int reserved0[3];
48};
49
50#define RK3528_CRU_BASE ((struct rk3528_cru *)0xff4a0000)
51
52struct rk3528_cru {
53 unsigned int apll_con[5];
54 unsigned int reserved0014[3];
55 unsigned int cpll_con[5];
56 unsigned int reserved0034[11];
57 unsigned int gpll_con[5];
58 unsigned int reserved0074[51 + 32];
59 unsigned int reserved01c0[48];
60 unsigned int mode_con[1];
61 unsigned int reserved0284[31];
62 unsigned int clksel_con[91];
63 unsigned int reserved046c[229];
64 unsigned int gate_con[46];
65 unsigned int reserved08b8[82];
66 unsigned int softrst_con[47];
67 unsigned int reserved0abc[81];
68 unsigned int glb_cnt_th;
69 unsigned int glb_rst_st;
70 unsigned int glb_srst_fst;
71 unsigned int glb_srst_snd;
72 unsigned int glb_rst_con;
73 unsigned int reserved0c14[6];
74 unsigned int corewfi_con;
75 unsigned int reserved0c30[15604];
76
77 /* pmucru */
78 unsigned int reserved10000[192];
79 unsigned int pmuclksel_con[3];
80 unsigned int reserved1030c[317];
81 unsigned int pmugate_con[3];
82 unsigned int reserved1080c[125];
83 unsigned int pmusoftrst_con[3];
84 unsigned int reserved10a08[7550 + 8191];
85
86 /* pciecru */
87 unsigned int reserved20000[32];
88 unsigned int ppll_con[5];
89 unsigned int reserved20094[155];
90 unsigned int pcieclksel_con[2];
91 unsigned int reserved20308[318];
92 unsigned int pciegate_con;
93};
94
95check_member(rk3528_cru, pciegate_con, 0x20800);
96
97struct pll_rate_table {
98 unsigned long rate;
99 unsigned int fbdiv;
100 unsigned int postdiv1;
101 unsigned int refdiv;
102 unsigned int postdiv2;
103 unsigned int dsmpd;
104 unsigned int frac;
105};
106
107#define RK3528_PMU_CRU_BASE 0x10000
108#define RK3528_PCIE_CRU_BASE 0x20000
109#define RK3528_DDRPHY_CRU_BASE 0x28000
110#define RK3528_PLL_CON(x) ((x) * 0x4)
111#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
112#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
113#define RK3528_MODE_CON 0x280
114#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
115#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
116#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
117#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
118
119#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
120#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT)
121#define RK3528_DIV_PCLK_DBG_SHIFT 1
122#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT)
123
124enum {
125 /* CRU_CLKSEL_CON00 */
126 CLK_MATRIX_50M_SRC_DIV_SHIFT = 2,
127 CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
128 CLK_MATRIX_100M_SRC_DIV_SHIFT = 7,
129 CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
130
131 /* CRU_CLKSEL_CON01 */
132 CLK_MATRIX_150M_SRC_DIV_SHIFT = 0,
133 CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
134 CLK_MATRIX_200M_SRC_DIV_SHIFT = 5,
135 CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
136 CLK_MATRIX_250M_SRC_DIV_SHIFT = 10,
137 CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
138 CLK_MATRIX_250M_SRC_SEL_SHIFT = 15,
139 CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
140
141 /* CRU_CLKSEL_CON02 */
142 CLK_MATRIX_300M_SRC_DIV_SHIFT = 0,
143 CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
144 CLK_MATRIX_339M_SRC_DIV_SHIFT = 5,
145 CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
146 CLK_MATRIX_400M_SRC_DIV_SHIFT = 10,
147 CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
148
149 /* CRU_CLKSEL_CON03 */
150 CLK_MATRIX_500M_SRC_DIV_SHIFT = 6,
151 CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
152 CLK_MATRIX_500M_SRC_SEL_SHIFT = 11,
153 CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
154
155 /* CRU_CLKSEL_CON04 */
156 CLK_MATRIX_600M_SRC_DIV_SHIFT = 0,
157 CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
158 CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U,
159 CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U,
160 CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U,
161 CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U,
162
163 /* PMUCRU_CLKSEL_CON00 */
164 CLK_I2C2_SEL_SHIFT = 0,
165 CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
166
167 /* PCIE_CRU_CLKSEL_CON01 */
168 PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7,
169 PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
170 PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11,
171 PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
172
173 /* CRU_CLKSEL_CON32 */
174 DCLK_VOP_SRC0_SEL_SHIFT = 10,
175 DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
176 DCLK_VOP_SRC0_DIV_SHIFT = 2,
177 DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
178
179 /* CRU_CLKSEL_CON33 */
180 DCLK_VOP_SRC1_SEL_SHIFT = 8,
181 DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
182 DCLK_VOP_SRC1_DIV_SHIFT = 0,
183 DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
184
185 /* CRU_CLKSEL_CON43 */
186 CLK_CORE_CRYPTO_SEL_SHIFT = 14,
187 CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
188 ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U,
189 ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
190
191 /* CRU_CLKSEL_CON44 */
192 CLK_PWM0_SEL_SHIFT = 6,
193 CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
194 CLK_PWM1_SEL_SHIFT = 8,
195 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
196 CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U,
197 CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U,
198 CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U,
199 CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U,
200 CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U,
201 CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U,
202 CLK_PKA_CRYPTO_SEL_SHIFT = 0,
203 CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
204 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
205 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
206 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
207 CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
208 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
209 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
210 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
211 CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
212
213 /* CRU_CLKSEL_CON60 */
214 CLK_MATRIX_25M_SRC_DIV_SHIFT = 2,
215 CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
216 CLK_MATRIX_125M_SRC_DIV_SHIFT = 10,
217 CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
218
219 /* CRU_CLKSEL_CON61 */
220 SCLK_SFC_DIV_SHIFT = 6,
221 SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT,
222 SCLK_SFC_SEL_SHIFT = 12,
223 SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
224 SCLK_SFC_SEL_CLK_GPLL_MUX = 0U,
225 SCLK_SFC_SEL_CLK_CPLL_MUX = 1U,
226 SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U,
227
228 /* CRU_CLKSEL_CON62 */
229 CCLK_SRC_EMMC_DIV_SHIFT = 0,
230 CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
231 CCLK_SRC_EMMC_SEL_SHIFT = 6,
232 CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
233 BCLK_EMMC_SEL_SHIFT = 8,
234 BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT,
235
236 /* CRU_CLKSEL_CON63 */
237 CLK_I2C3_SEL_SHIFT = 12,
238 CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
239 CLK_I2C5_SEL_SHIFT = 14,
240 CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT,
241 CLK_SPI1_SEL_SHIFT = 10,
242 CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
243
244 /* CRU_CLKSEL_CON64 */
245 CLK_I2C6_SEL_SHIFT = 0,
246 CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT,
247
248 /* CRU_CLKSEL_CON74 */
249 CLK_SARADC_DIV_SHIFT = 0,
250 CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
251 CLK_TSADC_DIV_SHIFT = 3,
252 CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
253 CLK_TSADC_TSEN_DIV_SHIFT = 8,
254 CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
255
256 /* CRU_CLKSEL_CON79 */
257 CLK_I2C1_SEL_SHIFT = 9,
258 CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
259 CLK_I2C0_SEL_SHIFT = 11,
260 CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
261 CLK_SPI0_SEL_SHIFT = 13,
262 CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
263
264 /* CRU_CLKSEL_CON83 */
265 ACLK_VOP_ROOT_DIV_SHIFT = 12,
266 ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
267 ACLK_VOP_ROOT_SEL_SHIFT = 15,
268 ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
269
270 /* CRU_CLKSEL_CON84 */
271 DCLK_VOP0_SEL_SHIFT = 0,
272 DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT,
273 DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U,
274 DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U,
275 ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U,
276 ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U,
277 DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U,
278 DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U,
279
280 /* CRU_CLKSEL_CON85 */
281 CLK_I2C4_SEL_SHIFT = 13,
282 CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
283 CLK_I2C7_SEL_SHIFT = 0,
284 CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT,
285 CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U,
286 CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U,
287 CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U,
288 CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U,
289 CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U,
290 CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U,
291 CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U,
292 CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U,
293 CCLK_SRC_SDMMC0_DIV_SHIFT = 0,
294 CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
295 CCLK_SRC_SDMMC0_SEL_SHIFT = 6,
296 CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
297 CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U,
298 CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U,
299 CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U,
300 BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U,
301 BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U,
302 BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U,
303 BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U,
304 CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U,
305 CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U,
306 CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U,
307
308 /* CRU_CLKSEL_CON04 */
309 CLK_UART0_SRC_DIV_SHIFT = 5,
310 CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT,
311 /* CRU_CLKSEL_CON05 */
312 CLK_UART0_FRAC_DIV_SHIFT = 0,
313 CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
314 /* CRU_CLKSEL_CON06 */
315 SCLK_UART0_SRC_SEL_SHIFT = 0,
316 SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
317 CLK_UART1_SRC_DIV_SHIFT = 2,
318 CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT,
319 /* CRU_CLKSEL_CON07 */
320 CLK_UART1_FRAC_DIV_SHIFT = 0,
321 CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
322 /* CRU_CLKSEL_CON08 */
323 SCLK_UART1_SRC_SEL_SHIFT = 0,
324 SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
325 CLK_UART2_SRC_DIV_SHIFT = 2,
326 CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT,
327 /* CRU_CLKSEL_CON09 */
328 CLK_UART2_FRAC_DIV_SHIFT = 0,
329 CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
330 /* CRU_CLKSEL_CON10 */
331 SCLK_UART2_SRC_SEL_SHIFT = 0,
332 SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
333 CLK_UART3_SRC_DIV_SHIFT = 2,
334 CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT,
335 /* CRU_CLKSEL_CON11 */
336 CLK_UART3_FRAC_DIV_SHIFT = 0,
337 CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
338 /* CRU_CLKSEL_CON12 */
339 SCLK_UART3_SRC_SEL_SHIFT = 0,
340 SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
341 CLK_UART4_SRC_DIV_SHIFT = 2,
342 CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT,
343 /* CRU_CLKSEL_CON13 */
344 CLK_UART4_FRAC_DIV_SHIFT = 0,
345 CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
346 /* CRU_CLKSEL_CON14 */
347 SCLK_UART4_SRC_SEL_SHIFT = 0,
348 SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
349 CLK_UART5_SRC_DIV_SHIFT = 2,
350 CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT,
351 /* CRU_CLKSEL_CON15 */
352 CLK_UART5_FRAC_DIV_SHIFT = 0,
353 CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
354 /* CRU_CLKSEL_CON16 */
355 SCLK_UART5_SRC_SEL_SHIFT = 0,
356 SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
357 CLK_UART6_SRC_DIV_SHIFT = 2,
358 CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT,
359 /* CRU_CLKSEL_CON17 */
360 CLK_UART6_FRAC_DIV_SHIFT = 0,
361 CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
362 /* CRU_CLKSEL_CON18 */
363 SCLK_UART6_SRC_SEL_SHIFT = 0,
364 SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
365 CLK_UART7_SRC_DIV_SHIFT = 2,
366 CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT,
367 /* CRU_CLKSEL_CON19 */
368 CLK_UART7_FRAC_DIV_SHIFT = 0,
369 CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
370 /* CRU_CLKSEL_CON20 */
371 SCLK_UART7_SRC_SEL_SHIFT = 0,
372 SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
373 SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U,
374 SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U,
375 SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U,
376
377 /* CRU_CLKSEL_CON60 */
378 CLK_GMAC1_VPU_25M_DIV_SHIFT = 2,
379 CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
380 /* CRU_CLKSEL_CON66 */
381 CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0,
382 CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
383 /* CRU_CLKSEL_CON84 */
384 CLK_GMAC0_SRC_DIV_SHIFT = 3,
385 CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
386};
387
388#endif /* _ASM_ARCH_CRU_RK3528_H */