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Michal Simekf97470e2019-06-28 13:18:50 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
Michal Simeka8c94362023-07-10 14:35:49 +02007 * Michal Simek <michal.simek@amd.com>
Michal Simekf97470e2019-06-28 13:18:50 +02008 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Versal System Controller on a2197 Memory Char board RevA";
17 compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA",
18 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem0;
Michal Simekf97470e2019-06-28 13:18:50 +020022 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 mmc0 = &sdhci0;
25 mmc1 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +020026 nvmem0 = &eeprom;
Michal Simekf97470e2019-06-28 13:18:50 +020027 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &dcc;
31 usb0 = &usb0;
32 usb1 = &usb1;
33 spi0 = &qspi;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simekf97470e2019-06-28 13:18:50 +020039 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
44 };
45
46 ina226-vcc-aux {
47 compatible = "iio-hwmon";
48 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
49 };
50 ina226-vcc-ram {
51 compatible = "iio-hwmon";
52 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
53 };
54 ina226-vcc1v1-lp4 {
55 compatible = "iio-hwmon";
56 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
57 };
58 ina226-vcc1v2-lp4 {
59 compatible = "iio-hwmon";
60 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
61 };
62 ina226-vdd1-1v8-lp4 {
63 compatible = "iio-hwmon";
64 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
65 };
66};
67
68&qspi {
69 status = "okay";
Michal Simekad200322023-10-23 09:21:53 +020070 num-cs = <2>;
Michal Simekf97470e2019-06-28 13:18:50 +020071 flash@0 {
72 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simekad200322023-10-23 09:21:53 +020073 reg = <0>, <1>;
74 parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
Michal Simekf97470e2019-06-28 13:18:50 +020075 #address-cells = <1>;
76 #size-cells = <1>;
Amit Kumar Mahapatraa02408b2022-05-10 16:33:01 +020077 spi-tx-bus-width = <4>;
Michal Simekf97470e2019-06-28 13:18:50 +020078 spi-rx-bus-width = <4>;
79 spi-max-frequency = <108000000>;
80 };
81};
82
83&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
84 status = "okay";
85 non-removable;
86 disable-wp;
Paul Alvina1398f02024-09-25 09:03:13 +020087 no-sd;
88 no-sdio;
89 cap-mmc-hw-reset;
Michal Simekf97470e2019-06-28 13:18:50 +020090 bus-width = <8>;
Michal Simek3b662642020-07-22 17:42:43 +020091 xlnx,mio-bank = <0>; /* FIXME tap delay */
Michal Simekf97470e2019-06-28 13:18:50 +020092};
93
94&uart0 { /* uart0 MIO38-39 */
95 status = "okay";
Michal Simekf97470e2019-06-28 13:18:50 +020096};
97
98&uart1 { /* uart1 MIO40-41 */
99 status = "okay";
Michal Simekf97470e2019-06-28 13:18:50 +0200100};
101
102&sdhci1 { /* sd1 MIO45-51 cd in place */
Michal Simek81e3aa52024-09-13 11:28:42 +0200103 status = "disabled";
Michal Simekf97470e2019-06-28 13:18:50 +0200104 no-1-8-v;
105 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200106 xlnx,mio-bank = <1>;
Michal Simekf97470e2019-06-28 13:18:50 +0200107};
108
109&gem0 {
110 status = "okay";
111 phy-handle = <&phy0>;
112 phy-mode = "sgmii";
Michal Simek0641df72023-09-22 12:35:36 +0200113 mdio: mdio {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
117 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
118 reg = <0>;
119 };
Michal Simekf97470e2019-06-28 13:18:50 +0200120 };
121};
122
123&gpio {
124 status = "okay";
125 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
126 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
127 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
128 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
129 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
130 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
131 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
132 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
133 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
134 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
135 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
136 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
137 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
138 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
139 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
140 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Michal Simek45d57932024-09-13 11:28:45 +0200141 "", "", /* 78 - 79 */
Michal Simekf97470e2019-06-28 13:18:50 +0200142 "", "", "", "", "", /* 80 - 84 */
Michal Simeka8c5ce42024-09-13 11:28:46 +0200143 "", "", "", "", "", /* 85 - 89 */
Michal Simekf97470e2019-06-28 13:18:50 +0200144 "", "", "", "", "", /* 90 - 94 */
145 "", "", "", "", "", /* 95 - 99 */
146 "", "", "", "", "", /* 100 - 104 */
147 "", "", "", "", "", /* 105 - 109 */
148 "", "", "", "", "", /* 110 - 114 */
149 "", "", "", "", "", /* 115 - 119 */
150 "", "", "", "", "", /* 120 - 124 */
151 "", "", "", "", "", /* 125 - 129 */
152 "", "", "", "", "", /* 130 - 134 */
153 "", "", "", "", "", /* 135 - 139 */
154 "", "", "", "", "", /* 140 - 144 */
155 "", "", "", "", "", /* 145 - 149 */
156 "", "", "", "", "", /* 150 - 154 */
157 "", "", "", "", "", /* 155 - 159 */
158 "", "", "", "", "", /* 160 - 164 */
159 "", "", "", "", "", /* 165 - 169 */
Michal Simekfdf3fc62023-07-10 14:37:31 +0200160 "", "", "", ""; /* 170 - 173 */
Michal Simekf97470e2019-06-28 13:18:50 +0200161};
162
163&i2c0 { /* MIO 34-35 - can't stay here */
164 status = "okay";
165 clock-frequency = <400000>;
166 i2c-mux@74 { /* u46 */
167 compatible = "nxp,pca9548";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <0x74>;
171 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
172 i2c@0 { /* PMBUS must be enabled via SW21 */
173 #address-cells = <1>;
174 #size-cells = <0>;
175 reg = <0>;
176 reg_vcc1v2_lp4: tps544@15 { /* u97 */
177 compatible = "ti,tps544b25";
178 reg = <0x15>;
179 };
180 reg_vcc1v1_lp4: tps544@16 { /* u95 */
181 compatible = "ti,tps544b25";
182 reg = <0x16>;
183 };
184 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
185 compatible = "ti,tps544b25";
186 reg = <0x17>;
187 };
188 /* UTIL_PMBUS connection */
189 reg_vcc1v8: tps544@13 { /* u92 */
190 compatible = "ti,tps544b25";
191 reg = <0x13>;
192 };
193 reg_vcc3v3: tps544@14 { /* u93 */
194 compatible = "ti,tps544b25";
195 reg = <0x14>;
196 };
197 reg_vcc5v0: tps544@1e { /* u94 */
198 compatible = "ti,tps544b25";
199 reg = <0x1e>;
200 };
Michal Simekf97470e2019-06-28 13:18:50 +0200201 };
202 i2c@1 { /* PMBUS_INA226 */
203 #address-cells = <1>;
204 #size-cells = <0>;
205 reg = <1>;
206 vcc_aux: ina226@42 { /* u86 */
207 compatible = "ti,ina226";
208 #io-channel-cells = <1>;
209 label = "ina226-vcc-aux";
210 reg = <0x42>;
211 shunt-resistor = <5000>;
212 };
213 vcc_ram: ina226@43 { /* u81 */
214 compatible = "ti,ina226";
215 #io-channel-cells = <1>;
216 label = "ina226-vcc-ram";
217 reg = <0x43>;
218 shunt-resistor = <5000>;
219 };
220 vcc1v1_lp4: ina226@46 { /* u96 */
221 compatible = "ti,ina226";
222 #io-channel-cells = <1>;
223 label = "ina226-vcc1v1-lp4";
224 reg = <0x46>;
225 shunt-resistor = <5000>;
226 };
227 vcc1v2_lp4: ina226@47 { /* u98 */
228 compatible = "ti,ina226";
229 #io-channel-cells = <1>;
230 label = "ina226-vcc1v2-lp4";
231 reg = <0x47>;
232 shunt-resistor = <5000>;
233 };
234 vdd1_1v8_lp4: ina226@48 { /* u100 */
235 compatible = "ti,ina226";
236 #io-channel-cells = <1>;
237 label = "ina226-vdd1-1v8-lp4";
238 reg = <0x48>;
239 shunt-resistor = <5000>;
240 };
241 };
242 i2c@2 { /* PMBUS1 */
243 #address-cells = <1>;
244 #size-cells = <0>;
245 reg = <2>;
Michal Simekb6964242022-06-15 11:56:55 +0200246 reg_vccint: tps53681@60 { /* u69 - 0xc0 */
Michal Simekf97470e2019-06-28 13:18:50 +0200247 compatible = "ti,tps53681", "ti,tps53679";
Michal Simekb6964242022-06-15 11:56:55 +0200248 reg = <0x60>;
Michal Simekf97470e2019-06-28 13:18:50 +0200249 };
250 reg_vcc_pmc: tps544@7 { /* u80 */
251 compatible = "ti,tps544b25";
252 reg = <0x7>;
253 };
254 reg_vcc_ram: tps544@8 { /* u82 */
255 compatible = "ti,tps544b25";
256 reg = <0x8>;
257 };
258 reg_vcc_pslp: tps544@9 { /* u83 */
259 compatible = "ti,tps544b25";
260 reg = <0x9>;
261 };
262 reg_vcc_psfp: tps544@a { /* u84 */
263 compatible = "ti,tps544b25";
264 reg = <0xa>;
265 };
266 reg_vccaux: tps544@d { /* u85 */
267 compatible = "ti,tps544b25";
268 reg = <0xd>;
269 };
270 reg_vccaux_pmc: tps544@e { /* u87 */
271 compatible = "ti,tps544b25";
272 reg = <0xe>;
273 };
274 reg_vcco_500: tps544@f { /* u88 */
275 compatible = "ti,tps544b25";
276 reg = <0xf>;
277 };
278 reg_vcco_501: tps544@10 { /* u89 */
279 compatible = "ti,tps544b25";
280 reg = <0x10>;
281 };
282 reg_vcco_502: tps544@11 { /* u90 */
283 compatible = "ti,tps544b25";
284 reg = <0x11>;
285 };
286 reg_vcco_503: tps544@12 { /* u91 */
287 compatible = "ti,tps544b25";
288 reg = <0x12>;
289 };
290 };
291 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
292 #address-cells = <1>;
293 #size-cells = <0>;
Michal Simek57e7fce2024-09-13 11:28:47 +0200294 reg = <3>;
Michal Simekf97470e2019-06-28 13:18:50 +0200295 };
296 i2c@4 { /* LP_I2C_SM */
297 #address-cells = <1>;
298 #size-cells = <0>;
299 reg = <4>;
300 /* connected to U20G */
301 };
302 i2c@5 { /* C0_DDR4_RDIMM */
303 #address-cells = <1>;
304 #size-cells = <0>;
305 reg = <5>;
306 };
307 i2c@6 { /* C2_DDR5_RDIMM */
308 #address-cells = <1>;
309 #size-cells = <0>;
310 reg = <6>;
311 };
312 i2c@7 { /* C3_DDR4_UDIMM */
313 #address-cells = <1>;
314 #size-cells = <0>;
315 reg = <7>;
316 };
317 };
318};
319
320/* TODO sysctrl via J239 */
321/* TODO samtec J212G/H via J242 */
322/* TODO teensy via U30 PCA9543A bus 1 */
323&i2c1 { /* i2c1 MIO 36-37 */
324 status = "okay";
325 clock-frequency = <400000>;
326
327 /* Must be enabled via J242 */
328 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
329 compatible = "atmel,24c02";
330 reg = <0x51>;
331 };
332
333 i2c-mux@74 { /* u47 */
334 compatible = "nxp,pca9548";
335 #address-cells = <1>;
336 #size-cells = <0>;
337 reg = <0x74>;
338 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
339 dc_i2c: i2c@0 { /* DC_I2C */
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <0>;
343 /* Use for storing information about SC board */
344 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
345 compatible = "atmel,24c08";
346 reg = <0x54>;
347 };
348 si570_ref_clk: clock-generator@5d { /* u26 */
349 #clock-cells = <0>;
350 compatible = "silabs,si570";
351 reg = <0x5d>; /* FIXME addr */
352 temperature-stability = <50>;
Michal Simekf86d2b52021-03-09 12:43:42 +0100353 factory-fout = <33333333>;
Michal Simekf97470e2019-06-28 13:18:50 +0200354 clock-frequency = <33333333>;
355 clock-output-names = "REF_CLK"; /* FIXME */
Michal Simekf86d2b52021-03-09 12:43:42 +0100356 silabs,skip-recall;
Michal Simekf97470e2019-06-28 13:18:50 +0200357 };
358 /* Connection via Samtec U20D */
359 /* Use for storing information about X-PRC card */
360 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
361 compatible = "atmel,24c02";
362 reg = <0x52>;
363 };
364
365 /* Use for setting up certain features on X-PRC card */
366 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
367 compatible = "nxp,pca9534";
368 reg = <0x22>;
369 gpio-controller; /* IRQ not connected */
370 #gpio-cells = <2>;
371 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
372 "", "", "", "";
Michal Simek5368d402024-09-13 11:28:43 +0200373 gtr-sel0-hog {
Michal Simekf97470e2019-06-28 13:18:50 +0200374 gpio-hog;
375 gpios = <0 0>;
376 input; /* FIXME add meaning */
377 line-name = "sw4_1";
378 };
Michal Simek5368d402024-09-13 11:28:43 +0200379 gtr-sel1-hog {
Michal Simekf97470e2019-06-28 13:18:50 +0200380 gpio-hog;
381 gpios = <1 0>;
382 input; /* FIXME add meaning */
383 line-name = "sw4_2";
384 };
Michal Simek5368d402024-09-13 11:28:43 +0200385 gtr-sel2-hog {
Michal Simekf97470e2019-06-28 13:18:50 +0200386 gpio-hog;
387 gpios = <2 0>;
388 input; /* FIXME add meaning */
389 line-name = "sw4_3";
390 };
Michal Simek5368d402024-09-13 11:28:43 +0200391 gtr-sel3-hog {
Michal Simekf97470e2019-06-28 13:18:50 +0200392 gpio-hog;
393 gpios = <3 0>;
394 input; /* FIXME add meaning */
395 line-name = "sw4_4";
396 };
397 };
398 };
399 i2c@2 { /* C0_DDR4 */
400 #address-cells = <1>;
401 #size-cells = <0>;
402 reg = <2>;
403 si570_c0_ddr4: clock-generator@55 { /* u4 */
404 #clock-cells = <0>;
405 compatible = "silabs,si570";
406 reg = <0x55>;
407 temperature-stability = <50>;
408 factory-fout = <30000000>;
409 clock-frequency = <30000000>;
410 clock-output-names = "C0_DD4_SI570_CLK";
411 };
412 };
413 i2c@3 { /* C1_RLD3 */
414 #address-cells = <1>;
415 #size-cells = <0>;
416 reg = <3>;
417 si570_c1_lp4: clock-generator@55 { /* u7 */
418 #clock-cells = <0>;
419 compatible = "silabs,si570";
420 reg = <0x55>;
421 temperature-stability = <50>;
422 factory-fout = <30000000>;
423 clock-frequency = <30000000>;
424 clock-output-names = "C1_RLD3_SI570_CLK";
425 };
426 };
427 i2c@4 { /* C2_DDR5 */
428 #address-cells = <1>;
429 #size-cells = <0>;
430 reg = <4>;
431 si570_c2_lp4: clock-generator@55 { /* u10 */
432 #clock-cells = <0>;
433 compatible = "silabs,si570";
434 reg = <0x55>;
435 temperature-stability = <50>;
436 factory-fout = <30000000>;
437 clock-frequency = <30000000>;
438 clock-output-names = "C2_DDR5_SI570_CLK";
439 };
440 };
441 i2c@5 { /* C3_DDR4 */
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <5>;
445 si570_c3_lp4: clock-generator@55 { /* u15 */
446 #clock-cells = <0>;
447 compatible = "silabs,si570";
448 reg = <0x55>;
449 temperature-stability = <50>;
450 factory-fout = <30000000>;
451 clock-frequency = <30000000>;
452 clock-output-names = "C3_LP4_SI570_CLK";
453 };
454 };
455 i2c@6 { /* HSDP_SI570 */
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg = <6>;
459 si570_hsdp: clock-generator@5d { /* u19 */
460 #clock-cells = <0>;
461 compatible = "silabs,si570";
462 reg = <0x5d>;
463 temperature-stability = <50>;
464 factory-fout = <156250000>;
465 clock-frequency = <156250000>;
466 clock-output-names = "HSDP_SI570";
467 };
468 };
469 };
470};
471
472&usb0 {
473 status = "okay";
Michal Simekf97470e2019-06-28 13:18:50 +0200474};
475
476&dwc3_0 {
477 status = "okay";
478 dr_mode = "host";
479 /* dr_mode = "peripheral"; */
480 maximum-speed = "high-speed";
481};
482
483&usb1 {
484 status = "disabled"; /* not at mem board */
Michal Simekf97470e2019-06-28 13:18:50 +0200485};
486
487&dwc3_1 {
488 /delete-property/ phy-names ;
489 /delete-property/ phys ;
490 maximum-speed = "high-speed";
491 snps,dis_u2_susphy_quirk ;
492 snps,dis_u3_susphy_quirk ;
493 status = "disabled";
494};