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Michal Simek090a2d72018-03-27 10:36:39 +02001// SPDX-License-Identifier: GPL-2.0+
Michal Simeka6604b62017-12-08 14:50:42 +01002/*
3 * Clock specification for Xilinx ZynqMP
4 *
Michal Simek3f283ea2023-09-22 12:35:41 +02005 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
Michal Simeka6604b62017-12-08 14:50:42 +01007 *
Michal Simeka8c94362023-07-10 14:35:49 +02008 * Michal Simek <michal.simek@amd.com>
Michal Simeka6604b62017-12-08 14:50:42 +01009 */
10
Michal Simekebddf492019-10-14 15:42:03 +020011#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
Michal Simeka6604b62017-12-08 14:50:42 +010012/ {
Naman Trivedi94302132024-12-12 09:12:41 +010013 pss_ref_clk: pss-ref-clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -070014 bootph-all;
Michal Simeka6604b62017-12-08 14:50:42 +010015 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <33333333>;
Naman Trivedi94302132024-12-12 09:12:41 +010018 clock-output-names = "pss_ref_clk";
Michal Simeka6604b62017-12-08 14:50:42 +010019 };
20
Naman Trivedi94302132024-12-12 09:12:41 +010021 video_clk: video-clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -070022 bootph-all;
Michal Simeka6604b62017-12-08 14:50:42 +010023 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <27000000>;
Naman Trivedi94302132024-12-12 09:12:41 +010026 clock-output-names = "video_clk";
Michal Simeka6604b62017-12-08 14:50:42 +010027 };
28
Naman Trivedi94302132024-12-12 09:12:41 +010029 pss_alt_ref_clk: pss-alt-ref-clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -070030 bootph-all;
Michal Simeka6604b62017-12-08 14:50:42 +010031 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <0>;
Naman Trivedi94302132024-12-12 09:12:41 +010034 clock-output-names = "pss_alt_ref_clk";
Michal Simeka6604b62017-12-08 14:50:42 +010035 };
36
Naman Trivedi94302132024-12-12 09:12:41 +010037 gt_crx_ref_clk: gt-crx-ref-clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -070038 bootph-all;
Michal Simeka6604b62017-12-08 14:50:42 +010039 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <108000000>;
Naman Trivedi94302132024-12-12 09:12:41 +010042 clock-output-names = "gt_crx_ref_clk";
Michal Simeka6604b62017-12-08 14:50:42 +010043 };
44
Naman Trivedi94302132024-12-12 09:12:41 +010045 aux_ref_clk: aux-ref-clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -070046 bootph-all;
Michal Simeka6604b62017-12-08 14:50:42 +010047 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <27000000>;
Naman Trivedi94302132024-12-12 09:12:41 +010050 clock-output-names = "aux_ref_clk";
Michal Simeka6604b62017-12-08 14:50:42 +010051 };
Michal Simeka6604b62017-12-08 14:50:42 +010052};
53
Michal Simekebddf492019-10-14 15:42:03 +020054&zynqmp_firmware {
55 zynqmp_clk: clock-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -070056 bootph-all;
Michal Simekebddf492019-10-14 15:42:03 +020057 #clock-cells = <1>;
58 compatible = "xlnx,zynqmp-clk";
59 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
60 <&aux_ref_clk>, <&gt_crx_ref_clk>;
61 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
62 "aux_ref_clk", "gt_crx_ref_clk";
63 };
64};
65
Michal Simeka6604b62017-12-08 14:50:42 +010066&can0 {
Michal Simekebddf492019-10-14 15:42:03 +020067 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +010068};
69
70&can1 {
Michal Simekebddf492019-10-14 15:42:03 +020071 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +010072};
73
74&cpu0 {
Michal Simekebddf492019-10-14 15:42:03 +020075 clocks = <&zynqmp_clk ACPU>;
Michal Simeka6604b62017-12-08 14:50:42 +010076};
77
Michal Simek19e355d2024-11-28 15:49:14 +010078&cpu0_debug {
79 clocks = <&zynqmp_clk DBF_FPD>;
80};
81
82&cpu1_debug {
83 clocks = <&zynqmp_clk DBF_FPD>;
84};
85
86&cpu2_debug {
87 clocks = <&zynqmp_clk DBF_FPD>;
88};
89
90&cpu3_debug {
91 clocks = <&zynqmp_clk DBF_FPD>;
92};
93
Michal Simeka6604b62017-12-08 14:50:42 +010094&fpd_dma_chan1 {
Michal Simekebddf492019-10-14 15:42:03 +020095 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +010096};
97
98&fpd_dma_chan2 {
Michal Simekebddf492019-10-14 15:42:03 +020099 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100100};
101
102&fpd_dma_chan3 {
Michal Simekebddf492019-10-14 15:42:03 +0200103 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100104};
105
106&fpd_dma_chan4 {
Michal Simekebddf492019-10-14 15:42:03 +0200107 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100108};
109
110&fpd_dma_chan5 {
Michal Simekebddf492019-10-14 15:42:03 +0200111 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100112};
113
114&fpd_dma_chan6 {
Michal Simekebddf492019-10-14 15:42:03 +0200115 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100116};
117
118&fpd_dma_chan7 {
Michal Simekebddf492019-10-14 15:42:03 +0200119 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100120};
121
122&fpd_dma_chan8 {
Michal Simekebddf492019-10-14 15:42:03 +0200123 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100124};
125
126&gpu {
Parth Gajjara281ad02023-07-10 14:37:29 +0200127 clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100128};
129
130&lpd_dma_chan1 {
Michal Simekebddf492019-10-14 15:42:03 +0200131 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100132};
133
134&lpd_dma_chan2 {
Michal Simekebddf492019-10-14 15:42:03 +0200135 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100136};
137
138&lpd_dma_chan3 {
Michal Simekebddf492019-10-14 15:42:03 +0200139 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100140};
141
142&lpd_dma_chan4 {
Michal Simekebddf492019-10-14 15:42:03 +0200143 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100144};
145
146&lpd_dma_chan5 {
Michal Simekebddf492019-10-14 15:42:03 +0200147 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100148};
149
150&lpd_dma_chan6 {
Michal Simekebddf492019-10-14 15:42:03 +0200151 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100152};
153
154&lpd_dma_chan7 {
Michal Simekebddf492019-10-14 15:42:03 +0200155 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100156};
157
158&lpd_dma_chan8 {
Michal Simekebddf492019-10-14 15:42:03 +0200159 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100160};
161
162&nand0 {
Michal Simekebddf492019-10-14 15:42:03 +0200163 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100164};
165
166&gem0 {
Michal Simek1092d682020-01-09 14:15:07 +0100167 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
168 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
169 <&zynqmp_clk GEM_TSU>;
Harini Katakam14d5fee2023-07-10 14:37:30 +0200170 assigned-clocks = <&zynqmp_clk GEM_TSU>;
Michal Simeka6604b62017-12-08 14:50:42 +0100171};
172
173&gem1 {
Michal Simek1092d682020-01-09 14:15:07 +0100174 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
175 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
176 <&zynqmp_clk GEM_TSU>;
Harini Katakam14d5fee2023-07-10 14:37:30 +0200177 assigned-clocks = <&zynqmp_clk GEM_TSU>;
Michal Simeka6604b62017-12-08 14:50:42 +0100178};
179
180&gem2 {
Michal Simek1092d682020-01-09 14:15:07 +0100181 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
182 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
183 <&zynqmp_clk GEM_TSU>;
Harini Katakam14d5fee2023-07-10 14:37:30 +0200184 assigned-clocks = <&zynqmp_clk GEM_TSU>;
Michal Simeka6604b62017-12-08 14:50:42 +0100185};
186
187&gem3 {
Michal Simek1092d682020-01-09 14:15:07 +0100188 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
189 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
190 <&zynqmp_clk GEM_TSU>;
Harini Katakam14d5fee2023-07-10 14:37:30 +0200191 assigned-clocks = <&zynqmp_clk GEM_TSU>;
Michal Simeka6604b62017-12-08 14:50:42 +0100192};
193
194&gpio {
Michal Simekebddf492019-10-14 15:42:03 +0200195 clocks = <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100196};
197
198&i2c0 {
Michal Simekebddf492019-10-14 15:42:03 +0200199 clocks = <&zynqmp_clk I2C0_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100200};
201
202&i2c1 {
Michal Simekebddf492019-10-14 15:42:03 +0200203 clocks = <&zynqmp_clk I2C1_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100204};
205
206&pcie {
Michal Simekebddf492019-10-14 15:42:03 +0200207 clocks = <&zynqmp_clk PCIE_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100208};
209
210&qspi {
Michal Simekebddf492019-10-14 15:42:03 +0200211 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100212};
213
214&sata {
Michal Simekebddf492019-10-14 15:42:03 +0200215 clocks = <&zynqmp_clk SATA_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100216};
217
218&sdhci0 {
Michal Simekebddf492019-10-14 15:42:03 +0200219 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekbd8ca912022-02-23 16:17:39 +0100220 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100221};
222
223&sdhci1 {
Michal Simekebddf492019-10-14 15:42:03 +0200224 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekbd8ca912022-02-23 16:17:39 +0100225 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100226};
227
228&spi0 {
Michal Simekebddf492019-10-14 15:42:03 +0200229 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100230};
231
232&spi1 {
Michal Simekebddf492019-10-14 15:42:03 +0200233 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka6604b62017-12-08 14:50:42 +0100234};
235
Rajan Vaja36d68be2018-04-25 05:34:04 -0700236&ttc0 {
Michal Simekebddf492019-10-14 15:42:03 +0200237 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vaja36d68be2018-04-25 05:34:04 -0700238};
239
240&ttc1 {
Michal Simekebddf492019-10-14 15:42:03 +0200241 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vaja36d68be2018-04-25 05:34:04 -0700242};
243
244&ttc2 {
Michal Simekebddf492019-10-14 15:42:03 +0200245 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vaja36d68be2018-04-25 05:34:04 -0700246};
247
248&ttc3 {
Michal Simekebddf492019-10-14 15:42:03 +0200249 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vaja36d68be2018-04-25 05:34:04 -0700250};
251
Michal Simeka6604b62017-12-08 14:50:42 +0100252&uart0 {
Michal Simekebddf492019-10-14 15:42:03 +0200253 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simek10a25f22023-09-18 13:22:04 +0200254 assigned-clocks = <&zynqmp_clk UART0_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100255};
256
257&uart1 {
Michal Simekebddf492019-10-14 15:42:03 +0200258 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simek10a25f22023-09-18 13:22:04 +0200259 assigned-clocks = <&zynqmp_clk UART1_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100260};
261
262&usb0 {
Michal Simekebddf492019-10-14 15:42:03 +0200263 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simekbd8ca912022-02-23 16:17:39 +0100264 assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100265};
266
Piyush Mehtac687c652022-08-23 15:03:31 +0200267&dwc3_0 {
268 clocks = <&zynqmp_clk USB3_DUAL_REF>;
269};
270
Michal Simeka6604b62017-12-08 14:50:42 +0100271&usb1 {
Michal Simekebddf492019-10-14 15:42:03 +0200272 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simekbd8ca912022-02-23 16:17:39 +0100273 assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100274};
275
Piyush Mehtac687c652022-08-23 15:03:31 +0200276&dwc3_1 {
277 clocks = <&zynqmp_clk USB3_DUAL_REF>;
278};
279
Michal Simeka6604b62017-12-08 14:50:42 +0100280&watchdog0 {
Michal Simekebddf492019-10-14 15:42:03 +0200281 clocks = <&zynqmp_clk WDT>;
Michal Simeka6604b62017-12-08 14:50:42 +0100282};
283
Michal Simek7b6280e2018-07-18 09:25:43 +0200284&lpd_watchdog {
285 clocks = <&zynqmp_clk LPD_WDT>;
286};
287
Michal Simeka6604b62017-12-08 14:50:42 +0100288&xilinx_ams {
Michal Simekebddf492019-10-14 15:42:03 +0200289 clocks = <&zynqmp_clk AMS_REF>;
Michal Simeka6604b62017-12-08 14:50:42 +0100290};
291
Michal Simek958c0e92020-11-26 14:25:02 +0100292&zynqmp_dpdma {
Michal Simekebddf492019-10-14 15:42:03 +0200293 clocks = <&zynqmp_clk DPDMA_REF>;
Michal Simekeb10f6a2022-02-23 16:17:38 +0100294 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
Michal Simeka6604b62017-12-08 14:50:42 +0100295};
296
Michal Simek958c0e92020-11-26 14:25:02 +0100297&zynqmp_dpsub {
298 clocks = <&zynqmp_clk TOPSW_LSBUS>,
299 <&zynqmp_clk DP_AUDIO_REF>,
300 <&zynqmp_clk DP_VIDEO_REF>;
Michal Simekeb10f6a2022-02-23 16:17:38 +0100301 assigned-clocks = <&zynqmp_clk DP_STC_REF>,
302 <&zynqmp_clk DP_AUDIO_REF>,
303 <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
Nava kishore Manne042ae5e2019-10-18 18:07:32 +0200304};