Michal Simek | 090a2d7 | 2018-03-27 10:36:39 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Clock specification for Xilinx ZynqMP |
| 4 | * |
Michal Simek | 3f283ea | 2023-09-22 12:35:41 +0200 | [diff] [blame] | 5 | * (C) Copyright 2017 - 2022, Xilinx, Inc. |
| 6 | * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 7 | * |
Michal Simek | a8c9436 | 2023-07-10 14:35:49 +0200 | [diff] [blame] | 8 | * Michal Simek <michal.simek@amd.com> |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 9 | */ |
| 10 | |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 11 | #include <dt-bindings/clock/xlnx-zynqmp-clk.h> |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 12 | / { |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 13 | pss_ref_clk: pss-ref-clk { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 14 | bootph-all; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 15 | compatible = "fixed-clock"; |
| 16 | #clock-cells = <0>; |
| 17 | clock-frequency = <33333333>; |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 18 | clock-output-names = "pss_ref_clk"; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 19 | }; |
| 20 | |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 21 | video_clk: video-clk { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 22 | bootph-all; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 23 | compatible = "fixed-clock"; |
| 24 | #clock-cells = <0>; |
| 25 | clock-frequency = <27000000>; |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 26 | clock-output-names = "video_clk"; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 27 | }; |
| 28 | |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 29 | pss_alt_ref_clk: pss-alt-ref-clk { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 30 | bootph-all; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 31 | compatible = "fixed-clock"; |
| 32 | #clock-cells = <0>; |
| 33 | clock-frequency = <0>; |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 34 | clock-output-names = "pss_alt_ref_clk"; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 35 | }; |
| 36 | |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 37 | gt_crx_ref_clk: gt-crx-ref-clk { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 38 | bootph-all; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 39 | compatible = "fixed-clock"; |
| 40 | #clock-cells = <0>; |
| 41 | clock-frequency = <108000000>; |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 42 | clock-output-names = "gt_crx_ref_clk"; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 43 | }; |
| 44 | |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 45 | aux_ref_clk: aux-ref-clk { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 46 | bootph-all; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 47 | compatible = "fixed-clock"; |
| 48 | #clock-cells = <0>; |
| 49 | clock-frequency = <27000000>; |
Naman Trivedi | 9430213 | 2024-12-12 09:12:41 +0100 | [diff] [blame] | 50 | clock-output-names = "aux_ref_clk"; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 51 | }; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 52 | }; |
| 53 | |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 54 | &zynqmp_firmware { |
| 55 | zynqmp_clk: clock-controller { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 56 | bootph-all; |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 57 | #clock-cells = <1>; |
| 58 | compatible = "xlnx,zynqmp-clk"; |
| 59 | clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, |
| 60 | <&aux_ref_clk>, <>_crx_ref_clk>; |
| 61 | clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", |
| 62 | "aux_ref_clk", "gt_crx_ref_clk"; |
| 63 | }; |
| 64 | }; |
| 65 | |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 66 | &can0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 67 | clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | &can1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 71 | clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | &cpu0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 75 | clocks = <&zynqmp_clk ACPU>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 76 | }; |
| 77 | |
Michal Simek | 19e355d | 2024-11-28 15:49:14 +0100 | [diff] [blame] | 78 | &cpu0_debug { |
| 79 | clocks = <&zynqmp_clk DBF_FPD>; |
| 80 | }; |
| 81 | |
| 82 | &cpu1_debug { |
| 83 | clocks = <&zynqmp_clk DBF_FPD>; |
| 84 | }; |
| 85 | |
| 86 | &cpu2_debug { |
| 87 | clocks = <&zynqmp_clk DBF_FPD>; |
| 88 | }; |
| 89 | |
| 90 | &cpu3_debug { |
| 91 | clocks = <&zynqmp_clk DBF_FPD>; |
| 92 | }; |
| 93 | |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 94 | &fpd_dma_chan1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 95 | clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 96 | }; |
| 97 | |
| 98 | &fpd_dma_chan2 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 99 | clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | &fpd_dma_chan3 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 103 | clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | &fpd_dma_chan4 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 107 | clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 108 | }; |
| 109 | |
| 110 | &fpd_dma_chan5 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 111 | clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 112 | }; |
| 113 | |
| 114 | &fpd_dma_chan6 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 115 | clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | &fpd_dma_chan7 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 119 | clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 120 | }; |
| 121 | |
| 122 | &fpd_dma_chan8 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 123 | clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 124 | }; |
| 125 | |
| 126 | &gpu { |
Parth Gajjar | a281ad0 | 2023-07-10 14:37:29 +0200 | [diff] [blame] | 127 | clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 128 | }; |
| 129 | |
| 130 | &lpd_dma_chan1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 131 | clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 132 | }; |
| 133 | |
| 134 | &lpd_dma_chan2 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 135 | clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | &lpd_dma_chan3 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 139 | clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 140 | }; |
| 141 | |
| 142 | &lpd_dma_chan4 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 143 | clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | &lpd_dma_chan5 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 147 | clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 148 | }; |
| 149 | |
| 150 | &lpd_dma_chan6 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 151 | clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | &lpd_dma_chan7 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 155 | clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | &lpd_dma_chan8 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 159 | clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 160 | }; |
| 161 | |
| 162 | &nand0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 163 | clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 164 | }; |
| 165 | |
| 166 | &gem0 { |
Michal Simek | 1092d68 | 2020-01-09 14:15:07 +0100 | [diff] [blame] | 167 | clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, |
| 168 | <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, |
| 169 | <&zynqmp_clk GEM_TSU>; |
Harini Katakam | 14d5fee | 2023-07-10 14:37:30 +0200 | [diff] [blame] | 170 | assigned-clocks = <&zynqmp_clk GEM_TSU>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | &gem1 { |
Michal Simek | 1092d68 | 2020-01-09 14:15:07 +0100 | [diff] [blame] | 174 | clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, |
| 175 | <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, |
| 176 | <&zynqmp_clk GEM_TSU>; |
Harini Katakam | 14d5fee | 2023-07-10 14:37:30 +0200 | [diff] [blame] | 177 | assigned-clocks = <&zynqmp_clk GEM_TSU>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 178 | }; |
| 179 | |
| 180 | &gem2 { |
Michal Simek | 1092d68 | 2020-01-09 14:15:07 +0100 | [diff] [blame] | 181 | clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, |
| 182 | <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, |
| 183 | <&zynqmp_clk GEM_TSU>; |
Harini Katakam | 14d5fee | 2023-07-10 14:37:30 +0200 | [diff] [blame] | 184 | assigned-clocks = <&zynqmp_clk GEM_TSU>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 185 | }; |
| 186 | |
| 187 | &gem3 { |
Michal Simek | 1092d68 | 2020-01-09 14:15:07 +0100 | [diff] [blame] | 188 | clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, |
| 189 | <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, |
| 190 | <&zynqmp_clk GEM_TSU>; |
Harini Katakam | 14d5fee | 2023-07-10 14:37:30 +0200 | [diff] [blame] | 191 | assigned-clocks = <&zynqmp_clk GEM_TSU>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 192 | }; |
| 193 | |
| 194 | &gpio { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 195 | clocks = <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | &i2c0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 199 | clocks = <&zynqmp_clk I2C0_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | &i2c1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 203 | clocks = <&zynqmp_clk I2C1_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | &pcie { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 207 | clocks = <&zynqmp_clk PCIE_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 208 | }; |
| 209 | |
| 210 | &qspi { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 211 | clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | &sata { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 215 | clocks = <&zynqmp_clk SATA_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 216 | }; |
| 217 | |
| 218 | &sdhci0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 219 | clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | bd8ca91 | 2022-02-23 16:17:39 +0100 | [diff] [blame] | 220 | assigned-clocks = <&zynqmp_clk SDIO0_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 221 | }; |
| 222 | |
| 223 | &sdhci1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 224 | clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | bd8ca91 | 2022-02-23 16:17:39 +0100 | [diff] [blame] | 225 | assigned-clocks = <&zynqmp_clk SDIO1_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 226 | }; |
| 227 | |
| 228 | &spi0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 229 | clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 230 | }; |
| 231 | |
| 232 | &spi1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 233 | clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 234 | }; |
| 235 | |
Rajan Vaja | 36d68be | 2018-04-25 05:34:04 -0700 | [diff] [blame] | 236 | &ttc0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 237 | clocks = <&zynqmp_clk LPD_LSBUS>; |
Rajan Vaja | 36d68be | 2018-04-25 05:34:04 -0700 | [diff] [blame] | 238 | }; |
| 239 | |
| 240 | &ttc1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 241 | clocks = <&zynqmp_clk LPD_LSBUS>; |
Rajan Vaja | 36d68be | 2018-04-25 05:34:04 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
| 244 | &ttc2 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 245 | clocks = <&zynqmp_clk LPD_LSBUS>; |
Rajan Vaja | 36d68be | 2018-04-25 05:34:04 -0700 | [diff] [blame] | 246 | }; |
| 247 | |
| 248 | &ttc3 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 249 | clocks = <&zynqmp_clk LPD_LSBUS>; |
Rajan Vaja | 36d68be | 2018-04-25 05:34:04 -0700 | [diff] [blame] | 250 | }; |
| 251 | |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 252 | &uart0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 253 | clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | 10a25f2 | 2023-09-18 13:22:04 +0200 | [diff] [blame] | 254 | assigned-clocks = <&zynqmp_clk UART0_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 255 | }; |
| 256 | |
| 257 | &uart1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 258 | clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; |
Michal Simek | 10a25f2 | 2023-09-18 13:22:04 +0200 | [diff] [blame] | 259 | assigned-clocks = <&zynqmp_clk UART1_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 260 | }; |
| 261 | |
| 262 | &usb0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 263 | clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; |
Michal Simek | bd8ca91 | 2022-02-23 16:17:39 +0100 | [diff] [blame] | 264 | assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 265 | }; |
| 266 | |
Piyush Mehta | c687c65 | 2022-08-23 15:03:31 +0200 | [diff] [blame] | 267 | &dwc3_0 { |
| 268 | clocks = <&zynqmp_clk USB3_DUAL_REF>; |
| 269 | }; |
| 270 | |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 271 | &usb1 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 272 | clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; |
Michal Simek | bd8ca91 | 2022-02-23 16:17:39 +0100 | [diff] [blame] | 273 | assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 274 | }; |
| 275 | |
Piyush Mehta | c687c65 | 2022-08-23 15:03:31 +0200 | [diff] [blame] | 276 | &dwc3_1 { |
| 277 | clocks = <&zynqmp_clk USB3_DUAL_REF>; |
| 278 | }; |
| 279 | |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 280 | &watchdog0 { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 281 | clocks = <&zynqmp_clk WDT>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 282 | }; |
| 283 | |
Michal Simek | 7b6280e | 2018-07-18 09:25:43 +0200 | [diff] [blame] | 284 | &lpd_watchdog { |
| 285 | clocks = <&zynqmp_clk LPD_WDT>; |
| 286 | }; |
| 287 | |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 288 | &xilinx_ams { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 289 | clocks = <&zynqmp_clk AMS_REF>; |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 290 | }; |
| 291 | |
Michal Simek | 958c0e9 | 2020-11-26 14:25:02 +0100 | [diff] [blame] | 292 | &zynqmp_dpdma { |
Michal Simek | ebddf49 | 2019-10-14 15:42:03 +0200 | [diff] [blame] | 293 | clocks = <&zynqmp_clk DPDMA_REF>; |
Michal Simek | eb10f6a | 2022-02-23 16:17:38 +0100 | [diff] [blame] | 294 | assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ |
Michal Simek | a6604b6 | 2017-12-08 14:50:42 +0100 | [diff] [blame] | 295 | }; |
| 296 | |
Michal Simek | 958c0e9 | 2020-11-26 14:25:02 +0100 | [diff] [blame] | 297 | &zynqmp_dpsub { |
| 298 | clocks = <&zynqmp_clk TOPSW_LSBUS>, |
| 299 | <&zynqmp_clk DP_AUDIO_REF>, |
| 300 | <&zynqmp_clk DP_VIDEO_REF>; |
Michal Simek | eb10f6a | 2022-02-23 16:17:38 +0100 | [diff] [blame] | 301 | assigned-clocks = <&zynqmp_clk DP_STC_REF>, |
| 302 | <&zynqmp_clk DP_AUDIO_REF>, |
| 303 | <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ |
Nava kishore Manne | 042ae5e | 2019-10-18 18:07:32 +0200 | [diff] [blame] | 304 | }; |