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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / dts / tegra114-nvidia-tegratab.dts
blob: f65772a8e019b47ba7fce652e3db532af355c7f0 [file] [log] [blame]
Svyatoslav Ryhel8178e892023-06-29 10:10:26 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/input.h>
5#include "tegra114.dtsi"
6
7/ {
8 model = "NVIDIA Tegra Note 7";
9 compatible = "nvidia,tegratab", "nvidia,tegra114";
10
11 chosen {
12 stdout-path = &uartd;
13 };
14
15 aliases {
16 i2c0 = &pwr_i2c;
17
18 mmc0 = &sdmmc4; /* eMMC */
19 mmc1 = &sdmmc3; /* uSD slot */
20
21 usb0 = &usb1;
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x40000000>;
27 };
28
29 host1x@50000000 {
30 dc@54200000 {
31 nvidia,180-rotation;
32 };
33
34 dsia: dsi@54300000 {
35 status = "okay";
36
37 avdd-dsi-csi-supply = <&avdd_dsi_csi>;
38
39 panel@0 {
40 compatible = "lg,ld070wx3-sl01";
41 reg = <0>;
42
43 vdd-supply = <&avdd_3v3_lcd>;
44 vcc-supply = <&dvdd_1v8_lcd>;
45
46 backlight = <&backlight>;
47 };
48 };
49 };
50
51 pinmux@70000868 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&state_default>;
54
55 state_default: pinmux {
56 /* ULPI pinmux */
57 ulpi-data0 {
58 nvidia,pins = "ulpi_data0_po1",
59 "ulpi_data1_po2",
60 "ulpi_data2_po3",
61 "ulpi_data5_po6",
62 "ulpi_data6_po7",
63 "ulpi_data7_po0";
64 nvidia,function = "ulpi";
65 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
67 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
68 };
69 ulpi-data3 {
70 nvidia,pins = "ulpi_data3_po4",
71 "ulpi_data4_po5";
72 nvidia,function = "ulpi";
73 nvidia,pull = <TEGRA_PIN_PULL_UP>;
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76 };
77
78 /* SPI1 pinmux */
79 ulpi-clk {
80 nvidia,pins = "ulpi_clk_py0",
81 "ulpi_nxt_py2",
82 "ulpi_stp_py3";
83 nvidia,function = "spi1";
84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87 };
88 ulpi-dir {
89 nvidia,pins = "ulpi_dir_py1";
90 nvidia,function = "spi1";
91 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
92 nvidia,tristate = <TEGRA_PIN_DISABLE>;
93 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
94 };
95
96 /* I2S pinmux */
97 dap1-pins {
98 nvidia,pins = "dap1_fs_pn0",
99 "dap1_din_pn1",
100 "dap1_dout_pn2",
101 "dap1_sclk_pn3";
102 nvidia,function = "rsvd4";
103 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
104 nvidia,tristate = <TEGRA_PIN_ENABLE>;
105 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
106 };
107 dap2-dout {
108 nvidia,pins = "dap2_fs_pa2",
109 "dap2_sclk_pa3",
110 "dap2_dout_pa5";
111 nvidia,function = "i2s1";
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
115 };
116 dap2-din {
117 nvidia,pins = "dap2_din_pa4";
118 nvidia,function = "i2s1";
119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristate = <TEGRA_PIN_DISABLE>;
121 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
122 };
123 dap3-fs-pp0 {
124 nvidia,pins = "dap3_fs_pp0",
125 "dap3_din_pp1",
126 "dap3_dout_pp2",
127 "dap3_sclk_pp3";
128 nvidia,function = "i2s2";
129 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
130 nvidia,tristate = <TEGRA_PIN_ENABLE>;
131 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
132 };
133 pv0 {
134 nvidia,pins = "pv0";
135 nvidia,function = "rsvd2";
136 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
137 nvidia,tristate = <TEGRA_PIN_ENABLE>;
138 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
139 };
140 pv1 {
141 nvidia,pins = "pv1";
142 nvidia,function = "rsvd1";
143 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
144 nvidia,tristate = <TEGRA_PIN_ENABLE>;
145 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
146 };
147 dap4-din {
148 nvidia,pins = "dap4_din_pp5";
149 nvidia,function = "i2s3";
150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
152 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
153 };
154 dap4-dout {
155 nvidia,pins = "dap4_fs_pp4",
156 "dap4_dout_pp6",
157 "dap4_sclk_pp7";
158 nvidia,function = "i2s3";
159 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160 nvidia,tristate = <TEGRA_PIN_DISABLE>;
161 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
162 };
163
164 /* SDMMC1 pinmux */
165 sdmmc1-clk {
166 nvidia,pins = "sdmmc1_clk_pz0";
167 nvidia,function = "sdmmc1";
168 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
169 nvidia,tristate = <TEGRA_PIN_DISABLE>;
170 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
171 };
172 sdmmc1-cmd {
173 nvidia,pins = "sdmmc1_cmd_pz1",
174 "sdmmc1_dat0_py7",
175 "sdmmc1_dat1_py6",
176 "sdmmc1_dat2_py5",
177 "sdmmc1_dat3_py4";
178 nvidia,function = "sdmmc1";
179 nvidia,pull = <TEGRA_PIN_PULL_UP>;
180 nvidia,tristate = <TEGRA_PIN_DISABLE>;
181 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
182 };
183 sdmmc1-wp-n {
184 nvidia,pins = "sdmmc1_wp_n_pv3";
185 nvidia,function = "sdmmc1";
186 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187 nvidia,tristate = <TEGRA_PIN_DISABLE>;
188 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
189 };
190
191 /* SDMMC3 pinmux */
192 sdmmc3-clk {
193 nvidia,pins = "sdmmc3_clk_pa6";
194 nvidia,function = "sdmmc3";
195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196 nvidia,tristate = <TEGRA_PIN_DISABLE>;
197 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
198 };
199 sdmmc3-cmd {
200 nvidia,pins = "sdmmc3_cmd_pa7",
201 "sdmmc3_dat0_pb7",
202 "sdmmc3_dat1_pb6",
203 "sdmmc3_dat2_pb5",
204 "sdmmc3_dat3_pb4",
205 "sdmmc3_cd_n_pv2";
206 nvidia,function = "sdmmc3";
207 nvidia,pull = <TEGRA_PIN_PULL_UP>;
208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
209 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
210 };
211 sdmmc3-clk-lb {
212 nvidia,pins = "sdmmc3_clk_lb_out_pee4",
213 "sdmmc3_clk_lb_in_pee5";
214 nvidia,function = "sdmmc3";
215 nvidia,pull = <TEGRA_PIN_PULL_UP>;
216 nvidia,tristate = <TEGRA_PIN_DISABLE>;
217 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
218 };
219
220 /* SDMMC4 pinmux */
221 sdmmc4-clk {
222 nvidia,pins = "sdmmc4_clk_pcc4";
223 nvidia,function = "sdmmc4";
224 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
226 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
227 };
228 sdmmc4-cmd {
229 nvidia,pins = "sdmmc4_cmd_pt7",
230 "sdmmc4_dat0_paa0",
231 "sdmmc4_dat1_paa1",
232 "sdmmc4_dat2_paa2",
233 "sdmmc4_dat3_paa3",
234 "sdmmc4_dat4_paa4",
235 "sdmmc4_dat5_paa5",
236 "sdmmc4_dat6_paa6",
237 "sdmmc4_dat7_paa7";
238 nvidia,function = "sdmmc4";
239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
240 nvidia,tristate = <TEGRA_PIN_DISABLE>;
241 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
242 };
243
244 /* EXTPERIPH pinmux */
245 clk1-req {
246 nvidia,pins = "clk1_req_pee2";
247 nvidia,function = "rsvd3";
248 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
249 nvidia,tristate = <TEGRA_PIN_ENABLE>;
250 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
251 };
252 clk1-out {
253 nvidia,pins = "clk1_out_pw4";
254 nvidia,function = "extperiph1";
255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
257 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
258 };
259 clk2-req {
260 nvidia,pins = "clk2_req_pcc5";
261 nvidia,function = "rsvd2";
262 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263 nvidia,tristate = <TEGRA_PIN_DISABLE>;
264 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
265 };
266 clk2-out {
267 nvidia,pins = "clk2_out_pw5";
268 nvidia,function = "extperiph2";
269 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
270 nvidia,tristate = <TEGRA_PIN_DISABLE>;
271 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
272 };
273 clk3-req-pee1 {
274 nvidia,pins = "clk3_req_pee1";
275 nvidia,function = "rsvd2";
276 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
277 nvidia,tristate = <TEGRA_PIN_DISABLE>;
278 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
279 };
280 clk3-out {
281 nvidia,pins = "clk3_out_pee0";
282 nvidia,function = "extperiph3";
283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
285 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
286 };
287
288 dvfs-pinmux {
289 nvidia,pins = "dvfs_pwm_px0",
290 "dvfs_clk_px2";
291 nvidia,function = "cldvfs";
292 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
293 nvidia,tristate = <TEGRA_PIN_DISABLE>;
294 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
295 };
296
297 /* HDMI pinmux */
298 hdmi-irq {
299 nvidia,pins = "hdmi_int_pn7";
300 nvidia,function = "rsvd1";
301 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
302 nvidia,tristate = <TEGRA_PIN_DISABLE>;
303 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
304 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
305 };
306 hdmi-cec {
307 nvidia,pins = "hdmi_cec_pee3";
308 nvidia,function = "cec";
309 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
310 nvidia,tristate = <TEGRA_PIN_DISABLE>;
311 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
312 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
313 };
314
315 /* I2C pinmux */
316 gen1-i2c {
317 nvidia,pins = "gen1_i2c_scl_pc4",
318 "gen1_i2c_sda_pc5";
319 nvidia,function = "i2c1";
320 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
321 nvidia,tristate = <TEGRA_PIN_DISABLE>;
322 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
323 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
324 };
325 gen2-i2c {
326 nvidia,pins = "gen2_i2c_scl_pt5",
327 "gen2_i2c_sda_pt6";
328 nvidia,function = "i2c2";
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330 nvidia,tristate = <TEGRA_PIN_DISABLE>;
331 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
332 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
333 };
334 cam-i2c {
335 nvidia,pins = "cam_i2c_scl_pbb1",
336 "cam_i2c_sda_pbb2";
337 nvidia,function = "i2c3";
338 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
339 nvidia,tristate = <TEGRA_PIN_DISABLE>;
340 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
341 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
342 };
343 ddc-scl-pv4 {
344 nvidia,pins = "ddc_scl_pv4",
345 "ddc_sda_pv5";
346 nvidia,function = "i2c4";
347 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
348 nvidia,tristate = <TEGRA_PIN_DISABLE>;
349 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
350 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
351 };
352 pwr-i2c {
353 nvidia,pins = "pwr_i2c_scl_pz6",
354 "pwr_i2c_sda_pz7";
355 nvidia,function = "i2cpwr";
356 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
357 nvidia,tristate = <TEGRA_PIN_DISABLE>;
358 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
359 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
360 };
361
362 /* UARTA pinmux */
363 uarta-out {
364 nvidia,pins = "kb_row9_ps1";
365 nvidia,function = "uarta";
366 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
367 nvidia,tristate = <TEGRA_PIN_DISABLE>;
368 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
369 };
370 uarta-in {
371 nvidia,pins = "kb_row10_ps2";
372 nvidia,function = "uarta";
373 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
374 nvidia,tristate = <TEGRA_PIN_DISABLE>;
375 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
376 };
377
378 /* UARTB pinmux */
379 uart2-cts-rts {
380 nvidia,pins = "uart2_cts_n_pj5",
381 "uart2_rts_n_pj6";
382 nvidia,function = "rsvd3";
383 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
384 nvidia,tristate = <TEGRA_PIN_ENABLE>;
385 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
386 };
387
388 /* UARTC pinmux */
389 uart3-cts-rxd {
390 nvidia,pins = "uart3_cts_n_pa1",
391 "uart3_rxd_pw7";
392 nvidia,function = "uartc";
393 nvidia,pull = <TEGRA_PIN_PULL_UP>;
394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
395 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
396 };
397 uart3-rts-txd {
398 nvidia,pins = "uart3_rts_n_pc0",
399 "uart3_txd_pw6";
400 nvidia,function = "uartc";
401 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
402 nvidia,tristate = <TEGRA_PIN_DISABLE>;
403 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
404 };
405
406 /* UARTD pinmux */
407 gmi-a17 {
408 nvidia,pins = "gmi_a17_pb0";
409 nvidia,function = "uartd";
410 nvidia,pull = <TEGRA_PIN_PULL_UP>;
411 nvidia,tristate = <TEGRA_PIN_DISABLE>;
412 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
413 };
414 gmi-a18 {
415 nvidia,pins = "gmi_a18_pb1";
416 nvidia,function = "uartd";
417 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
418 nvidia,tristate = <TEGRA_PIN_DISABLE>;
419 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
420 };
421 uartd-out {
422 nvidia,pins = "gmi_a16_pj7",
423 "gmi_a19_pk7";
424 nvidia,function = "uartd";
425 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
426 nvidia,tristate = <TEGRA_PIN_DISABLE>;
427 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
428 };
429
430 /* PORT U */
431 pu0 {
432 nvidia,pins = "pu0";
433 nvidia,function = "rsvd3";
434 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
435 nvidia,tristate = <TEGRA_PIN_ENABLE>;
436 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
437 };
438 pu1-2 {
439 nvidia,pins = "pu1", "pu2";
440 nvidia,function = "rsvd1";
441 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
442 nvidia,tristate = <TEGRA_PIN_ENABLE>;
443 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
444 };
445 pu3 {
446 nvidia,pins = "pu3";
447 nvidia,function = "pwm0";
448 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
449 nvidia,tristate = <TEGRA_PIN_ENABLE>;
450 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
451 };
452 pu4 {
453 nvidia,pins = "pu4";
454 nvidia,function = "pwm1";
455 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
456 nvidia,tristate = <TEGRA_PIN_ENABLE>;
457 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
458 };
459 pu5 {
460 nvidia,pins = "pu5";
461 nvidia,function = "pwm2";
462 nvidia,pull = <TEGRA_PIN_PULL_UP>;
463 nvidia,tristate = <TEGRA_PIN_DISABLE>;
464 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
465 };
466 pu6 {
467 nvidia,pins = "pu6";
468 nvidia,function = "pwm3";
469 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
470 nvidia,tristate = <TEGRA_PIN_DISABLE>;
471 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
472 };
473
474 /* GMI section */
475 gmi-wp-n-pc7 {
476 nvidia,pins = "gmi_wp_n_pc7",
477 "gmi_adv_n_pk0",
478 "gmi_cs0_n_pj0",
479 "gmi_wr_n_pi0";
480 nvidia,function = "rsvd1";
481 nvidia,pull = <TEGRA_PIN_PULL_UP>;
482 nvidia,tristate = <TEGRA_PIN_DISABLE>;
483 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
484 };
485 gmi-iordy-pi5 {
486 nvidia,pins = "gmi_iordy_pi5";
487 nvidia,function = "rsvd2";
488 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
489 nvidia,tristate = <TEGRA_PIN_ENABLE>;
490 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
491 };
492 gmi-wait-pi7 {
493 nvidia,pins = "gmi_wait_pi7";
494 nvidia,function = "nand";
495 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
496 nvidia,tristate = <TEGRA_PIN_DISABLE>;
497 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
498 };
499 gmi-clk-pk1 {
500 nvidia,pins = "gmi_clk_pk1",
501 "gmi_ad10_ph2",
502 "gmi_ad11_ph3",
503 "gmi_ad14_ph6",
504 "gmi_cs3_n_pk4";
505 nvidia,function = "gmi";
506 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
507 nvidia,tristate = <TEGRA_PIN_DISABLE>;
508 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
509 };
510 gmi-cs2-n-pk3 {
511 nvidia,pins = "gmi_cs2_n_pk3";
512 nvidia,function = "gmi";
513 nvidia,pull = <TEGRA_PIN_PULL_UP>;
514 nvidia,tristate = <TEGRA_PIN_DISABLE>;
515 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
516 };
517 gmi-cs4-n-pk2 {
518 nvidia,pins = "gmi_cs4_n_pk2";
519 nvidia,function = "gmi";
520 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
521 nvidia,tristate = <TEGRA_PIN_ENABLE>;
522 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
523 };
524 gmi-cs6-n-pi3 {
525 nvidia,pins = "gmi_cs6_n_pi3";
526 nvidia,function = "nand";
527 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
528 nvidia,tristate = <TEGRA_PIN_ENABLE>;
529 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
530 };
531 gmi-cs7-n-pi6 {
532 nvidia,pins = "gmi_cs7_n_pi6";
533 nvidia,function = "nand";
534 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
535 nvidia,tristate = <TEGRA_PIN_DISABLE>;
536 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
537 };
538 gmi-ad0-pg0 {
539 nvidia,pins = "gmi_ad0_pg0";
540 nvidia,function = "rsvd1";
541 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
542 nvidia,tristate = <TEGRA_PIN_DISABLE>;
543 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
544 };
545 gmi-ad1-pg1 {
546 nvidia,pins = "gmi_ad1_pg1",
547 "gmi_ad4_pg4",
548 "gmi_ad5_pg5",
549 "gmi_ad6_pg6",
550 "gmi_ad7_pg7";
551 nvidia,function = "rsvd1";
552 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
553 nvidia,tristate = <TEGRA_PIN_ENABLE>;
554 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
555 };
556 gmi-ad2-pg2 {
557 nvidia,pins = "gmi_ad2_pg2",
558 "gmi_ad3_pg3",
559 "gmi_oe_n_pi1";
560 nvidia,function = "rsvd1";
561 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
562 nvidia,tristate = <TEGRA_PIN_DISABLE>;
563 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
564 };
565 gmi-ad8-ph0 {
566 nvidia,pins = "gmi_ad8_ph0";
567 nvidia,function = "gmi";
568 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
569 nvidia,tristate = <TEGRA_PIN_ENABLE>;
570 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
571 };
572 gmi-ad9 {
573 nvidia,pins = "gmi_ad9_ph1";
574 nvidia,function = "pwm1";
575 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
576 nvidia,tristate = <TEGRA_PIN_DISABLE>;
577 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
578 };
579 gmi-ad12-ph4 {
580 nvidia,pins = "gmi_ad12_ph4";
581 nvidia,function = "rsvd4";
582 nvidia,pull = <TEGRA_PIN_PULL_UP>;
583 nvidia,tristate = <TEGRA_PIN_DISABLE>;
584 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
585 };
586 gmi-ad13-ph5 {
587 nvidia,pins = "gmi_ad13_ph5";
588 nvidia,function = "rsvd4";
589 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
590 nvidia,tristate = <TEGRA_PIN_DISABLE>;
591 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
592 };
593 gmi-ad15-ph7 {
594 nvidia,pins = "gmi_ad15_ph7";
595 nvidia,function = "gmi";
596 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
597 nvidia,tristate = <TEGRA_PIN_ENABLE>;
598 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
599 };
600 gmi-dqs-p-pj3 {
601 nvidia,pins = "gmi_dqs_p_pj3";
602 nvidia,function = "nand";
603 nvidia,pull = <TEGRA_PIN_PULL_UP>;
604 nvidia,tristate = <TEGRA_PIN_DISABLE>;
605 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
606 };
607 gmi-rst-n-pi4 {
608 nvidia,pins = "gmi_rst_n_pi4";
609 nvidia,function = "rsvd4";
610 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
611 nvidia,tristate = <TEGRA_PIN_DISABLE>;
612 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
613 };
614 gmi-clk-lb {
615 nvidia,pins = "gmi_clk_lb";
616 nvidia,function = "gmi";
617 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
618 nvidia,tristate = <TEGRA_PIN_DISABLE>;
619 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
620 };
621
622 /* VI_ALT3 pinmux */
623 cam-mclk {
624 nvidia,pins = "pbb0", "cam_mclk_pcc0";
625 nvidia,function = "vi_alt3";
626 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
627 nvidia,tristate = <TEGRA_PIN_DISABLE>;
628 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
629 };
630
631 port-bb {
632 nvidia,pins = "pbb3", "pbb4", "pbb5",
633 "pbb6", "pbb7";
634 nvidia,function = "rsvd4";
635 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
636 nvidia,tristate = <TEGRA_PIN_DISABLE>;
637 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
638 };
639
640 port-cc {
641 nvidia,pins = "pcc1", "pcc2";
642 nvidia,function = "rsvd2";
643 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
644 nvidia,tristate = <TEGRA_PIN_DISABLE>;
645 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
646 };
647
648 jtag-rtck {
649 nvidia,pins = "jtag_rtck";
650 nvidia,function = "rtck";
651 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
652 nvidia,tristate = <TEGRA_PIN_DISABLE>;
653 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
654 };
655
656 /* KBC pinmux */
657 kb-row0-pr0 {
658 nvidia,pins = "kb_row0_pr0",
659 "kb_row1_pr1";
660 nvidia,function = "rsvd2";
661 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
662 nvidia,tristate = <TEGRA_PIN_DISABLE>;
663 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
664 };
665 kb-row2-pr2 {
666 nvidia,pins = "kb_row2_pr2",
667 "kb_col0_pq0";
668 nvidia,function = "kbc";
669 nvidia,pull = <TEGRA_PIN_PULL_UP>;
670 nvidia,tristate = <TEGRA_PIN_DISABLE>;
671 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
672 };
673 kb-row3-pr3 {
674 nvidia,pins = "kb_row3_pr3";
675 nvidia,function = "rsvd3";
676 nvidia,pull = <TEGRA_PIN_PULL_UP>;
677 nvidia,tristate = <TEGRA_PIN_DISABLE>;
678 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
679 };
680 kb-row4-pr4 {
681 nvidia,pins = "kb_row4_pr4",
682 "kb_row5_pr5",
683 "kb_row6_pr6",
684 "kb_col3_pq3",
685 "kb_col4_pq4";
686 nvidia,function = "kbc";
687 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
688 nvidia,tristate = <TEGRA_PIN_ENABLE>;
689 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
690 };
691 kb-row7-pr7 {
692 nvidia,pins = "kb_row7_pr7",
693 "kb_col2_pq2",
694 "kb_col5_pq5";
695 nvidia,function = "rsvd2";
696 nvidia,pull = <TEGRA_PIN_PULL_UP>;
697 nvidia,tristate = <TEGRA_PIN_DISABLE>;
698 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
699 };
700 kb-row8-ps0 {
701 nvidia,pins = "kb_row8_ps0",
702 "kb_col1_pq1",
703 "kb_col6_pq6",
704 "kb_col7_pq7";
705 nvidia,function = "rsvd2";
706 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
707 nvidia,tristate = <TEGRA_PIN_ENABLE>;
708 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
709 };
710
711 /* CORE pinmux */
712 sys-clk-req {
713 nvidia,pins = "sys_clk_req_pz5";
714 nvidia,function = "rsvd2";
715 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
716 nvidia,tristate = <TEGRA_PIN_ENABLE>;
717 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
718 };
719 clk-32k-out {
720 nvidia,pins = "clk_32k_out_pa0",
721 "gmi_cs1_n_pj2";
722 nvidia,function = "soc";
723 nvidia,pull = <TEGRA_PIN_PULL_UP>;
724 nvidia,tristate = <TEGRA_PIN_ENABLE>;
725 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
726 };
727 clk-32k-in {
728 nvidia,pins = "clk_32k_in";
729 nvidia,function = "clk";
730 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
731 nvidia,tristate = <TEGRA_PIN_DISABLE>;
732 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
733 };
734 core-pwr-req {
735 nvidia,pins = "core_pwr_req";
736 nvidia,function = "pwron";
737 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
738 nvidia,tristate = <TEGRA_PIN_DISABLE>;
739 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
740 };
741 cpu-pwr-req {
742 nvidia,pins = "cpu_pwr_req";
743 nvidia,function = "cpu";
744 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
745 nvidia,tristate = <TEGRA_PIN_DISABLE>;
746 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
747 };
748 pwr-int-n {
749 nvidia,pins = "pwr_int_n";
750 nvidia,function = "pmi";
751 nvidia,pull = <TEGRA_PIN_PULL_UP>;
752 nvidia,tristate = <TEGRA_PIN_DISABLE>;
753 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
754 };
755 owr {
756 nvidia,pins = "owr";
757 nvidia,function = "rsvd2";
758 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
759 nvidia,tristate = <TEGRA_PIN_ENABLE>;
760 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
761 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
762 };
763 reset-out-n {
764 nvidia,pins = "reset_out_n";
765 nvidia,function = "reset_out_n";
766 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
767 nvidia,tristate = <TEGRA_PIN_DISABLE>;
768 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
769 };
770
771 /* AUD pinmux */
772 gpio-x1-aud-px1 {
773 nvidia,pins = "gpio_x1_aud_px1";
774 nvidia,function = "rsvd2";
775 nvidia,pull = <TEGRA_PIN_PULL_UP>;
776 nvidia,tristate = <TEGRA_PIN_DISABLE>;
777 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
778 };
779 gpio-x3-aud-px3 {
780 nvidia,pins = "gpio_x3_aud_px3";
781 nvidia,function = "rsvd3";
782 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
783 nvidia,tristate = <TEGRA_PIN_ENABLE>;
784 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
785 };
786 gpio-x4-aud-px4 {
787 nvidia,pins = "gpio_x4_aud_px4",
788 "gpio_x5_aud_px5",
789 "gpio_x7_aud_px7";
790 nvidia,function = "rsvd1";
791 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
792 nvidia,tristate = <TEGRA_PIN_ENABLE>;
793 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
794 };
795 gpio-x6-aud-px6 {
796 nvidia,pins = "gpio_x6_aud_px6";
797 nvidia,function = "rsvd4";
798 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
799 nvidia,tristate = <TEGRA_PIN_ENABLE>;
800 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
801 };
802 gpio-w2-aud-pw2 {
803 nvidia,pins = "gpio_w2_aud_pw2";
804 nvidia,function = "rsvd2";
805 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
806 nvidia,tristate = <TEGRA_PIN_ENABLE>;
807 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
808 };
809 gpio-w3-aud-pw3 {
810 nvidia,pins = "gpio_w3_aud_pw3";
811 nvidia,function = "spi6";
812 nvidia,pull = <TEGRA_PIN_PULL_UP>;
813 nvidia,tristate = <TEGRA_PIN_DISABLE>;
814 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815 };
816
817 usb-vbus-en {
818 nvidia,pins = "usb_vbus_en0_pn4",
819 "usb_vbus_en1_pn5";
820 nvidia,function = "rsvd2";
821 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
822 nvidia,tristate = <TEGRA_PIN_ENABLE>;
823 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
824 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
825 };
826
827 /* GPIO power/drive control */
828 drive-sdio1 {
829 nvidia,pins = "drive_sdio1";
830 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
831 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
832 nvidia,pull-down-strength = <36>;
833 nvidia,pull-up-strength = <20>;
834 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
835 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
836 };
837 drive-sdio3 {
838 nvidia,pins = "drive_sdio3";
839 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
840 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
841 nvidia,pull-down-strength = <22>;
842 nvidia,pull-up-strength = <36>;
843 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
844 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
845 };
846 drive-gma {
847 nvidia,pins = "drive_gma";
848 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
849 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
850 nvidia,pull-down-strength = <2>;
851 nvidia,pull-up-strength = <2>;
852 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
853 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
854 };
855 };
856 };
857
858 uartd: serial@70006300 {
859 status = "okay";
860 };
861
862 pwm: pwm@7000a000 {
863 status = "okay";
864 };
865
866 pwr_i2c: i2c@7000d000 {
867 status = "okay";
868 clock-frequency = <400000>;
869
870 /* Texas Instruments TPS65913 PMIC */
871 pmic: tps65913@58 {
872 compatible = "ti,tps65913";
873 reg = <0x58>;
874
875 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
876 #interrupt-cells = <2>;
877 interrupt-controller;
878
879 ti,system-power-controller;
880
881 palmas_gpio: gpio {
882 compatible = "ti,palmas-gpio";
883 gpio-controller;
884 #gpio-cells = <2>;
885 };
886
887 pinmux {
888 compatible = "ti,tps65913-pinctrl";
889 ti,palmas-enable-dvfs1;
890
891 pinctrl-names = "default";
892 pinctrl-0 = <&palmas_default>;
893
894 palmas_default: pinmux {
895 pin_gpio4 {
896 pins = "gpio4";
897 function = "gpio";
898 };
899 };
900 };
901
902 pmic {
903 compatible = "ti,tps65913-pmic";
904
905 regulators {
906 avdd_3v3_lcd: smps6 {
907 regulator-name = "vdd_lcd_hv";
908 regulator-min-microvolt = <3160000>;
909 regulator-max-microvolt = <3160000>;
910 regulator-boot-on;
911 };
912
913 vdd_1v8_vio: smps8 {
914 regulator-name = "vdd_1v8_gen";
915 regulator-min-microvolt = <1800000>;
916 regulator-max-microvolt = <1800000>;
917 regulator-always-on;
918 regulator-boot-on;
919 };
920
921 vcore_emmc: smps9 {
922 regulator-name = "vdd_sdmmc";
923 regulator-min-microvolt = <2900000>;
924 regulator-max-microvolt = <2900000>;
925 regulator-always-on;
926 regulator-boot-on;
927 };
928
929 avdd_dsi_csi: ldo2 {
930 regulator-name = "avdd_dsi_csi";
931 regulator-min-microvolt = <1200000>;
932 regulator-max-microvolt = <1200000>;
933 regulator-boot-on;
934 };
935
936 vddio_usd: ldo9 {
937 regulator-name = "vddio_sdmmc";
938 regulator-min-microvolt = <2900000>;
939 regulator-max-microvolt = <2900000>;
940 regulator-always-on;
941 regulator-boot-on;
942 };
943
944 avdd_usb: ldousb {
945 regulator-name = "vdd_usb";
946 regulator-min-microvolt = <3300000>;
947 regulator-max-microvolt = <3300000>;
948 regulator-always-on;
949 regulator-boot-on;
950 };
951 };
952 };
953 };
954 };
955
956 sdmmc3: sdhci@78000400 {
957 status = "okay";
958 bus-width = <4>;
959
960 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
961 power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
962
963 nvidia,default-tap = <0x3>;
964 nvidia,default-trim = <0x3>;
965
966 vmmc-supply = <&vcore_emmc>;
967 vqmmc-supply = <&vddio_usd>;
968 };
969
970 sdmmc4: sdhci@78000600 {
971 status = "okay";
972 bus-width = <8>;
973 non-removable;
974
975 vmmc-supply = <&vcore_emmc>;
976 vqmmc-supply = <&vdd_1v8_vio>;
977 };
978
979 usb1: usb@7d000000 {
980 status = "okay";
981 dr_mode = "otg";
982 };
983
984 backlight: backlight {
985 compatible = "pwm-backlight";
986
987 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
988 pwms = <&pwm 1 1000000>;
989
990 brightness-levels = <1 35 70 105 140 175 210 255>;
991 default-brightness-level = <5>;
992 };
993
994 clk32k_in: clock-32k {
995 compatible = "fixed-clock";
996 #clock-cells = <0>;
997 clock-frequency = <32768>;
998 clock-output-names = "ref-oscillator";
999 };
1000
1001 extcon-keys {
1002 compatible = "gpio-keys";
1003
1004 switch-hall-sensor {
1005 label = "Hall Sensor";
1006 gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
1007 linux,code = <SW_LID>;
1008 };
1009 };
1010
1011 gpio-keys {
1012 compatible = "gpio-keys";
1013
1014 key-power {
1015 label = "Power";
1016 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1017 linux,code = <KEY_ENTER>;
1018 };
1019
1020 key-volume-up {
1021 label = "Volume Up";
1022 gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
1023 linux,code = <KEY_UP>;
1024 };
1025
1026 key-volume-down {
1027 label = "Volume Down";
1028 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
1029 linux,code = <KEY_DOWN>;
1030 };
1031 };
1032
1033 dvdd_1v8_lcd: regulator-lcdvio {
1034 compatible = "regulator-fixed";
1035 regulator-name = "dvdd_lcd";
1036 regulator-min-microvolt = <1800000>;
1037 regulator-max-microvolt = <1800000>;
1038 gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>;
1039 enable-active-high;
1040 };
1041};