Svyatoslav Ryhel | f1ec06b | 2023-03-14 18:24:51 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /dts-v1/; |
| 3 | |
| 4 | #include <dt-bindings/input/input.h> |
| 5 | #include "tegra114.dtsi" |
| 6 | |
| 7 | / { |
| 8 | model = "ASUS Transformer Pad TF701T"; |
| 9 | compatible = "asus,tf701t", "nvidia,tegra114"; |
| 10 | |
| 11 | chosen { |
| 12 | stdout-path = &uartd; |
| 13 | }; |
| 14 | |
| 15 | aliases { |
| 16 | i2c0 = &pwr_i2c; |
| 17 | |
| 18 | mmc0 = &sdmmc4; /* eMMC */ |
| 19 | mmc1 = &sdmmc3; /* uSD slot */ |
| 20 | |
| 21 | usb0 = &usb1; |
| 22 | usb1 = &usb3; /* Dock USB */ |
| 23 | }; |
| 24 | |
| 25 | memory { |
| 26 | device_type = "memory"; |
| 27 | reg = <0x80000000 0x80000000>; |
| 28 | }; |
| 29 | |
| 30 | host1x@50000000 { |
| 31 | dsia: dsi@54300000 { |
| 32 | status = "okay"; |
| 33 | |
| 34 | avdd-dsi-csi-supply = <&avdd_dsi_csi>; |
| 35 | nvidia,ganged-mode = <&dsib>; |
| 36 | |
| 37 | panel@0 { |
| 38 | compatible = "sharp,lq101r1sx01"; |
| 39 | reg = <0>; |
| 40 | |
| 41 | link2 = <&panel_secondary>; |
| 42 | |
| 43 | power-supply = <&dvdd_1v8_lcd>; |
| 44 | backlight = <&backlight>; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | dsib: dsi@54400000 { |
| 49 | clocks = <&tegra_car TEGRA114_CLK_DSIB>, |
| 50 | <&tegra_car TEGRA114_CLK_DSIBLP>, |
| 51 | <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; |
| 52 | clock-names = "dsi", "lp", "parent"; |
| 53 | status = "okay"; |
| 54 | |
| 55 | avdd-dsi-csi-supply = <&avdd_dsi_csi>; |
| 56 | |
| 57 | panel_secondary: panel@0 { |
| 58 | compatible = "sharp,lq101r1sx01"; |
| 59 | reg = <0>; |
| 60 | }; |
| 61 | }; |
| 62 | }; |
| 63 | |
| 64 | pinmux@70000868 { |
| 65 | pinctrl-names = "default"; |
| 66 | pinctrl-0 = <&state_default>; |
| 67 | |
| 68 | state_default: pinmux { |
| 69 | /* WLAN SDIO pinmux */ |
| 70 | sdmmc1-clk { |
| 71 | nvidia,pins = "sdmmc1_clk_pz0"; |
| 72 | nvidia,function = "sdmmc1"; |
| 73 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 74 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 75 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 76 | }; |
| 77 | sdmmc1-cmd { |
| 78 | nvidia,pins = "sdmmc1_cmd_pz1", |
| 79 | "sdmmc1_dat0_py7", |
| 80 | "sdmmc1_dat1_py6", |
| 81 | "sdmmc1_dat2_py5", |
| 82 | "sdmmc1_dat3_py4"; |
| 83 | nvidia,function = "sdmmc1"; |
| 84 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 85 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 86 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 87 | }; |
| 88 | wlan-power { |
| 89 | nvidia,pins = "clk2_req_pcc5"; |
| 90 | nvidia,function = "rsvd2"; |
| 91 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 92 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 93 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 94 | }; |
| 95 | wlan-reset { |
| 96 | nvidia,pins = "gpio_x7_aud_px7"; |
| 97 | nvidia,function = "rsvd1"; |
| 98 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 99 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 100 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 101 | }; |
| 102 | wlan-host-wake { |
| 103 | nvidia,pins = "pu5"; |
| 104 | nvidia,function = "pwm2"; |
| 105 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 106 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 107 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 108 | }; |
| 109 | wlan-3v3-com { |
| 110 | nvidia,pins = "pu1"; |
| 111 | nvidia,function = "rsvd1"; |
| 112 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 113 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 114 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 115 | }; |
| 116 | |
| 117 | /* UART-A pinmux */ |
| 118 | uarta-cts { |
| 119 | nvidia,pins = "kb_row10_ps2"; |
| 120 | nvidia,function = "uarta"; |
| 121 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 122 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 123 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 124 | }; |
| 125 | uarta-rts { |
| 126 | nvidia,pins = "kb_row9_ps1"; |
| 127 | nvidia,function = "uarta"; |
| 128 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 129 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 130 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 131 | }; |
| 132 | |
| 133 | /* GNSS UART-B pinmux */ |
| 134 | uartb-cts { |
| 135 | nvidia,pins = "uart2_cts_n_pj5"; |
| 136 | nvidia,function = "uartb"; |
| 137 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 138 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 139 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 140 | }; |
| 141 | uartb-rts { |
| 142 | nvidia,pins = "uart2_rts_n_pj6"; |
| 143 | nvidia,function = "uartb"; |
| 144 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 145 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 146 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 147 | }; |
| 148 | uartb-rxd { |
| 149 | nvidia,pins = "uart2_rxd_pc3"; |
| 150 | nvidia,function = "irda"; |
| 151 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 152 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 153 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 154 | }; |
| 155 | uartb-txd { |
| 156 | nvidia,pins = "uart2_txd_pc2"; |
| 157 | nvidia,function = "irda"; |
| 158 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 159 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 160 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 161 | }; |
| 162 | |
| 163 | /* Bluetooth UART-C pinmux */ |
| 164 | uartc-cts-rxd { |
| 165 | nvidia,pins = "uart3_cts_n_pa1", |
| 166 | "uart3_rxd_pw7"; |
| 167 | nvidia,function = "uartc"; |
| 168 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 171 | }; |
| 172 | uartc-rts-txd { |
| 173 | nvidia,pins = "uart3_rts_n_pc0", |
| 174 | "uart3_txd_pw6"; |
| 175 | nvidia,function = "uartc"; |
| 176 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 178 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 179 | }; |
| 180 | bt-shutdown { |
| 181 | nvidia,pins = "kb_col6_pq6", |
| 182 | "kb_col7_pq7"; |
| 183 | nvidia,function = "rsvd2"; |
| 184 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 185 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 186 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 187 | }; |
| 188 | bt-dev-wake { |
| 189 | nvidia,pins = "clk3_req_pee1"; |
| 190 | nvidia,function = "rsvd2"; |
| 191 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 192 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 193 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 194 | }; |
| 195 | bt-host-wake { |
| 196 | nvidia,pins = "pu6"; |
| 197 | nvidia,function = "pwm3"; |
| 198 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 199 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 200 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 201 | }; |
| 202 | bt-pcm-dap4-out { |
| 203 | nvidia,pins = "dap4_fs_pp4", |
| 204 | "dap4_dout_pp6", |
| 205 | "dap4_sclk_pp7"; |
| 206 | nvidia,function = "i2s3"; |
| 207 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 208 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 209 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 210 | }; |
| 211 | bt-pcm-dap4-in { |
| 212 | nvidia,pins = "dap4_din_pp5"; |
| 213 | nvidia,function = "i2s3"; |
| 214 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 215 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 216 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 217 | }; |
| 218 | |
| 219 | /* UART-D pinmux */ |
| 220 | uartd-cts { |
| 221 | nvidia,pins = "gmi_a17_pb0"; |
| 222 | nvidia,function = "uartd"; |
| 223 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 224 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 225 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 226 | }; |
| 227 | uartd-rts { |
| 228 | nvidia,pins = "gmi_a16_pj7", |
| 229 | "gmi_a19_pk7"; |
| 230 | nvidia,function = "uartd"; |
| 231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 232 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 233 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 234 | }; |
| 235 | |
| 236 | /* MicroSD pinmux */ |
| 237 | sdmmc3-clk { |
| 238 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 239 | nvidia,function = "sdmmc3"; |
| 240 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 241 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 242 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 243 | }; |
| 244 | sdmmc3-data { |
| 245 | nvidia,pins = "sdmmc3_cmd_pa7", |
| 246 | "sdmmc3_dat0_pb7", |
| 247 | "sdmmc3_dat1_pb6", |
| 248 | "sdmmc3_dat2_pb5", |
| 249 | "sdmmc3_dat3_pb4", |
| 250 | "kb_col4_pq4", |
| 251 | "sdmmc3_cd_n_pv2", |
| 252 | "sdmmc3_clk_lb_out_pee4", |
| 253 | "sdmmc3_clk_lb_in_pee5"; |
| 254 | nvidia,function = "sdmmc3"; |
| 255 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 256 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 257 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 258 | }; |
| 259 | microsd-pwr { |
| 260 | nvidia,pins = "gmi_clk_pk1"; |
| 261 | nvidia,function = "gmi"; |
| 262 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 263 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 264 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 265 | }; |
| 266 | |
| 267 | /* EMMC pinmux */ |
| 268 | sdmmc4-clk-cmd { |
| 269 | nvidia,pins = "sdmmc4_clk_pcc4"; |
| 270 | nvidia,function = "sdmmc4"; |
| 271 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 272 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 273 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 274 | }; |
| 275 | sdmmc4-data { |
| 276 | nvidia,pins = "sdmmc4_cmd_pt7", |
| 277 | "sdmmc4_dat0_paa0", |
| 278 | "sdmmc4_dat1_paa1", |
| 279 | "sdmmc4_dat2_paa2", |
| 280 | "sdmmc4_dat3_paa3", |
| 281 | "sdmmc4_dat4_paa4", |
| 282 | "sdmmc4_dat5_paa5", |
| 283 | "sdmmc4_dat6_paa6", |
| 284 | "sdmmc4_dat7_paa7"; |
| 285 | nvidia,function = "sdmmc4"; |
| 286 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 288 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 289 | }; |
| 290 | |
| 291 | /* I2C pinmux */ |
| 292 | gen1-i2c { |
| 293 | nvidia,pins = "gen1_i2c_scl_pc4", |
| 294 | "gen1_i2c_sda_pc5"; |
| 295 | nvidia,function = "i2c1"; |
| 296 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 297 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 298 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 299 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 300 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 301 | }; |
| 302 | gen2-i2c { |
| 303 | nvidia,pins = "gen2_i2c_scl_pt5", |
| 304 | "gen2_i2c_sda_pt6"; |
| 305 | nvidia,function = "i2c2"; |
| 306 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 307 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 308 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 309 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 310 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 311 | }; |
| 312 | cam-i2c { |
| 313 | nvidia,pins = "cam_i2c_scl_pbb1", |
| 314 | "cam_i2c_sda_pbb2"; |
| 315 | nvidia,function = "i2c3"; |
| 316 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 317 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 318 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 319 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 320 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 321 | }; |
| 322 | ddc-i2c { |
| 323 | nvidia,pins = "ddc_scl_pv4", |
| 324 | "ddc_sda_pv5"; |
| 325 | nvidia,function = "i2c4"; |
| 326 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 327 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 328 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 329 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 330 | }; |
| 331 | pwr-i2c { |
| 332 | nvidia,pins = "pwr_i2c_scl_pz6", |
| 333 | "pwr_i2c_sda_pz7"; |
| 334 | nvidia,function = "i2cpwr"; |
| 335 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 336 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 337 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 338 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 339 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 340 | }; |
| 341 | |
| 342 | /* SPI pinmux */ |
| 343 | spi1-out { |
| 344 | nvidia,pins = "ulpi_clk_py0", |
| 345 | "ulpi_nxt_py2", |
| 346 | "ulpi_stp_py3"; |
| 347 | nvidia,function = "spi1"; |
| 348 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 349 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 350 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 351 | }; |
| 352 | spi1-in { |
| 353 | nvidia,pins = "ulpi_dir_py1"; |
| 354 | nvidia,function = "spi1"; |
| 355 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 356 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 357 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 358 | }; |
| 359 | spi2 { |
| 360 | nvidia,pins = "ulpi_data4_po5", |
| 361 | "ulpi_data7_po0"; |
| 362 | nvidia,function = "spi2"; |
| 363 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 364 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 365 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 366 | }; |
| 367 | spi4-out { |
| 368 | nvidia,pins = "gmi_ad6_pg6", |
| 369 | "gmi_wr_n_pi0"; |
| 370 | nvidia,function = "spi4"; |
| 371 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 372 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 373 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 374 | }; |
| 375 | spi4-in { |
| 376 | nvidia,pins = "gmi_ad5_pg5", |
| 377 | "gmi_ad7_pg7"; |
| 378 | nvidia,function = "spi4"; |
| 379 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 380 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 381 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 382 | }; |
| 383 | |
| 384 | /* GPIO keys pinmux */ |
| 385 | hall-switch { |
| 386 | nvidia,pins = "ulpi_data4_po5"; |
| 387 | nvidia,function = "spi2"; |
| 388 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 389 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 390 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 391 | }; |
| 392 | lineout-switch { |
| 393 | nvidia,pins = "gpio_x5_aud_px5"; |
| 394 | nvidia,function = "rsvd1"; |
| 395 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 396 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 397 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 398 | }; |
| 399 | power-key { |
| 400 | nvidia,pins = "kb_col0_pq0"; |
| 401 | nvidia,function = "kbc"; |
| 402 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 403 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 404 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 405 | }; |
| 406 | volume-keys { |
| 407 | nvidia,pins = "kb_row1_pr1", |
| 408 | "kb_row2_pr2"; |
| 409 | nvidia,function = "rsvd2"; |
| 410 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 411 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 412 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 413 | }; |
| 414 | |
| 415 | /* Sensors pinmux */ |
| 416 | nct-irq { |
| 417 | nvidia,pins = "ulpi_data3_po4"; |
| 418 | nvidia,function = "ulpi"; |
| 419 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 420 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 421 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 422 | }; |
| 423 | mpu-irq { |
| 424 | nvidia,pins = "kb_row3_pr3"; |
| 425 | nvidia,function = "rsvd3"; |
| 426 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 427 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 428 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 429 | }; |
| 430 | |
| 431 | /* HDMI pinmux */ |
| 432 | hdmi-hpd { |
| 433 | nvidia,pins = "hdmi_int_pn7"; |
| 434 | nvidia,function = "rsvd1"; |
| 435 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 436 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 437 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 438 | }; |
| 439 | hdmi-en { |
| 440 | nvidia,pins = "dap3_dout_pp2"; |
| 441 | nvidia,function = "i2s2"; |
| 442 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 444 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 445 | }; |
| 446 | hdmi-cec { |
| 447 | nvidia,pins = "hdmi_cec_pee3"; |
| 448 | nvidia,function = "cec"; |
| 449 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 450 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 451 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 452 | }; |
| 453 | |
| 454 | /* LED pinmux */ |
| 455 | backlight-pwm { |
| 456 | nvidia,pins = "gmi_ad9_ph1"; |
| 457 | nvidia,function = "pwm1"; |
| 458 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 459 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 460 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 461 | }; |
| 462 | backlight-en { |
| 463 | nvidia,pins = "gmi_ad10_ph2"; |
| 464 | nvidia,function = "gmi"; |
| 465 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 466 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 467 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 468 | }; |
| 469 | |
| 470 | /* Touchscreen pinmux */ |
| 471 | touch-irq { |
| 472 | nvidia,pins = "gmi_cs4_n_pk2"; |
| 473 | nvidia,function = "gmi"; |
| 474 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 475 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 476 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 477 | }; |
| 478 | touch-rst { |
| 479 | nvidia,pins = "gmi_cs3_n_pk4"; |
| 480 | nvidia,function = "gmi"; |
| 481 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 482 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 483 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 484 | }; |
| 485 | touch-pwr { |
| 486 | nvidia,pins = "gmi_ad8_ph0"; |
| 487 | nvidia,function = "gmi"; |
| 488 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 489 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 490 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 491 | }; |
| 492 | touch-vio { |
| 493 | nvidia,pins = "gmi_ad12_ph4"; |
| 494 | nvidia,function = "rsvd4"; |
| 495 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 496 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 497 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 498 | }; |
| 499 | |
| 500 | /* AUDIO pinmux */ |
| 501 | audio-ldo1 { |
| 502 | nvidia,pins = "sdmmc1_wp_n_pv3"; |
| 503 | nvidia,function = "sdmmc1"; |
| 504 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 505 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 506 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 507 | }; |
| 508 | hp-detect { |
| 509 | nvidia,pins = "kb_row7_pr7"; |
| 510 | nvidia,function = "rsvd2"; |
| 511 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 512 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 513 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 514 | }; |
| 515 | dap-i2s0-in { |
| 516 | nvidia,pins = "dap1_din_pn1"; |
| 517 | nvidia,function = "i2s0"; |
| 518 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 519 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 520 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 521 | }; |
| 522 | dap-i2s0-out { |
| 523 | nvidia,pins = "dap1_dout_pn2", |
| 524 | "dap1_fs_pn0", |
| 525 | "dap1_sclk_pn3"; |
| 526 | nvidia,function = "i2s0"; |
| 527 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 528 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 529 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 530 | }; |
| 531 | dap-i2s1-in { |
| 532 | nvidia,pins = "dap2_din_pa4"; |
| 533 | nvidia,function = "i2s1"; |
| 534 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 535 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 536 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 537 | }; |
| 538 | dap-i2s1-out { |
| 539 | nvidia,pins = "dap2_dout_pa5", |
| 540 | "dap2_fs_pa2", |
| 541 | "dap2_sclk_pa3"; |
| 542 | nvidia,function = "i2s1"; |
| 543 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 544 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 545 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 546 | }; |
| 547 | dap-i2s2-in { |
| 548 | nvidia,pins = "dap3_fs_pp0", |
| 549 | "dap3_sclk_pp3"; |
| 550 | nvidia,function = "i2s2"; |
| 551 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 552 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 553 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 554 | }; |
| 555 | dap-i2s2-out { |
| 556 | nvidia,pins = "dap3_din_pp1"; |
| 557 | nvidia,function = "i2s2"; |
| 558 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 559 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 560 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 561 | }; |
| 562 | spdif-in { |
| 563 | nvidia,pins = "spdif_in_pk6"; |
| 564 | nvidia,function = "rsvd3"; |
| 565 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 566 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 567 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 568 | }; |
| 569 | spdif-out { |
| 570 | nvidia,pins = "spdif_out_pk5"; |
| 571 | nvidia,function = "rsvd2"; |
| 572 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 573 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 574 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 575 | }; |
| 576 | |
| 577 | /* AsusEC pinmux */ |
| 578 | ec-irq { |
| 579 | nvidia,pins = "kb_col5_pq5"; |
| 580 | nvidia,function = "kbc"; |
| 581 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 582 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 583 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 584 | }; |
| 585 | ec-req { |
| 586 | nvidia,pins = "kb_col2_pq2"; |
| 587 | nvidia,function = "kbc"; |
| 588 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 589 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 590 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 591 | }; |
| 592 | hotplug-i2c { |
| 593 | nvidia,pins = "ulpi_data7_po0"; |
| 594 | nvidia,function = "spi2"; |
| 595 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 596 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 597 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 598 | }; |
| 599 | ps2-irq { |
| 600 | nvidia,pins = "gpio_w2_aud_pw2"; |
| 601 | nvidia,function = "spi6"; |
| 602 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 603 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 604 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 605 | }; |
| 606 | kbd-irq { |
| 607 | nvidia,pins = "gmi_cs0_n_pj0"; |
| 608 | nvidia,function = "rsvd1"; |
| 609 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 610 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 611 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 612 | }; |
| 613 | |
| 614 | dvfs-pin { |
| 615 | nvidia,pins = "dvfs_pwm_px0", |
| 616 | "dvfs_clk_px2"; |
| 617 | nvidia,function = "cldvfs"; |
| 618 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 619 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 620 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 621 | }; |
| 622 | |
| 623 | /* Core pinmux */ |
| 624 | clk-32k-out { |
| 625 | nvidia,pins = "clk_32k_out_pa0"; |
| 626 | nvidia,function = "soc"; |
| 627 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 628 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 629 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 630 | }; |
| 631 | sys-clk-req { |
| 632 | nvidia,pins = "sys_clk_req_pz5"; |
| 633 | nvidia,function = "sysclk"; |
| 634 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 635 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 636 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 637 | }; |
| 638 | core-pwr-req { |
| 639 | nvidia,pins = "core_pwr_req"; |
| 640 | nvidia,function = "pwron"; |
| 641 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 642 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 643 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 644 | }; |
| 645 | cpu-pwr-req { |
| 646 | nvidia,pins = "cpu_pwr_req"; |
| 647 | nvidia,function = "cpu"; |
| 648 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 649 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 650 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 651 | }; |
| 652 | pwr-int-n { |
| 653 | nvidia,pins = "pwr_int_n"; |
| 654 | nvidia,function = "pmi"; |
| 655 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 656 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 657 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 658 | }; |
| 659 | clk-32k-in { |
| 660 | nvidia,pins = "clk_32k_in"; |
| 661 | nvidia,function = "clk"; |
| 662 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 663 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 664 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 665 | }; |
| 666 | owr { |
| 667 | nvidia,pins = "owr"; |
| 668 | nvidia,function = "rsvd2"; |
| 669 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 670 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 671 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 672 | }; |
| 673 | reset-out-n { |
| 674 | nvidia,pins = "reset_out_n"; |
| 675 | nvidia,function = "reset_out_n"; |
| 676 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 677 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 678 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 679 | }; |
| 680 | |
| 681 | /* ULPI pinmux */ |
| 682 | ulpi-data0-6 { |
| 683 | nvidia,pins = "ulpi_data0_po1", |
| 684 | "ulpi_data6_po7"; |
| 685 | nvidia,function = "ulpi"; |
| 686 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 687 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 688 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 689 | }; |
| 690 | ulpi-data1-5 { |
| 691 | nvidia,pins = "ulpi_data1_po2", |
| 692 | "ulpi_data5_po6"; |
| 693 | nvidia,function = "ulpi"; |
| 694 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 695 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 696 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 697 | }; |
| 698 | ulpi-data2-3 { |
| 699 | nvidia,pins = "ulpi_data2_po3", |
| 700 | "ulpi_data3_po4"; |
| 701 | nvidia,function = "ulpi"; |
| 702 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 703 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 704 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 705 | }; |
| 706 | |
| 707 | /* PORT V */ |
| 708 | pv0-gpio { |
| 709 | nvidia,pins = "pv0"; |
| 710 | nvidia,function = "rsvd2"; |
| 711 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 712 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 713 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 714 | }; |
| 715 | pv1-gpio { |
| 716 | nvidia,pins = "pv1"; |
| 717 | nvidia,function = "rsvd1"; |
| 718 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 719 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 720 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 721 | }; |
| 722 | |
| 723 | /* PORT U */ |
| 724 | pu0-gpio { |
| 725 | nvidia,pins = "pu0"; |
| 726 | nvidia,function = "rsvd3"; |
| 727 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 728 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 729 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 730 | }; |
| 731 | pu2-gpio { |
| 732 | nvidia,pins = "pu2"; |
| 733 | nvidia,function = "rsvd1"; |
| 734 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 735 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 736 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 737 | }; |
| 738 | |
| 739 | /* PWM pinmux */ |
| 740 | pwm0 { |
| 741 | nvidia,pins = "pu3"; |
| 742 | nvidia,function = "pwm0"; |
| 743 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 744 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 745 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 746 | }; |
| 747 | pwm1 { |
| 748 | nvidia,pins = "pu4"; |
| 749 | nvidia,function = "pwm1"; |
| 750 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 751 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 752 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 753 | }; |
| 754 | |
| 755 | /* EXTPERIPH pinmux */ |
| 756 | clk1-out { |
| 757 | nvidia,pins = "clk1_out_pw4"; |
| 758 | nvidia,function = "extperiph1"; |
| 759 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 760 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 761 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 762 | }; |
| 763 | clk2-out { |
| 764 | nvidia,pins = "clk2_out_pw5"; |
| 765 | nvidia,function = "extperiph2"; |
| 766 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 767 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 768 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 769 | }; |
| 770 | clk3-out { |
| 771 | nvidia,pins = "clk3_out_pee0"; |
| 772 | nvidia,function = "extperiph3"; |
| 773 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 774 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 775 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 776 | }; |
| 777 | clk1-req { |
| 778 | nvidia,pins = "clk1_req_pee2"; |
| 779 | nvidia,function = "rsvd3"; |
| 780 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 781 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 782 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 783 | }; |
| 784 | |
| 785 | /* GMI pinmux */ |
| 786 | gmi-wp-n { |
| 787 | nvidia,pins = "gmi_wp_n_pc7"; |
| 788 | nvidia,function = "rsvd1"; |
| 789 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 790 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 791 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 792 | }; |
| 793 | gmi-adv { |
| 794 | nvidia,pins = "gmi_adv_n_pk0"; |
| 795 | nvidia,function = "rsvd1"; |
| 796 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 797 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 798 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 799 | }; |
| 800 | gmi-ad0-ad1 { |
| 801 | nvidia,pins = "gmi_ad0_pg0", |
| 802 | "gmi_ad1_pg1"; |
| 803 | nvidia,function = "rsvd1"; |
| 804 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 805 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 806 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 807 | }; |
| 808 | gmi-ad2-ad3 { |
| 809 | nvidia,pins = "gmi_ad2_pg2", |
| 810 | "gmi_ad3_pg3"; |
| 811 | nvidia,function = "rsvd1"; |
| 812 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 813 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 814 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 815 | }; |
| 816 | gmi-iordy { |
| 817 | nvidia,pins = "gmi_iordy_pi5"; |
| 818 | nvidia,function = "rsvd2"; |
| 819 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 820 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 821 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 822 | }; |
| 823 | gmi-a18 { |
| 824 | nvidia,pins = "gmi_a18_pb1"; |
| 825 | nvidia,function = "rsvd2"; |
| 826 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 827 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 828 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 829 | }; |
| 830 | gmi-wait { |
| 831 | nvidia,pins = "gmi_wait_pi7"; |
| 832 | nvidia,function = "nand"; |
| 833 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 834 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 835 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 836 | }; |
| 837 | gmi-cs6-n { |
| 838 | nvidia,pins = "gmi_cs6_n_pi3"; |
| 839 | nvidia,function = "nand"; |
| 840 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 841 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 842 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 843 | }; |
| 844 | gmi-cs7-n { |
| 845 | nvidia,pins = "gmi_cs7_n_pi6"; |
| 846 | nvidia,function = "nand"; |
| 847 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 848 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 849 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 850 | }; |
| 851 | gmi-dqs-p { |
| 852 | nvidia,pins = "gmi_dqs_p_pj3"; |
| 853 | nvidia,function = "nand"; |
| 854 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 855 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 856 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 857 | }; |
| 858 | gmi-cs2-ad { |
| 859 | nvidia,pins = "gmi_cs2_n_pk3", |
| 860 | "gmi_ad14_ph6", |
| 861 | "gmi_ad15_ph7"; |
| 862 | nvidia,function = "gmi"; |
| 863 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 864 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 865 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 866 | }; |
| 867 | gmi-cs4-clk { |
| 868 | nvidia,pins = "gmi_cs4_n_pk2", |
| 869 | "gmi_clk_lb"; |
| 870 | nvidia,function = "gmi"; |
| 871 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 872 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 873 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 874 | }; |
| 875 | gmi-ad11 { |
| 876 | nvidia,pins = "gmi_ad11_ph3"; |
| 877 | nvidia,function = "gmi"; |
| 878 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 879 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 880 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 881 | }; |
| 882 | gmi-cs1-oe { |
| 883 | nvidia,pins = "gmi_cs1_n_pj2", |
| 884 | "gmi_oe_n_pi1"; |
| 885 | nvidia,function = "soc"; |
| 886 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 887 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 888 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 889 | }; |
| 890 | gmi-ad4 { |
| 891 | nvidia,pins = "gmi_ad4_pg4"; |
| 892 | nvidia,function = "rsvd4"; |
| 893 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 894 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 895 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 896 | }; |
| 897 | gmi-ad13 { |
| 898 | nvidia,pins = "gmi_ad13_ph5"; |
| 899 | nvidia,function = "rsvd4"; |
| 900 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 901 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 902 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 903 | }; |
| 904 | gmi-rst-n { |
| 905 | nvidia,pins = "gmi_rst_n_pi4"; |
| 906 | nvidia,function = "rsvd4"; |
| 907 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 908 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 909 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 910 | }; |
| 911 | |
| 912 | /* PORT CC */ |
| 913 | pcc-gpio { |
| 914 | nvidia,pins = "pcc1", "pcc2"; |
| 915 | nvidia,function = "rsvd2"; |
| 916 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 917 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 918 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 919 | }; |
| 920 | |
| 921 | /* PORT BB */ |
| 922 | pbb3-gpio { |
| 923 | nvidia,pins = "pbb3"; |
| 924 | nvidia,function = "rsvd4"; |
| 925 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 926 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 927 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 928 | }; |
| 929 | pbb4-5-6-gpio { |
| 930 | nvidia,pins = "pbb4", "pbb5", "pbb6"; |
| 931 | nvidia,function = "rsvd4"; |
| 932 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 933 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 934 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 935 | }; |
| 936 | pbb7-gpio { |
| 937 | nvidia,pins = "pbb7"; |
| 938 | nvidia,function = "rsvd2"; |
| 939 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 940 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 941 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 942 | }; |
| 943 | |
| 944 | /* KBC pinmux */ |
| 945 | kb-r0-c1 { |
| 946 | nvidia,pins = "kb_row0_pr0", |
| 947 | "kb_col1_pq1"; |
| 948 | nvidia,function = "rsvd2"; |
| 949 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 950 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 951 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 952 | }; |
| 953 | kb-row4 { |
| 954 | nvidia,pins = "kb_row4_pr4"; |
| 955 | nvidia,function = "kbc"; |
| 956 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 957 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 958 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 959 | }; |
| 960 | kb-row5 { |
| 961 | nvidia,pins = "kb_row5_pr5"; |
| 962 | nvidia,function = "kbc"; |
| 963 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 964 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 965 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 966 | }; |
| 967 | kb-row6 { |
| 968 | nvidia,pins = "kb_row6_pr6"; |
| 969 | nvidia,function = "kbc"; |
| 970 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 971 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 972 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 973 | }; |
| 974 | kb-r8-c3 { |
| 975 | nvidia,pins = "kb_row8_ps0", |
| 976 | "kb_col3_pq3"; |
| 977 | nvidia,function = "kbc"; |
| 978 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 979 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 980 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 981 | }; |
| 982 | |
| 983 | /* VI pinmux */ |
| 984 | cam-mclk { |
| 985 | nvidia,pins = "cam_mclk_pcc0", |
| 986 | "pbb0"; |
| 987 | nvidia,function = "vi_alt3"; |
| 988 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 989 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 990 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 991 | }; |
| 992 | |
| 993 | /* AUD pinmux */ |
| 994 | gpio-x4-aud { |
| 995 | nvidia,pins = "gpio_x4_aud_px4"; |
| 996 | nvidia,function = "rsvd1"; |
| 997 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 998 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 999 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1000 | }; |
| 1001 | gpio-x1-aud { |
| 1002 | nvidia,pins = "gpio_x1_aud_px1"; |
| 1003 | nvidia,function = "rsvd2"; |
| 1004 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1005 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1006 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1007 | }; |
| 1008 | gpio-x3-aud { |
| 1009 | nvidia,pins = "gpio_x3_aud_px3"; |
| 1010 | nvidia,function = "rsvd3"; |
| 1011 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1012 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1013 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1014 | }; |
| 1015 | gpio-x6-aud { |
| 1016 | nvidia,pins = "gpio_x6_aud_px6"; |
| 1017 | nvidia,function = "rsvd4"; |
| 1018 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1019 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1020 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1021 | }; |
| 1022 | |
| 1023 | usb-vbus { |
| 1024 | nvidia,pins = "usb_vbus_en0_pn4", |
| 1025 | "usb_vbus_en1_pn5"; |
| 1026 | nvidia,function = "rsvd2"; |
| 1027 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1028 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1029 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1030 | }; |
| 1031 | |
| 1032 | /* GPIO power/drive control */ |
| 1033 | drive-sdio1 { |
| 1034 | nvidia,pins = "drive_sdio1"; |
| 1035 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 1036 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 1037 | nvidia,pull-down-strength = <36>; |
| 1038 | nvidia,pull-up-strength = <20>; |
| 1039 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; |
| 1040 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; |
| 1041 | }; |
| 1042 | drive-sdio3 { |
| 1043 | nvidia,pins = "drive_sdio3"; |
| 1044 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 1045 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 1046 | nvidia,pull-down-strength = <22>; |
| 1047 | nvidia,pull-up-strength = <36>; |
| 1048 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1049 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1050 | }; |
| 1051 | drive-gma { |
| 1052 | nvidia,pins = "drive_gma"; |
| 1053 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 1054 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 1055 | nvidia,pull-down-strength = <2>; |
| 1056 | nvidia,pull-up-strength = <2>; |
| 1057 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1058 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1059 | }; |
| 1060 | }; |
| 1061 | }; |
| 1062 | |
| 1063 | uartd: serial@70006300 { |
| 1064 | status = "okay"; |
| 1065 | }; |
| 1066 | |
| 1067 | pwm: pwm@7000a000 { |
| 1068 | status = "okay"; |
| 1069 | }; |
| 1070 | |
| 1071 | pwr_i2c: i2c@7000d000 { |
| 1072 | status = "okay"; |
| 1073 | clock-frequency = <400000>; |
| 1074 | |
| 1075 | /* Texas Instruments TPS65913 PMIC */ |
| 1076 | pmic: tps65913@58 { |
| 1077 | compatible = "ti,tps65913"; |
| 1078 | reg = <0x58>; |
| 1079 | |
| 1080 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 1081 | #interrupt-cells = <2>; |
| 1082 | interrupt-controller; |
| 1083 | |
| 1084 | ti,system-power-controller; |
| 1085 | |
| 1086 | palmas_gpio: gpio { |
| 1087 | compatible = "ti,palmas-gpio"; |
| 1088 | gpio-controller; |
| 1089 | #gpio-cells = <2>; |
| 1090 | }; |
| 1091 | |
| 1092 | pinmux { |
| 1093 | compatible = "ti,tps65913-pinctrl"; |
| 1094 | ti,palmas-enable-dvfs1; |
| 1095 | |
| 1096 | pinctrl-names = "default"; |
| 1097 | pinctrl-0 = <&palmas_default>; |
| 1098 | |
| 1099 | palmas_default: pinmux { |
| 1100 | pin_gpio4 { |
| 1101 | pins = "gpio4"; |
| 1102 | function = "gpio"; |
| 1103 | }; |
| 1104 | }; |
| 1105 | }; |
| 1106 | |
| 1107 | pmic { |
| 1108 | compatible = "ti,tps65913-pmic"; |
| 1109 | |
| 1110 | regulators { |
| 1111 | vdd_1v8_vio: smps8 { |
| 1112 | regulator-name = "vdd_1v8_gen"; |
| 1113 | regulator-min-microvolt = <1800000>; |
| 1114 | regulator-max-microvolt = <1800000>; |
| 1115 | regulator-always-on; |
| 1116 | regulator-boot-on; |
| 1117 | }; |
| 1118 | |
| 1119 | vcore_emmc: smps9 { |
| 1120 | regulator-name = "vdd_sdmmc"; |
| 1121 | regulator-min-microvolt = <2900000>; |
| 1122 | regulator-max-microvolt = <2900000>; |
| 1123 | regulator-always-on; |
| 1124 | regulator-boot-on; |
| 1125 | }; |
| 1126 | |
| 1127 | avdd_dsi_csi: ldo2 { |
| 1128 | regulator-name = "avdd_dsi_csi"; |
| 1129 | regulator-min-microvolt = <1200000>; |
| 1130 | regulator-max-microvolt = <1200000>; |
| 1131 | regulator-boot-on; |
| 1132 | }; |
| 1133 | |
| 1134 | vddio_usd: ldo9 { |
| 1135 | regulator-name = "vddio_sdmmc"; |
| 1136 | regulator-min-microvolt = <2900000>; |
| 1137 | regulator-max-microvolt = <2900000>; |
| 1138 | regulator-always-on; |
| 1139 | regulator-boot-on; |
| 1140 | }; |
| 1141 | |
| 1142 | avdd_usb: ldousb { |
| 1143 | regulator-name = "vdd_usb"; |
| 1144 | regulator-min-microvolt = <3300000>; |
| 1145 | regulator-max-microvolt = <3300000>; |
| 1146 | regulator-always-on; |
| 1147 | regulator-boot-on; |
| 1148 | }; |
| 1149 | }; |
| 1150 | }; |
| 1151 | }; |
| 1152 | }; |
| 1153 | |
| 1154 | sdmmc3: sdhci@78000400 { |
| 1155 | status = "okay"; |
| 1156 | bus-width = <4>; |
| 1157 | |
| 1158 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 1159 | power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
| 1160 | |
| 1161 | nvidia,default-tap = <0x3>; |
| 1162 | nvidia,default-trim = <0x3>; |
| 1163 | |
| 1164 | vmmc-supply = <&vcore_emmc>; |
| 1165 | vqmmc-supply = <&vddio_usd>; |
| 1166 | }; |
| 1167 | |
| 1168 | sdmmc4: sdhci@78000600 { |
| 1169 | status = "okay"; |
| 1170 | bus-width = <8>; |
| 1171 | non-removable; |
| 1172 | |
| 1173 | vmmc-supply = <&vcore_emmc>; |
| 1174 | vqmmc-supply = <&vdd_1v8_vio>; |
| 1175 | }; |
| 1176 | |
| 1177 | /* USB via ASUS connector */ |
| 1178 | usb1: usb@7d000000 { |
| 1179 | status = "okay"; |
| 1180 | dr_mode = "otg"; |
| 1181 | }; |
| 1182 | |
| 1183 | /* Dock's USB port */ |
| 1184 | usb3: usb@7d008000 { |
| 1185 | status = "okay"; |
| 1186 | }; |
| 1187 | |
| 1188 | backlight: backlight { |
| 1189 | compatible = "pwm-backlight"; |
| 1190 | |
| 1191 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| 1192 | pwms = <&pwm 1 1000000>; |
| 1193 | |
| 1194 | brightness-levels = <1 35 70 105 140 175 210 255>; |
| 1195 | default-brightness-level = <5>; |
| 1196 | }; |
| 1197 | |
| 1198 | clk32k_in: clock-32k { |
| 1199 | compatible = "fixed-clock"; |
| 1200 | #clock-cells = <0>; |
| 1201 | clock-frequency = <32768>; |
| 1202 | clock-output-names = "ref-oscillator"; |
| 1203 | }; |
| 1204 | |
| 1205 | extcon-keys { |
| 1206 | compatible = "gpio-keys"; |
| 1207 | |
| 1208 | switch-hall-sensor { |
| 1209 | label = "Hall Sensor"; |
| 1210 | gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; |
| 1211 | linux,code = <SW_LID>; |
| 1212 | }; |
| 1213 | }; |
| 1214 | |
| 1215 | gpio-keys { |
| 1216 | compatible = "gpio-keys"; |
| 1217 | |
| 1218 | key-power { |
| 1219 | label = "Power"; |
| 1220 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; |
| 1221 | linux,code = <KEY_ENTER>; |
| 1222 | }; |
| 1223 | |
| 1224 | key-volume-down { |
| 1225 | label = "Volume Down"; |
| 1226 | gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; |
| 1227 | linux,code = <KEY_DOWN>; |
| 1228 | }; |
| 1229 | |
| 1230 | key-volume-up { |
| 1231 | label = "Volume Up"; |
| 1232 | gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; |
| 1233 | linux,code = <KEY_UP>; |
| 1234 | }; |
| 1235 | }; |
| 1236 | |
| 1237 | dvdd_1v8_lcd: regulator-lcdvio { |
| 1238 | compatible = "regulator-fixed"; |
| 1239 | regulator-name = "dvdd_lcd"; |
| 1240 | regulator-min-microvolt = <1800000>; |
| 1241 | regulator-max-microvolt = <1800000>; |
| 1242 | gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; |
| 1243 | enable-active-high; |
| 1244 | }; |
| 1245 | }; |