| Jonas Karlman | ea80bf3 | 2025-04-07 22:46:51 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | |
| 3 | #include "rockchip-u-boot.dtsi" |
| 4 | |
| 5 | / { |
| 6 | aliases { |
| 7 | mmc0 = &sdhci; |
| 8 | mmc1 = &sdmmc; |
| 9 | }; |
| 10 | |
| 11 | chosen { |
| 12 | u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; |
| 13 | }; |
| 14 | |
| 15 | dmc { |
| 16 | compatible = "rockchip,rk3528-dmc"; |
| 17 | bootph-all; |
| 18 | }; |
| 19 | |
| 20 | soc { |
| 21 | rng: rng@ffc50000 { |
| 22 | compatible = "rockchip,rkrng"; |
| 23 | reg = <0x0 0xffc50000 0x0 0x200>; |
| 24 | }; |
| 25 | |
| 26 | otp: nvmem@ffce0000 { |
| 27 | compatible = "rockchip,rk3528-otp"; |
| 28 | reg = <0x0 0xffce0000 0x0 0x4000>; |
| 29 | }; |
| 30 | |
| 31 | sdmmc: mmc@ffc30000 { |
| 32 | compatible = "rockchip,rk3528-dw-mshc", |
| 33 | "rockchip,rk3288-dw-mshc"; |
| 34 | reg = <0x0 0xffc30000 0x0 0x4000>; |
| 35 | clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; |
| 36 | clock-names = "biu", "ciu"; |
| 37 | fifo-depth = <0x100>; |
| 38 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| 39 | max-frequency = <150000000>; |
| 40 | pinctrl-names = "default"; |
| 41 | pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, |
| 42 | <&sdmmc_det>; |
| 43 | resets = <&cru SRST_H_SDMMC0>; |
| 44 | reset-names = "reset"; |
| 45 | rockchip,default-sample-phase = <90>; |
| 46 | status = "disabled"; |
| 47 | }; |
| 48 | }; |
| 49 | }; |
| 50 | |
| 51 | &cru { |
| 52 | bootph-all; |
| 53 | }; |
| 54 | |
| 55 | &emmc_bus8 { |
| 56 | bootph-pre-ram; |
| 57 | bootph-some-ram; |
| 58 | }; |
| 59 | |
| 60 | &emmc_clk { |
| 61 | bootph-pre-ram; |
| 62 | bootph-some-ram; |
| 63 | }; |
| 64 | |
| 65 | &emmc_cmd { |
| 66 | bootph-pre-ram; |
| 67 | bootph-some-ram; |
| 68 | }; |
| 69 | |
| 70 | &emmc_strb { |
| 71 | bootph-pre-ram; |
| 72 | bootph-some-ram; |
| 73 | }; |
| 74 | |
| 75 | &gmac0_clk { |
| 76 | bootph-all; |
| 77 | }; |
| 78 | |
| 79 | &ioc_grf { |
| 80 | bootph-all; |
| 81 | }; |
| 82 | |
| 83 | &otp { |
| 84 | bootph-some-ram; |
| 85 | }; |
| 86 | |
| 87 | &pcfg_pull_none { |
| 88 | bootph-all; |
| 89 | }; |
| 90 | |
| 91 | &pcfg_pull_up { |
| 92 | bootph-all; |
| 93 | }; |
| 94 | |
| 95 | &pcfg_pull_up_drv_level_2 { |
| 96 | bootph-pre-ram; |
| 97 | bootph-some-ram; |
| 98 | }; |
| 99 | |
| 100 | &pinctrl { |
| 101 | bootph-all; |
| 102 | }; |
| 103 | |
| 104 | &sdhci { |
| 105 | bootph-pre-ram; |
| 106 | bootph-some-ram; |
| 107 | u-boot,spl-fifo-mode; |
| 108 | }; |
| 109 | |
| 110 | &sdmmc { |
| 111 | bootph-pre-ram; |
| 112 | bootph-some-ram; |
| 113 | u-boot,spl-fifo-mode; |
| 114 | }; |
| 115 | |
| 116 | &sdmmc_bus4 { |
| 117 | bootph-pre-ram; |
| 118 | bootph-some-ram; |
| 119 | }; |
| 120 | |
| 121 | &sdmmc_clk { |
| 122 | bootph-pre-ram; |
| 123 | bootph-some-ram; |
| 124 | }; |
| 125 | |
| 126 | &sdmmc_cmd { |
| 127 | bootph-pre-ram; |
| 128 | bootph-some-ram; |
| 129 | }; |
| 130 | |
| 131 | &sdmmc_det { |
| 132 | bootph-pre-ram; |
| 133 | bootph-some-ram; |
| 134 | }; |
| 135 | |
| 136 | &uart0 { |
| 137 | bootph-all; |
| 138 | clock-frequency = <24000000>; |
| 139 | }; |
| 140 | |
| 141 | &uart0m0_xfer { |
| 142 | bootph-pre-sram; |
| 143 | bootph-pre-ram; |
| 144 | }; |
| 145 | |
| 146 | &xin24m { |
| 147 | bootph-all; |
| 148 | }; |