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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / dts / rk3399-gru-u-boot.dtsi
blob: dfc7be4c621e712cc665e889b9c54d192924827a [file] [log] [blame]
Jagan Teki46dbd402019-05-07 23:51:52 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
4 */
5
6#include "rk3399-u-boot.dtsi"
Simon Glass8251e032020-07-19 13:55:58 -0600[diff] [blame]7
Simon Glasscc3f4352021-12-24 16:43:44 +0300[diff] [blame]8/ {
9 chosen {
10 u-boot,spl-boot-order = &spi_flash;
11 };
12
13 config {
Jonas Karlman1f3294b2024-12-12 23:57:09 +0000[diff] [blame]14 u-boot,spl-payload-offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
Simon Glasscc3f4352021-12-24 16:43:44 +0300[diff] [blame]15 };
16};
17
Quentin Schulzc4a219f2025-05-05 16:47:18 +0200[diff] [blame]18#if defined(CONFIG_ROCKCHIP_SPI_IMAGE)
Simon Glasscc3f4352021-12-24 16:43:44 +0300[diff] [blame]19&binman {
Quentin Schulzc4a219f2025-05-05 16:47:18 +0200[diff] [blame]20 simple-bin-spi {
Simon Glasscc3f4352021-12-24 16:43:44 +0300[diff] [blame]21 size = <0x800000>;
22 };
23};
Quentin Schulzc4a219f2025-05-05 16:47:18 +0200[diff] [blame]24#endif
Simon Glasscc3f4352021-12-24 16:43:44 +0300[diff] [blame]25
26&cros_ec {
27 ec-interrupt = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
28};
29
30&edp {
31 rockchip,panel = <&edp_panel>;
32};
33
Jonas Karlmane9b187d2024-12-12 23:57:15 +0000[diff] [blame]34&emmc_phy {
35 /delete-property/ bootph-pre-ram;
36};
37
Jonas Karlman96fbf682024-12-12 23:57:18 +0000[diff] [blame]38&gpio0 {
39 bootph-pre-ram;
40};
41
42&pp1500_ap_io {
43 bootph-pre-ram;
44};
Jonas Karlmane9b187d2024-12-12 23:57:15 +0000[diff] [blame]45
Simon Glasscc3f4352021-12-24 16:43:44 +0300[diff] [blame]46&pp1800_audio {
47 regulator-min-microvolt = <1800000>;
48 regulator-max-microvolt = <1800000>;
49};
50
Jonas Karlman96fbf682024-12-12 23:57:18 +0000[diff] [blame]51&pp1500_en {
52 bootph-pre-ram;
53};
54
55&pp3000 {
56 bootph-pre-ram;
57};
58
59&pp3000_en {
60 bootph-pre-ram;
61};
62
Simon Glasscc3f4352021-12-24 16:43:44 +0300[diff] [blame]63&ppvar_bigcpu_pwm {
64 regulator-init-microvolt = <900000>;
65};
66
67&ppvar_centerlogic_pwm {
68 regulator-init-microvolt = <900000>;
69};
70
71&ppvar_gpu_pwm {
72 regulator-init-microvolt = <900000>;
73};
74
75&ppvar_litcpu_pwm {
76 regulator-init-microvolt = <900000>;
77};
78
79&ppvar_sd_card_io {
80 enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
81};
82
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]83&sdhci {
84 /delete-property/ bootph-pre-ram;
85};
86
87&sdmmc {
88 /delete-property/ bootph-pre-ram;
89};
90
91&sdmmc_bus4 {
92 /delete-property/ bootph-pre-ram;
93};
94
95&sdmmc_cd {
96 /delete-property/ bootph-pre-ram;
97};
98
99&sdmmc_clk {
100 /delete-property/ bootph-pre-ram;
101};
102
103&sdmmc_cmd {
104 /delete-property/ bootph-pre-ram;
105};
106
Jonas Karlmand7728122024-05-01 16:22:23 +0000[diff] [blame]107&spi1 {
108 spi_flash: flash@0 {
Jonas Karlmane9b187d2024-12-12 23:57:15 +0000[diff] [blame]109 bootph-pre-ram;
110 bootph-some-ram;
Jonas Karlmand7728122024-05-01 16:22:23 +0000[diff] [blame]111 };
112};
113
Simon Glasscc3f4352021-12-24 16:43:44 +0300[diff] [blame]114&spi5 {
115 spi-activate-delay = <100>;
116 spi-max-frequency = <3000000>;
117 spi-deactivate-delay = <200>;
118};