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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / dts / nuvoton-common-npcm7xx.dtsi
blob: 093d5427e305f6c24001af5ab0d9398650bb6700 [file] [log] [blame]
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/interrupt-controller/arm-gic.h>
4#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
5#include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
6
7/ {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 /* external reference clock */
13 clk_refclk: clk_refclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <25000000>;
17 clock-output-names = "refclk";
18 };
19
20 /* external reference clock for cpu. float in normal operation */
21 clk_sysbypck: clk_sysbypck {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <800000000>;
25 clock-output-names = "sysbypck";
26 };
27
28 /* external reference clock for MC. float in normal operation */
29 clk_mcbypck: clk_mcbypck {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <800000000>;
33 clock-output-names = "mcbypck";
34 };
35
36 /* external clock signal rg1refck, supplied by the phy */
37 clk_rg1refck: clk_rg1refck {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <125000000>;
41 clock-output-names = "clk_rg1refck";
42 };
43
44 /* external clock signal rg2refck, supplied by the phy */
45 clk_rg2refck: clk_rg2refck {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <125000000>;
49 clock-output-names = "clk_rg2refck";
50 };
51
52 clk_xin: clk_xin {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <50000000>;
56 clock-output-names = "clk_xin";
57 };
58
59 soc {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "simple-bus";
63 interrupt-parent = <&gic>;
64 ranges = <0x0 0xf0000000 0x00900000>;
65
66 scu: scu@3fe000 {
67 compatible = "arm,cortex-a9-scu";
68 reg = <0x3fe000 0x1000>;
69 };
70
71 l2: cache-controller@3fc000 {
72 compatible = "arm,pl310-cache";
73 reg = <0x3fc000 0x1000>;
74 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
75 cache-unified;
76 cache-level = <2>;
77 clocks = <&clk NPCM7XX_CLK_AXI>;
78 arm,shared-override;
79 };
80
81 gic: interrupt-controller@3ff000 {
82 compatible = "arm,cortex-a9-gic";
83 interrupt-controller;
84 #interrupt-cells = <3>;
85 reg = <0x3ff000 0x1000>,
86 <0x3fe100 0x100>;
87 };
88
89 gcr: gcr@800000 {
90 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
91 reg = <0x800000 0x1000>;
92 };
93
94 rst: rst@801000 {
95 compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
96 reg = <0x801000 0x6C>;
97 };
Jim Liuc3112f82025-02-25 09:45:05 +0800[diff] [blame]98
99 timer0: timer@f0801068 {
100 compatible = "nuvoton,npcm750-timer";
101 reg = <0x801068 0x8>;
102 };
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]103 };
104
105 ahb {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "simple-bus";
109 interrupt-parent = <&gic>;
110 ranges;
111
112 rstc: rstc@f0801000 {
113 compatible = "nuvoton,npcm750-reset";
114 reg = <0xf0801000 0x70>;
115 #reset-cells = <2>;
116 };
117
118 clk: clock-controller@f0801000 {
119 compatible = "nuvoton,npcm750-clk", "syscon";
120 #clock-cells = <1>;
121 clock-controller;
122 reg = <0xf0801000 0x1000>;
123 clock-names = "refclk", "sysbypck", "mcbypck";
124 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
125 };
126
127 gmac0: eth@f0802000 {
128 device_type = "network";
129 compatible = "nuvoton,npcm-dwmac";
130 reg = <0xf0802000 0x2000>;
131 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
132 interrupt-names = "macirq";
133 ethernet = <0>;
134 clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
135 clock-names = "stmmaceth", "clk_gmac";
136 pinctrl-names = "default";
137 pinctrl-0 = <&rg1_pins
138 &rg1mdio_pins>;
139 status = "disabled";
140 };
141
142 ehci1: usb@f0806000 {
143 compatible = "nuvoton,npcm750-ehci";
144 reg = <0xf0806000 0x1000>;
145 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
146 status = "disabled";
147 };
148
149 fiu0: spi@fb000000 {
150 compatible = "nuvoton,npcm750-fiu";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 reg = <0xfb000000 0x1000>;
154 reg-names = "control", "memory";
155 clocks = <&clk NPCM7XX_CLK_SPI0>;
156 clock-names = "clk_spi0";
157 status = "disabled";
158 };
159
160 fiu3: spi@c0000000 {
161 compatible = "nuvoton,npcm750-fiu";
162 #address-cells = <1>;
163 #size-cells = <0>;
164 reg = <0xc0000000 0x1000>;
165 reg-names = "control", "memory";
166 clocks = <&clk NPCM7XX_CLK_SPI3>;
167 clock-names = "clk_spi3";
168 pinctrl-names = "default";
169 pinctrl-0 = <&spi3_pins>;
170 status = "disabled";
171 };
172
173 fiux: spi@fb001000 {
174 compatible = "nuvoton,npcm750-fiu";
175 #address-cells = <1>;
176 #size-cells = <0>;
177 reg = <0xfb001000 0x1000>;
178 reg-names = "control", "memory";
179 clocks = <&clk NPCM7XX_CLK_SPIX>;
180 clock-names = "clk_spix";
181 status = "disabled";
182 };
183
184 apb {
185 #address-cells = <1>;
186 #size-cells = <1>;
187 compatible = "simple-bus";
188 interrupt-parent = <&gic>;
189 ranges = <0x0 0xf0000000 0x00300000>;
190
191 lpc_kcs: lpc_kcs@7000 {
192 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
193 reg = <0x7000 0x40>;
194 reg-io-width = <1>;
195
196 #address-cells = <1>;
197 #size-cells = <1>;
198 ranges = <0x0 0x7000 0x40>;
199
200 kcs1: kcs1@0 {
201 compatible = "nuvoton,npcm750-kcs-bmc";
202 reg = <0x0 0x40>;
203 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
204 kcs_chan = <1>;
205 status = "disabled";
206 };
207
208 kcs2: kcs2@0 {
209 compatible = "nuvoton,npcm750-kcs-bmc";
210 reg = <0x0 0x40>;
211 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
212 kcs_chan = <2>;
213 status = "disabled";
214 };
215
216 kcs3: kcs3@0 {
217 compatible = "nuvoton,npcm750-kcs-bmc";
218 reg = <0x0 0x40>;
219 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
220 kcs_chan = <3>;
221 status = "disabled";
222 };
223 };
224
225 spi0: spi@200000 {
226 compatible = "nuvoton,npcm750-pspi";
227 reg = <0x200000 0x1000>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&pspi1_pins>;
230 #address-cells = <1>;
231 #size-cells = <0>;
232 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clk NPCM7XX_CLK_APB5>;
234 clock-names = "clk_apb5";
235 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
236 status = "disabled";
237 };
238
239 spi1: spi@201000 {
240 compatible = "nuvoton,npcm750-pspi";
241 reg = <0x201000 0x1000>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pspi2_pins>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clk NPCM7XX_CLK_APB5>;
248 clock-names = "clk_apb5";
249 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>;
250 status = "disabled";
251 };
252
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]253 watchdog0: watchdog@801C {
254 compatible = "nuvoton,npcm750-wdt";
255 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
256 reg = <0x801C 0x4>;
257 status = "disabled";
258 clocks = <&clk NPCM7XX_CLK_TIMER>;
259 };
260
261 watchdog1: watchdog@901C {
262 compatible = "nuvoton,npcm750-wdt";
263 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
264 reg = <0x901C 0x4>;
265 status = "disabled";
266 clocks = <&clk NPCM7XX_CLK_TIMER>;
267 };
268
269 watchdog2: watchdog@a01C {
270 compatible = "nuvoton,npcm750-wdt";
271 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
272 reg = <0xa01C 0x4>;
273 status = "disabled";
274 clocks = <&clk NPCM7XX_CLK_TIMER>;
275 };
276
277 serial0: serial@1000 {
278 compatible = "nuvoton,npcm750-uart";
279 reg = <0x1000 0x1000>;
280 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
281 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
282 reg-shift = <2>;
283 status = "disabled";
284 };
285
286 serial1: serial@2000 {
287 compatible = "nuvoton,npcm750-uart";
288 reg = <0x2000 0x1000>;
289 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
290 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
291 reg-shift = <2>;
292 status = "disabled";
293 };
294
295 serial2: serial@3000 {
296 compatible = "nuvoton,npcm750-uart";
297 reg = <0x3000 0x1000>;
298 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
299 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
300 reg-shift = <2>;
301 status = "disabled";
302 };
303
304 serial3: serial@4000 {
305 compatible = "nuvoton,npcm750-uart";
306 reg = <0x4000 0x1000>;
307 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
308 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
309 reg-shift = <2>;
310 status = "disabled";
311 };
312
313 rng: rng@b000 {
314 compatible = "nuvoton,npcm750-rng";
315 reg = <0xb000 0x8>;
316 status = "disabled";
317 };
318
319 adc: adc@c000 {
320 compatible = "nuvoton,npcm750-adc";
321 reg = <0xc000 0x8>;
322 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clk NPCM7XX_CLK_ADC>;
324 resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
325 status = "disabled";
326 };
327
328 pwm_fan: pwm-fan-controller@103000 {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 compatible = "nuvoton,npcm750-pwm-fan";
332 reg = <0x103000 0x2000>, <0x180000 0x8000>;
333 reg-names = "pwm", "fan";
334 clocks = <&clk NPCM7XX_CLK_APB3>,
335 <&clk NPCM7XX_CLK_APB4>;
336 clock-names = "pwm","fan";
337 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&pwm0_pins &pwm1_pins
347 &pwm2_pins &pwm3_pins
348 &pwm4_pins &pwm5_pins
349 &pwm6_pins &pwm7_pins
350 &fanin0_pins &fanin1_pins
351 &fanin2_pins &fanin3_pins
352 &fanin4_pins &fanin5_pins
353 &fanin6_pins &fanin7_pins
354 &fanin8_pins &fanin9_pins
355 &fanin10_pins &fanin11_pins
356 &fanin12_pins &fanin13_pins
357 &fanin14_pins &fanin15_pins>;
358 status = "disabled";
359 };
360
361 i2c0: i2c@80000 {
362 reg = <0x80000 0x1000>;
363 compatible = "nuvoton,npcm750-i2c";
364 #address-cells = <1>;
365 #size-cells = <0>;
366 clocks = <&clk NPCM7XX_CLK_APB2>;
367 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&smb0_pins>;
370 status = "disabled";
371 };
372
373 i2c1: i2c@81000 {
374 reg = <0x81000 0x1000>;
375 compatible = "nuvoton,npcm750-i2c";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 clocks = <&clk NPCM7XX_CLK_APB2>;
379 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&smb1_pins>;
382 status = "disabled";
383 };
384
385 i2c2: i2c@82000 {
386 reg = <0x82000 0x1000>;
387 compatible = "nuvoton,npcm750-i2c";
388 #address-cells = <1>;
389 #size-cells = <0>;
390 clocks = <&clk NPCM7XX_CLK_APB2>;
391 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&smb2_pins>;
394 status = "disabled";
395 };
396
397 i2c3: i2c@83000 {
398 reg = <0x83000 0x1000>;
399 compatible = "nuvoton,npcm750-i2c";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 clocks = <&clk NPCM7XX_CLK_APB2>;
403 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&smb3_pins>;
406 status = "disabled";
407 };
408
409 i2c4: i2c@84000 {
410 reg = <0x84000 0x1000>;
411 compatible = "nuvoton,npcm750-i2c";
412 #address-cells = <1>;
413 #size-cells = <0>;
414 clocks = <&clk NPCM7XX_CLK_APB2>;
415 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&smb4_pins>;
418 status = "disabled";
419 };
420
421 i2c5: i2c@85000 {
422 reg = <0x85000 0x1000>;
423 compatible = "nuvoton,npcm750-i2c";
424 #address-cells = <1>;
425 #size-cells = <0>;
426 clocks = <&clk NPCM7XX_CLK_APB2>;
427 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&smb5_pins>;
430 status = "disabled";
431 };
432
433 i2c6: i2c@86000 {
434 reg = <0x86000 0x1000>;
435 compatible = "nuvoton,npcm750-i2c";
436 #address-cells = <1>;
437 #size-cells = <0>;
438 clocks = <&clk NPCM7XX_CLK_APB2>;
439 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&smb6_pins>;
442 status = "disabled";
443 };
444
445 i2c7: i2c@87000 {
446 reg = <0x87000 0x1000>;
447 compatible = "nuvoton,npcm750-i2c";
448 #address-cells = <1>;
449 #size-cells = <0>;
450 clocks = <&clk NPCM7XX_CLK_APB2>;
451 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&smb7_pins>;
454 status = "disabled";
455 };
456
457 i2c8: i2c@88000 {
458 reg = <0x88000 0x1000>;
459 compatible = "nuvoton,npcm750-i2c";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 clocks = <&clk NPCM7XX_CLK_APB2>;
463 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&smb8_pins>;
466 status = "disabled";
467 };
468
469 i2c9: i2c@89000 {
470 reg = <0x89000 0x1000>;
471 compatible = "nuvoton,npcm750-i2c";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 clocks = <&clk NPCM7XX_CLK_APB2>;
475 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&smb9_pins>;
478 status = "disabled";
479 };
480
481 i2c10: i2c@8a000 {
482 reg = <0x8a000 0x1000>;
483 compatible = "nuvoton,npcm750-i2c";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 clocks = <&clk NPCM7XX_CLK_APB2>;
487 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&smb10_pins>;
490 status = "disabled";
491 };
492
493 i2c11: i2c@8b000 {
494 reg = <0x8b000 0x1000>;
495 compatible = "nuvoton,npcm750-i2c";
496 #address-cells = <1>;
497 #size-cells = <0>;
498 clocks = <&clk NPCM7XX_CLK_APB2>;
499 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&smb11_pins>;
502 status = "disabled";
503 };
504
505 i2c12: i2c@8c000 {
506 reg = <0x8c000 0x1000>;
507 compatible = "nuvoton,npcm750-i2c";
508 #address-cells = <1>;
509 #size-cells = <0>;
510 clocks = <&clk NPCM7XX_CLK_APB2>;
511 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&smb12_pins>;
514 status = "disabled";
515 };
516
517 i2c13: i2c@8d000 {
518 reg = <0x8d000 0x1000>;
519 compatible = "nuvoton,npcm750-i2c";
520 #address-cells = <1>;
521 #size-cells = <0>;
522 clocks = <&clk NPCM7XX_CLK_APB2>;
523 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&smb13_pins>;
526 status = "disabled";
527 };
528
529 i2c14: i2c@8e000 {
530 reg = <0x8e000 0x1000>;
531 compatible = "nuvoton,npcm750-i2c";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 clocks = <&clk NPCM7XX_CLK_APB2>;
535 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&smb14_pins>;
538 status = "disabled";
539 };
540
541 i2c15: i2c@8f000 {
542 reg = <0x8f000 0x1000>;
543 compatible = "nuvoton,npcm750-i2c";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 clocks = <&clk NPCM7XX_CLK_APB2>;
547 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&smb15_pins>;
550 status = "disabled";
551 };
552 };
553 };
554
555 pinctrl: pinctrl@f0800000 {
556 #address-cells = <1>;
557 #size-cells = <1>;
558 compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
559 ranges = <0 0xf0010000 0x8000>;
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]560 reg = <0xf0010000 0x8000>;
561 syscon-gcr = <&gcr>;
562 syscon-rst = <&rst>;
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]563 gpio0: gpio@f0010000 {
564 gpio-controller;
565 #gpio-cells = <2>;
566 reg = <0x0 0x80>;
567 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
568 gpio-ranges = <&pinctrl 0 0 32>;
569 };
570 gpio1: gpio@f0011000 {
571 gpio-controller;
572 #gpio-cells = <2>;
573 reg = <0x1000 0x80>;
574 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
575 gpio-ranges = <&pinctrl 0 32 32>;
576 };
577 gpio2: gpio@f0012000 {
578 gpio-controller;
579 #gpio-cells = <2>;
580 reg = <0x2000 0x80>;
581 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
582 gpio-ranges = <&pinctrl 0 64 32>;
583 };
584 gpio3: gpio@f0013000 {
585 gpio-controller;
586 #gpio-cells = <2>;
587 reg = <0x3000 0x80>;
588 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
589 gpio-ranges = <&pinctrl 0 96 32>;
590 };
591 gpio4: gpio@f0014000 {
592 gpio-controller;
593 #gpio-cells = <2>;
594 reg = <0x4000 0x80>;
595 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
596 gpio-ranges = <&pinctrl 0 128 32>;
597 };
598 gpio5: gpio@f0015000 {
599 gpio-controller;
600 #gpio-cells = <2>;
601 reg = <0x5000 0x80>;
602 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
603 gpio-ranges = <&pinctrl 0 160 32>;
604 };
605 gpio6: gpio@f0016000 {
606 gpio-controller;
607 #gpio-cells = <2>;
608 reg = <0x6000 0x80>;
609 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
610 gpio-ranges = <&pinctrl 0 192 32>;
611 };
612 gpio7: gpio@f0017000 {
613 gpio-controller;
614 #gpio-cells = <2>;
615 reg = <0x7000 0x80>;
616 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
617 gpio-ranges = <&pinctrl 0 224 32>;
618 };
619
620 iox1_pins: iox1-pins {
621 groups = "iox1";
622 function = "iox1";
623 };
624 iox2_pins: iox2-pins {
625 groups = "iox2";
626 function = "iox2";
627 };
628 smb1d_pins: smb1d-pins {
629 groups = "smb1d";
630 function = "smb1d";
631 };
632 smb2d_pins: smb2d-pins {
633 groups = "smb2d";
634 function = "smb2d";
635 };
636 lkgpo1_pins: lkgpo1-pins {
637 groups = "lkgpo1";
638 function = "lkgpo1";
639 };
640 lkgpo2_pins: lkgpo2-pins {
641 groups = "lkgpo2";
642 function = "lkgpo2";
643 };
644 ioxh_pins: ioxh-pins {
645 groups = "ioxh";
646 function = "ioxh";
647 };
648 gspi_pins: gspi-pins {
649 groups = "gspi";
650 function = "gspi";
651 };
652 smb5b_pins: smb5b-pins {
653 groups = "smb5b";
654 function = "smb5b";
655 };
656 smb5c_pins: smb5c-pins {
657 groups = "smb5c";
658 function = "smb5c";
659 };
660 lkgpo0_pins: lkgpo0-pins {
661 groups = "lkgpo0";
662 function = "lkgpo0";
663 };
664 pspi2_pins: pspi2-pins {
665 groups = "pspi2";
666 function = "pspi2";
667 };
668 smb4den_pins: smb4den-pins {
669 groups = "smb4den";
670 function = "smb4den";
671 };
672 smb4b_pins: smb4b-pins {
673 groups = "smb4b";
674 function = "smb4b";
675 };
676 smb4c_pins: smb4c-pins {
677 groups = "smb4c";
678 function = "smb4c";
679 };
680 smb15_pins: smb15-pins {
681 groups = "smb15";
682 function = "smb15";
683 };
684 smb4d_pins: smb4d-pins {
685 groups = "smb4d";
686 function = "smb4d";
687 };
688 smb14_pins: smb14-pins {
689 groups = "smb14";
690 function = "smb14";
691 };
692 smb5_pins: smb5-pins {
693 groups = "smb5";
694 function = "smb5";
695 };
696 smb4_pins: smb4-pins {
697 groups = "smb4";
698 function = "smb4";
699 };
700 smb3_pins: smb3-pins {
701 groups = "smb3";
702 function = "smb3";
703 };
704 spi0cs1_pins: spi0cs1-pins {
705 groups = "spi0cs1";
706 function = "spi0cs1";
707 };
708 spi0cs2_pins: spi0cs2-pins {
709 groups = "spi0cs2";
710 function = "spi0cs2";
711 };
712 spi0cs3_pins: spi0cs3-pins {
713 groups = "spi0cs3";
714 function = "spi0cs3";
715 };
716 smb3c_pins: smb3c-pins {
717 groups = "smb3c";
718 function = "smb3c";
719 };
720 smb3b_pins: smb3b-pins {
721 groups = "smb3b";
722 function = "smb3b";
723 };
724 bmcuart0a_pins: bmcuart0a-pins {
725 groups = "bmcuart0a";
726 function = "bmcuart0a";
727 };
728 uart1_pins: uart1-pins {
729 groups = "uart1";
730 function = "uart1";
731 };
732 jtag2_pins: jtag2-pins {
733 groups = "jtag2";
734 function = "jtag2";
735 };
736 bmcuart1_pins: bmcuart1-pins {
737 groups = "bmcuart1";
738 function = "bmcuart1";
739 };
740 uart2_pins: uart2-pins {
741 groups = "uart2";
742 function = "uart2";
743 };
744 bmcuart0b_pins: bmcuart0b-pins {
745 groups = "bmcuart0b";
746 function = "bmcuart0b";
747 };
748 r1err_pins: r1err-pins {
749 groups = "r1err";
750 function = "r1err";
751 };
752 r1md_pins: r1md-pins {
753 groups = "r1md";
754 function = "r1md";
755 };
756 smb3d_pins: smb3d-pins {
757 groups = "smb3d";
758 function = "smb3d";
759 };
760 fanin0_pins: fanin0-pins {
761 groups = "fanin0";
762 function = "fanin0";
763 };
764 fanin1_pins: fanin1-pins {
765 groups = "fanin1";
766 function = "fanin1";
767 };
768 fanin2_pins: fanin2-pins {
769 groups = "fanin2";
770 function = "fanin2";
771 };
772 fanin3_pins: fanin3-pins {
773 groups = "fanin3";
774 function = "fanin3";
775 };
776 fanin4_pins: fanin4-pins {
777 groups = "fanin4";
778 function = "fanin4";
779 };
780 fanin5_pins: fanin5-pins {
781 groups = "fanin5";
782 function = "fanin5";
783 };
784 fanin6_pins: fanin6-pins {
785 groups = "fanin6";
786 function = "fanin6";
787 };
788 fanin7_pins: fanin7-pins {
789 groups = "fanin7";
790 function = "fanin7";
791 };
792 fanin8_pins: fanin8-pins {
793 groups = "fanin8";
794 function = "fanin8";
795 };
796 fanin9_pins: fanin9-pins {
797 groups = "fanin9";
798 function = "fanin9";
799 };
800 fanin10_pins: fanin10-pins {
801 groups = "fanin10";
802 function = "fanin10";
803 };
804 fanin11_pins: fanin11-pins {
805 groups = "fanin11";
806 function = "fanin11";
807 };
808 fanin12_pins: fanin12-pins {
809 groups = "fanin12";
810 function = "fanin12";
811 };
812 fanin13_pins: fanin13-pins {
813 groups = "fanin13";
814 function = "fanin13";
815 };
816 fanin14_pins: fanin14-pins {
817 groups = "fanin14";
818 function = "fanin14";
819 };
820 fanin15_pins: fanin15-pins {
821 groups = "fanin15";
822 function = "fanin15";
823 };
824 pwm0_pins: pwm0-pins {
825 groups = "pwm0";
826 function = "pwm0";
827 };
828 pwm1_pins: pwm1-pins {
829 groups = "pwm1";
830 function = "pwm1";
831 };
832 pwm2_pins: pwm2-pins {
833 groups = "pwm2";
834 function = "pwm2";
835 };
836 pwm3_pins: pwm3-pins {
837 groups = "pwm3";
838 function = "pwm3";
839 };
840 r2_pins: r2-pins {
841 groups = "r2";
842 function = "r2";
843 };
844 r2err_pins: r2err-pins {
845 groups = "r2err";
846 function = "r2err";
847 };
848 r2md_pins: r2md-pins {
849 groups = "r2md";
850 function = "r2md";
851 };
852 ga20kbc_pins: ga20kbc-pins {
853 groups = "ga20kbc";
854 function = "ga20kbc";
855 };
856 smb5d_pins: smb5d-pins {
857 groups = "smb5d";
858 function = "smb5d";
859 };
860 lpc_pins: lpc-pins {
861 groups = "lpc";
862 function = "lpc";
863 };
864 espi_pins: espi-pins {
865 groups = "espi";
866 function = "espi";
867 };
868 rg1_pins: rg1-pins {
869 groups = "rg1";
870 function = "rg1";
871 };
872 rg1mdio_pins: rg1mdio-pins {
873 groups = "rg1mdio";
874 function = "rg1mdio";
875 };
876 rg2_pins: rg2-pins {
877 groups = "rg2";
878 function = "rg2";
879 };
880 ddr_pins: ddr-pins {
881 groups = "ddr";
882 function = "ddr";
883 };
884 smb0_pins: smb0-pins {
885 groups = "smb0";
886 function = "smb0";
887 };
888 smb1_pins: smb1-pins {
889 groups = "smb1";
890 function = "smb1";
891 };
892 smb2_pins: smb2-pins {
893 groups = "smb2";
894 function = "smb2";
895 };
896 smb2c_pins: smb2c-pins {
897 groups = "smb2c";
898 function = "smb2c";
899 };
900 smb2b_pins: smb2b-pins {
901 groups = "smb2b";
902 function = "smb2b";
903 };
904 smb1c_pins: smb1c-pins {
905 groups = "smb1c";
906 function = "smb1c";
907 };
908 smb1b_pins: smb1b-pins {
909 groups = "smb1b";
910 function = "smb1b";
911 };
912 smb8_pins: smb8-pins {
913 groups = "smb8";
914 function = "smb8";
915 };
916 smb9_pins: smb9-pins {
917 groups = "smb9";
918 function = "smb9";
919 };
920 smb10_pins: smb10-pins {
921 groups = "smb10";
922 function = "smb10";
923 };
924 smb11_pins: smb11-pins {
925 groups = "smb11";
926 function = "smb11";
927 };
928 sd1_pins: sd1-pins {
929 groups = "sd1";
930 function = "sd1";
931 };
932 sd1pwr_pins: sd1pwr-pins {
933 groups = "sd1pwr";
934 function = "sd1pwr";
935 };
936 pwm4_pins: pwm4-pins {
937 groups = "pwm4";
938 function = "pwm4";
939 };
940 pwm5_pins: pwm5-pins {
941 groups = "pwm5";
942 function = "pwm5";
943 };
944 pwm6_pins: pwm6-pins {
945 groups = "pwm6";
946 function = "pwm6";
947 };
948 pwm7_pins: pwm7-pins {
949 groups = "pwm7";
950 function = "pwm7";
951 };
952 mmc8_pins: mmc8-pins {
953 groups = "mmc8";
954 function = "mmc8";
955 };
956 mmc_pins: mmc-pins {
957 groups = "mmc";
958 function = "mmc";
959 };
960 mmcwp_pins: mmcwp-pins {
961 groups = "mmcwp";
962 function = "mmcwp";
963 };
964 mmccd_pins: mmccd-pins {
965 groups = "mmccd";
966 function = "mmccd";
967 };
968 mmcrst_pins: mmcrst-pins {
969 groups = "mmcrst";
970 function = "mmcrst";
971 };
972 clkout_pins: clkout-pins {
973 groups = "clkout";
974 function = "clkout";
975 };
976 serirq_pins: serirq-pins {
977 groups = "serirq";
978 function = "serirq";
979 };
980 lpcclk_pins: lpcclk-pins {
981 groups = "lpcclk";
982 function = "lpcclk";
983 };
984 scipme_pins: scipme-pins {
985 groups = "scipme";
986 function = "scipme";
987 };
988 sci_pins: sci-pins {
989 groups = "sci";
990 function = "sci";
991 };
992 smb6_pins: smb6-pins {
993 groups = "smb6";
994 function = "smb6";
995 };
996 smb7_pins: smb7-pins {
997 groups = "smb7";
998 function = "smb7";
999 };
1000 pspi1_pins: pspi1-pins {
1001 groups = "pspi1";
1002 function = "pspi1";
1003 };
1004 faninx_pins: faninx-pins {
1005 groups = "faninx";
1006 function = "faninx";
1007 };
1008 r1_pins: r1-pins {
1009 groups = "r1";
1010 function = "r1";
1011 };
1012 spi3_pins: spi3-pins {
1013 groups = "spi3";
1014 function = "spi3";
1015 };
1016 spi3cs1_pins: spi3cs1-pins {
1017 groups = "spi3cs1";
1018 function = "spi3cs1";
1019 };
1020 spi3quad_pins: spi3quad-pins {
1021 groups = "spi3quad";
1022 function = "spi3quad";
1023 };
1024 spi3cs2_pins: spi3cs2-pins {
1025 groups = "spi3cs2";
1026 function = "spi3cs2";
1027 };
1028 spi3cs3_pins: spi3cs3-pins {
1029 groups = "spi3cs3";
1030 function = "spi3cs3";
1031 };
1032 nprd_smi_pins: nprd-smi-pins {
1033 groups = "nprd_smi";
1034 function = "nprd_smi";
1035 };
1036 smb0b_pins: smb0b-pins {
1037 groups = "smb0b";
1038 function = "smb0b";
1039 };
1040 smb0c_pins: smb0c-pins {
1041 groups = "smb0c";
1042 function = "smb0c";
1043 };
1044 smb0den_pins: smb0den-pins {
1045 groups = "smb0den";
1046 function = "smb0den";
1047 };
1048 smb0d_pins: smb0d-pins {
1049 groups = "smb0d";
1050 function = "smb0d";
1051 };
1052 ddc_pins: ddc-pins {
1053 groups = "ddc";
1054 function = "ddc";
1055 };
1056 rg2mdio_pins: rg2mdio-pins {
1057 groups = "rg2mdio";
1058 function = "rg2mdio";
1059 };
1060 wdog1_pins: wdog1-pins {
1061 groups = "wdog1";
1062 function = "wdog1";
1063 };
1064 wdog2_pins: wdog2-pins {
1065 groups = "wdog2";
1066 function = "wdog2";
1067 };
1068 smb12_pins: smb12-pins {
1069 groups = "smb12";
1070 function = "smb12";
1071 };
1072 smb13_pins: smb13-pins {
1073 groups = "smb13";
1074 function = "smb13";
1075 };
1076 spix_pins: spix-pins {
1077 groups = "spix";
1078 function = "spix";
1079 };
1080 spixcs1_pins: spixcs1-pins {
1081 groups = "spixcs1";
1082 function = "spixcs1";
1083 };
1084 clkreq_pins: clkreq-pins {
1085 groups = "clkreq";
1086 function = "clkreq";
1087 };
1088 hgpio0_pins: hgpio0-pins {
1089 groups = "hgpio0";
1090 function = "hgpio0";
1091 };
1092 hgpio1_pins: hgpio1-pins {
1093 groups = "hgpio1";
1094 function = "hgpio1";
1095 };
1096 hgpio2_pins: hgpio2-pins {
1097 groups = "hgpio2";
1098 function = "hgpio2";
1099 };
1100 hgpio3_pins: hgpio3-pins {
1101 groups = "hgpio3";
1102 function = "hgpio3";
1103 };
1104 hgpio4_pins: hgpio4-pins {
1105 groups = "hgpio4";
1106 function = "hgpio4";
1107 };
1108 hgpio5_pins: hgpio5-pins {
1109 groups = "hgpio5";
1110 function = "hgpio5";
1111 };
1112 hgpio6_pins: hgpio6-pins {
1113 groups = "hgpio6";
1114 function = "hgpio6";
1115 };
1116 hgpio7_pins: hgpio7-pins {
1117 groups = "hgpio7";
1118 function = "hgpio7";
1119 };
1120 };
1121};