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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / dts / mt7987.dtsi
blob: 4c1d597499ce5cb4c448a50689a8e03d150721da [file] [log] [blame]
developer2de1f362025-01-23 16:55:01 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/reset/ti-syscon.h>
11#include <dt-bindings/clock/mediatek,mt7987-clk.h>
12#include <dt-bindings/pinctrl/mt65xx.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/thermal/thermal.h>
15#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
16
17/ {
18 compatible = "mediatek,mt7987";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 clkxtal: oscillator@0 {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <40000000>;
27 clock-output-names = "clkxtal";
28 };
29
30 vproc: regulator-vproc {
31 compatible = "regulator-fixed";
32 regulator-name = "proc";
33 regulator-min-microvolt = <8500000>;
34 regulator-max-microvolt = <8500000>;
35 regulator-boot-on;
36 regulator-always-on;
37 };
38
39 firmware {
40 optee {
41 method = "smc";
42 compatible = "linaro,optee-tz";
43 status = "okay";
44 };
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a53";
53 enable-method = "psci";
54 next-level-cache = <&l2_cache>;
55 reg = <0x0>;
56 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
57 <&topckgen CLK_TOP_CB_CKSQ_40M>,
58 <&apmixedsys CLK_APMIXED_ARM_LL>;
59 clock-names = "cpu", "intermediate", "armpll";
60 operating-points-v2 = <&cluster0_opp>;
61 };
62
63 cpu1: cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a53";
66 enable-method = "psci";
67 next-level-cache = <&l2_cache>;
68 reg = <0x1>;
69 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
70 <&topckgen CLK_TOP_CB_CKSQ_40M>,
71 <&apmixedsys CLK_APMIXED_ARM_LL>;
72 clock-names = "cpu", "intermediate", "armpll";
73 operating-points-v2 = <&cluster0_opp>;
74 };
75
76 cpu2: cpu@2 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 next-level-cache = <&l2_cache>;
81 reg = <0x2>;
82 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
83 <&topckgen CLK_TOP_CB_CKSQ_40M>,
84 <&apmixedsys CLK_APMIXED_ARM_LL>;
85 clock-names = "cpu", "intermediate", "armpll";
86 operating-points-v2 = <&cluster0_opp>;
87 };
88
89 cpu3: cpu@3 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a53";
92 enable-method = "psci";
93 next-level-cache = <&l2_cache>;
94 reg = <0x3>;
95 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
96 <&topckgen CLK_TOP_CB_CKSQ_40M>,
97 <&apmixedsys CLK_APMIXED_ARM_LL>;
98 clock-names = "cpu", "intermediate", "armpll";
99 operating-points-v2 = <&cluster0_opp>;
100 };
101
102 cluster0_opp: opp_table0 {
103 compatible = "operating-points-v2";
104 opp-shared;
105 opp00 {
106 opp-hz = /bits/ 64 <500000000>;
107 opp-microvolt = <850000>;
108 };
109 opp01 {
110 opp-hz = /bits/ 64 <1300000000>;
111 opp-microvolt = <850000>;
112 };
113 opp02 {
114 opp-hz = /bits/ 64 <1600000000>;
115 opp-microvolt = <850000>;
116 };
117 opp03 {
118 opp-hz = /bits/ 64 <2000000000>;
119 opp-microvolt = <850000>;
120 };
121 };
122
123 l2_cache: l2-cache {
124 compatible = "cache";
125 cache-level = <2>;
126 };
127 };
128
129 clk40m: clk40m {
130 compatible = "fixed-clock";
131 #clock-cells = <0>;
132 clock-frequency = <40000000>;
133 };
134
135 clkitg: clkitg {
136 compatible = "simple-bus";
137 status = "disabled";
138 };
139
140 clksys: soc_clksys {
141 #address-cells = <2>;
142 #size-cells = <2>;
143 compatible = "simple-bus";
144 ranges;
145
146 infracfg: infracfg@10001000 {
147 compatible = "mediatek,mt7987-infracfg", "syscon";
148 reg = <0 0x10001000 0 0x1000>;
149 #clock-cells = <1>;
150 };
151
152 topckgen: topckgen@1001b000 {
153 compatible = "mediatek,mt7987-topckgen", "syscon";
154 reg = <0 0x1001b000 0 0x1000>;
155 #clock-cells = <1>;
156 };
157
158 apmixedsys: apmixedsys@1001e000 {
159 compatible = "mediatek,mt7987-apmixedsys", "syscon";
160 reg = <0 0x1001e000 0 0x1000>;
161 #clock-cells = <1>;
162 };
163
164 sgmiisys0: syscon@10060000 {
165 compatible = "mediatek,mt7987-sgmiisys",
166 "mediatek,mt7987-sgmiisys_0",
167 "syscon";
168 reg = <0 0x10060000 0 0x1000>;
169 #clock-cells = <1>;
170 };
171
172 sgmiisys1: syscon@10070000 {
173 compatible = "mediatek,mt7987-sgmiisys",
174 "mediatek,mt7987-sgmiisys_1",
175 "syscon";
176 reg = <0 0x10070000 0 0x1000>;
177 #clock-cells = <1>;
178 };
179
180 mcusys: mcusys@10400000 {
181 compatible = "mediatek,mt7987-mcusys", "syscon";
182 reg = <0 0x10400000 0 0x1000>;
183 #clock-cells = <1>;
184 };
185
186 ethsys: syscon@15000000 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 compatible = "mediatek,mt7987-ethdma",
190 "mediatek,mt7987-ethsys",
191 "syscon";
192 reg = <0 0x15000000 0 0x1000>;
193 #clock-cells = <1>;
194 #reset-cells = <1>;
195 ethsysrst: reset-controller {
196 compatible = "ti,syscon-reset";
197 #reset-cells = <1>;
198 ti,reset-bits =
199 <0x34 4 0x34 4 0x34 4
200 (ASSERT_SET | DEASSERT_CLEAR |
201 STATUS_SET)>;
202 };
203 };
204 };
205
206 fan: pwm-fan {
207 compatible = "pwm-fan";
208 cooling-levels = <0 128 255>;
209 #cooling-cells = <2>;
210 #thermal-sensor-cells = <1>;
211 status = "disabled";
212 };
213
214 pmu: pmu {
215 compatible = "arm,cortex-a53-pmu";
216 interrupt-parent = <&gic>;
217 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
218 };
219
220 psci {
221 compatible = "arm,psci-0.2";
222 method = "smc";
223 };
224
225 reserved-memory {
226 #address-cells = <2>;
227 #size-cells = <2>;
228 ranges;
229
230 wmcpu_emi: wmcpu-reserved@50000000 {
231 compatible = "mediatek,wmcpu-reserved";
232 no-map;
233 reg = <0 0x50000000 0 0x00100000>;
234 };
235 };
236
237 thermal-zones {
238 thermal_zone0: soc_thermal {
239 polling-delay-passive = <1000>;
240 polling-delay = <1000>;
241 thermal-sensors = <&lvts 0>;
242 trips {
243 cpu_trip_crit: crit {
244 temperature = <125000>;
245 hysteresis = <2000>;
246 type = "critical";
247 };
248
249 cpu_trip_hot: hot {
250 temperature = <120000>;
251 hysteresis = <2000>;
252 type = "hot";
253 };
254
255 cpu_trip_active1: active1 {
256 temperature = <115000>;
257 hysteresis = <2000>;
258 type = "active";
259 };
260
261 cpu_trip_active0: active0 {
262 temperature = <85000>;
263 hysteresis = <2000>;
264 type = "active";
265 };
266
267 cpu_trip_passive: passive {
268 temperature = <40000>;
269 hysteresis = <2000>;
270 type = "passive";
271 };
272 };
273
274 cooling-maps {
275 cpu-active-high {
276 cooling-device = <&fan 2 2>;
277 trip = <&cpu_trip_active1>;
278 };
279
280 cpu-active-low {
281 cooling-device = <&fan 1 1>;
282 trip = <&cpu_trip_active0>;
283 };
284
285 cpu-passive {
286 cooling-device = <&fan 0 0>;
287 trip = <&cpu_trip_passive>;
288 };
289 };
290 };
291
292 thermal_zone1: mcusys_thermal {
293 polling-delay-passive = <1000>;
294 polling-delay = <1000>;
295 thermal-sensors = <&lvts 1>;
296 };
297
298 thermal_zone2: eth2p5g_thermal {
299 polling-delay-passive = <1000>;
300 polling-delay = <1000>;
301 thermal-sensors = <&lvts 2>;
302 };
303 };
304
305 timer {
306 compatible = "arm,armv8-timer";
307 interrupt-parent = <&gic>;
308 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
309 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
310 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
311 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
312 };
313
314 soc: soc {
315 #address-cells = <2>;
316 #size-cells = <2>;
317 compatible = "simple-bus";
318 ranges;
319
320 hwver: hwver@8000000 {
321 compatible = "mediatek,hwver", "syscon";
322 reg = <0 0x8000000 0 0x1000>;
323 };
324
325 gic: interrupt-controller@c000000 {
326 compatible = "arm,gic-v3";
327 #interrupt-cells = <3>;
328 interrupt-parent = <&gic>;
329 interrupt-controller;
330 reg = <0 0x0c000000 0 0x40000>, /* GICD */
331 <0 0x0c080000 0 0x200000>, /* GICR */
332 <0 0x0c400000 0 0x2000>, /* GICC */
333 <0 0x0c410000 0 0x1000>, /* GICH */
334 <0 0x0c420000 0 0x2000>; /* GICV */
335 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
336 };
337
338 infra_bus_prot: infra_bus_prot@1000310c {
339 compatible = "mediatek,infracfg_ao_bus_hang_prot";
340 reg = <0 0x1000310c 0 0x14>;
341 status = "disabled";
342 };
343
344 watchdog: watchdog@1001c000 {
345 compatible = "mediatek,mt7622-wdt",
346 "mediatek,mt6589-wdt",
347 "syscon";
348 reg = <0 0x1001c000 0 0x1000>;
349 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
350 #reset-cells = <1>;
351 status = "disabled";
352 };
353
354 pio: pinctrl@1001f000 {
355 compatible = "mediatek,mt7987-pinctrl";
356 reg = <0 0x1001f000 0 0x1000>,
357 <0 0x11d00000 0 0x1000>,
358 <0 0x11e00000 0 0x1000>,
359 <0 0x11f00000 0 0x1000>,
360 <0 0x11f40000 0 0x1000>,
361 <0 0x11f60000 0 0x1000>,
362 <0 0x1000b000 0 0x1000>;
363 reg-names = "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1",
364 "iocfg_rt2", "iocfg_tl", "eint";
365 gpio-controller;
366 #gpio-cells = <2>;
367 gpio-ranges = <&pio 0 0 50>;
368 interrupt-controller;
369 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-parent = <&gic>;
371 #interrupt-cells = <2>;
372
373 pcie1pereset {
374 gpio-hog;
375 gpios = <36 GPIO_ACTIVE_HIGH>;
376 output-high;
377 };
378 };
379
380 boottrap: boottrap@1001f6f0 {
381 compatible = "mediatek,boottrap";
382 reg = <0 0x1001f6f0 0 0x20>;
383 status = "disabled";
384 };
385
386 trng: trng@1020f000 {
387 compatible = "mediatek,mt7987-rng";
388 status = "disabled";
389 };
390
391 pwm: pwm@10048000 {
developer5551adc2025-03-07 11:22:23 +0800[diff] [blame]392 compatible = "mediatek,mt7987-pwm";
developer2de1f362025-01-23 16:55:01 +0800[diff] [blame]393 reg = <0 0x10048000 0 0x1000>;
394 #pwm-cells = <2>;
395 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
396 <&infracfg CLK_INFRA_66M_PWM_HCK>,
developer5551adc2025-03-07 11:22:23 +0800[diff] [blame]397 <&infracfg CLK_INFRA_66M_PWM_HCK>,
398 <&infracfg CLK_INFRA_66M_PWM_HCK>,
399 <&infracfg CLK_INFRA_66M_PWM_HCK>;
400 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
developer2de1f362025-01-23 16:55:01 +0800[diff] [blame]401 status = "disabled";
402 };
403
404 uart0: serial@11000000 {
405 compatible = "mediatek,mt7986-uart",
406 "mediatek,mt6577-uart";
407 reg = <0 0x11000000 0 0x100>;
408 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&infracfg CLK_INFRA_52M_UART0_CK>,
410 <&infracfg CLK_INFRA_66M_UART0_PCK>;
411 clock-names = "baud", "bus";
412 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
413 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
414 assigned-clock-parents = <&topckgen
415 CLK_TOP_CB_CKSQ_40M>,
416 <&topckgen CLK_TOP_UART_SEL>;
417 status = "disabled";
418 };
419
420 uart1: serial@11000100 {
421 compatible = "mediatek,mt7986-uart",
422 "mediatek,mt6577-uart";
423 reg = <0 0x11000100 0 0x100>;
424 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&infracfg CLK_INFRA_52M_UART1_CK>,
426 <&infracfg CLK_INFRA_66M_UART1_PCK>;
427 clock-names = "baud", "bus";
428 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
429 <&infracfg CLK_INFRA_MUX_UART1_SEL>;
430 assigned-clock-parents = <&topckgen
431 CLK_TOP_CB_CKSQ_40M>,
432 <&topckgen CLK_TOP_UART_SEL>;
433 status = "disabled";
434 };
435
436 uart2: serial@11000200 {
437 compatible = "mediatek,mt7986-uart",
438 "mediatek,mt6577-uart";
439 reg = <0 0x11000200 0 0x100>;
440 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&infracfg CLK_INFRA_52M_UART2_CK>,
442 <&infracfg CLK_INFRA_66M_UART2_PCK>;
443 clock-names = "baud", "bus";
444 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
445 <&infracfg CLK_INFRA_MUX_UART2_SEL>;
446 assigned-clock-parents = <&topckgen
447 CLK_TOP_CB_CKSQ_40M>,
448 <&topckgen CLK_TOP_UART_SEL>;
449 status = "disabled";
450 };
451
452 i2c0: i2c@11003000 {
453 compatible = "mediatek,mt7988-i2c",
454 "mediatek,mt7981-i2c";
455 reg = <0 0x11003000 0 0x1000>,
456 <0 0x10217080 0 0x80>;
457 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
458 clock-div = <1>;
459 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
460 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
461 clock-names = "main", "dma";
462 #address-cells = <1>;
463 #size-cells = <0>;
464 status = "disabled";
465 };
466
467 spi0: spi@11007800 {
468 compatible = "mediatek,ipm-spi-quad",
469 "mediatek,spi-ipm";
470 reg = <0 0x11007800 0 0x100>;
471 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&topckgen CLK_TOP_CB_M_D2>,
473 <&topckgen CLK_TOP_SPI_SEL>,
474 <&infracfg CLK_INFRA_104M_SPI0>,
475 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
476 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
477 <&infracfg CLK_INFRA_MUX_SPI0_SEL>;
478 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
479 <&topckgen CLK_TOP_SPI_SEL>;
480 clock-names = "parent-clk", "sel-clk", "spi-clk",
481 "hclk";
482 status = "disabled";
483 };
484
485 spi1: spi@11008800 {
486 compatible = "mediatek,ipm-spi-single",
487 "mediatek,spi-ipm";
488 reg = <0 0x11008800 0 0x100>;
489 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&topckgen CLK_TOP_CB_M_D2>,
491 <&topckgen CLK_TOP_SPI_SEL>,
492 <&infracfg CLK_INFRA_104M_SPI1>,
493 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
494 assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
495 <&infracfg CLK_INFRA_MUX_SPI1_SEL>;
496 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
497 <&topckgen
498 CLK_TOP_SPIM_MST_SEL>;
499 clock-names = "parent-clk", "sel-clk", "spi-clk",
500 "hclk";
501 status = "disabled";
502 };
503
504 spi2: spi@11009800 {
505 compatible = "mediatek,ipm-spi-quad",
506 "mediatek,spi-ipm";
507 reg = <0 0x11009800 0 0x100>;
508 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&topckgen CLK_TOP_CB_M_D2>,
510 <&topckgen CLK_TOP_SPI_SEL>,
511 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
512 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
513 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
514 <&infracfg
515 CLK_INFRA_MUX_SPI2_BCK_SEL>;
516 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
517 <&topckgen CLK_TOP_SPI_SEL>;
518 clock-names = "parent-clk", "sel-clk", "spi-clk",
519 "hclk";
520 status = "disabled";
521 };
522
523 lvts: lvts@1100a000 {
524 compatible = "mediatek,mt7987-lvts";
525 #thermal-sensor-cells = <1>;
526 reg = <0 0x1100a000 0 0x1000>;
527 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
528 clock-names = "lvts_clk";
529 nvmem-cells = <&lvts_calibration>;
530 nvmem-cell-names = "e_data1";
531 status = "disabled";
532 };
533
534 usbtphy: usb-phy@11c50000 {
535 compatible = "mediatek,mt7987",
536 "mediatek,generic-tphy-v2";
537 #address-cells = <2>;
538 #size-cells = <2>;
539 ranges;
540
541 tphyu2port0: usb-phy@11c50000 {
542 reg = <0 0x11c50000 0 0x700>;
543 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
544 clock-names = "ref";
545 #phy-cells = <1>;
546
547 auto_load_valid;
548 nvmem-cells = <&u2_intr_p0>,
549 <&u2_auto_load_valid_p0>;
550 nvmem-cell-names = "intr", "auto_load_valid";
551 };
552
553 tphyu3port0: usb-phy@11c50700 {
554 reg = <0 0x11c50700 0 0x900>;
555 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
556 clock-names = "ref";
557 #phy-cells = <1>;
558
559 auto_load_valid;
560 nvmem-cells = <&comb_intr_p0>,
561 <&comb_rx_imp_p0>,
562 <&comb_tx_imp_p0>,
563 <&comb_auto_load_valid>;
564 nvmem-cell-names = "intr", "rx_imp", "tx_imp",
565 "auto_load_valid";
566
567 /* MT7987: 4'b0010 default USB30
568 * Don't change the '0'
569 */
570 mediatek,syscon-type = <&topmisc 0x218 0>;
571
572 status = "disabled";
573 };
574 };
575
576 xhci: xhci@11200000 {
577 compatible = "mediatek,mt7987-xhci",
578 "mediatek,mtk-xhci";
579 reg = <0 0x11200000 0 0x2e00>,
580 <0 0x11203e00 0 0x0100>;
581 reg-names = "mac", "ippc";
582 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
583 usb2-lpm-disable;
584 status = "disabled";
585 };
586
587 afe: audio-controller@11210000 {
588 compatible = "mediatek,mt79xx-audio";
589 reg = <0 0x11210000 0 0x9000>;
590 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
592 <&infracfg CLK_INFRA_AUD_26M>,
593 <&infracfg CLK_INFRA_AUD_L>,
594 <&infracfg CLK_INFRA_AUD_AUD>,
595 <&infracfg CLK_INFRA_AUD_EG2>,
596 <&topckgen CLK_TOP_AUD_SEL>,
597 <&topckgen CLK_TOP_AUD_I2S_M>;
598 clock-names = "aud_bus_ck",
599 "aud_26m_ck",
600 "aud_l_ck",
601 "aud_aud_ck",
602 "aud_eg2_ck",
603 "aud_sel",
604 "aud_i2s_m";
605 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
606 <&topckgen CLK_TOP_A1SYS_SEL>,
607 <&topckgen CLK_TOP_AUD_L_SEL>,
608 <&topckgen CLK_TOP_A_TUNER_SEL>;
609 assigned-clock-parents = <&apmixedsys
610 CLK_APMIXED_APLL2>,
611 <&topckgen
612 CLK_TOP_CB_APLL2_D4>,
613 <&apmixedsys
614 CLK_APMIXED_APLL2>,
615 <&topckgen
616 CLK_TOP_CB_APLL2_D4>;
617 status = "disabled";
618 };
619
620 mmc0: mmc@11230000 {
621 #address-cells = <1>;
622 #size-cells = <0>;
623 compatible = "mediatek,mt7986-mmc";
624 reg = <0 0x11230000 0 0x1000>,
625 <0 0x11f50000 0 0x1000>;
626 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&topckgen CLK_TOP_EMMC_200M_SEL>,
628 <&infracfg CLK_INFRA_MSDC400>,
629 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
630 <&infracfg CLK_INFRA_MSDC2_HCK>,
631 <&infracfg CLK_INFRA_MSDC200_SRC>,
632 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
633 clock-names = "source", "bus_clk", "axi_cg", "hclk",
634 "source_cg", "ahb_cg";
635 status = "disabled";
636 };
637
638 wed: wed {
639 compatible = "mediatek,wed";
640 wed_num = <1>;
641 };
642
643 wed0: wed0@15010000 {
644 compatible = "mediatek,wed0";
645 /* add this property for wed get the pci slot number */
646 pci_slot_map = <0>;
647 reg = <0 0x15010000 0 0x2000>;
648 interrupt-parent = <&gic>;
649 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
650 };
651
652 wdma: wdma@15104800 {
653 compatible = "mediatek,wed-wdma";
654 reg = <0 0x15104800 0 0x400>;
655 };
656
657 pcie0: pcie@11280000 {
658 compatible = "mediatek,mt7988-pcie",
659 "mediatek,mt7987-pcie",
660 "mediatek,mt7986-pcie";
661 device_type = "pci";
662 #address-cells = <3>;
663 #size-cells = <2>;
664 reg = <0 0x11280000 0 0x2000>;
665 reg-names = "pcie-mac";
666 linux,pci-domain = <0>;
667 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
668 bus-range = <0x00 0xff>;
669 ranges = <0x81000000 0x00 0x20000000 0x00
670 0x20000000 0x00 0x00200000>,
671 <0x82000000 0x00 0x20200000 0x00
672 0x20200000 0x00 0x0fe00000>;
673 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
674 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
675 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
676 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
677 clock-names = "pl_250m", "tl_26m", "peri_26m",
678 "top_133m";
679 status = "disabled";
680 #interrupt-cells = <1>;
681 interrupt-map-mask = <0 0 0 0x7>;
682 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
683 <0 0 0 2 &pcie_intc2 1>,
684 <0 0 0 3 &pcie_intc2 2>,
685 <0 0 0 4 &pcie_intc2 3>;
686 pcie_intc2: interrupt-controller {
687 #address-cells = <0>;
688 #interrupt-cells = <1>;
689 interrupt-controller;
690 };
691 };
692
693 pcie1: pcie@11290000 {
694 compatible = "mediatek,mt7988-pcie",
695 "mediatek,mt7987-pcie",
696 "mediatek,mt7986-pcie";
697 device_type = "pci";
698 #address-cells = <3>;
699 #size-cells = <2>;
700 reg = <0 0x11290000 0 0x2000>;
701 reg-names = "pcie-mac";
702 linux,pci-domain = <1>;
703 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
704 bus-range = <0x00 0xff>;
705 ranges = <0x81000000 0x00 0x30000000 0x00
706 0x30000000 0x00 0x00200000>,
707 <0x82000000 0x00 0x30200000 0x00
708 0x30200000 0x00 0x0fe00000>;
709 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
710 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
711 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
712 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
713 clock-names = "pl_250m", "tl_26m", "peri_26m",
714 "top_133m";
715 status = "disabled";
716 #interrupt-cells = <1>;
717 interrupt-map-mask = <0 0 0 0x7>;
718 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
719 <0 0 0 2 &pcie_intc1 1>,
720 <0 0 0 3 &pcie_intc1 2>,
721 <0 0 0 4 &pcie_intc1 3>;
722 pcie_intc1: interrupt-controller {
723 #address-cells = <0>;
724 #interrupt-cells = <1>;
725 interrupt-controller;
726 };
727 slot1: pcie@0,0 {
728 reg = <0x0000 0 0 0 0>;
729 };
730 };
731
732 topmisc: topmisc@10021000 {
733 compatible = "mediatek,mt7987-topmisc", "syscon",
734 "mediatek,mt7987-power-controller";
735 reg = <0 0x10021000 0 0x10000>;
736 #clock-cells = <1>;
737 #power-domain-cells = <1>;
738 #address-cells = <1>;
739 #size-cells = <0>;
740 /* power domain of the SoC */
741 /* eth2p5@MT7988_POWER_DOMAIN_ETH2P5 {
742 * reg = <MT7988_POWER_DOMAIN_ETH2P5>;
743 * #power-domain-cells = <0>;
744 * };
745 */
746 };
747
748 efuse: efuse@11d30000 {
749 compatible = "mediatek,efuse";
750 reg = <0 0x11d30000 0 0x1000>;
751 #address-cells = <1>;
752 #size-cells = <1>;
753
754 lvts_calibration: calib@918 {
755 reg = <0x918 0x10>;
756 };
757
758 comb_auto_load_valid: usb3-alv-imp@8ee {
759 reg = <0x8ee 1>;
760 bits = <0 1>;
761 };
762
763 comb_rx_imp_p0: usb3-rx-imp@8ec {
764 reg = <0x8ec 1>;
765 bits = <0 5>;
766 };
767
768 comb_tx_imp_p0: usb3-tx-imp@8ec {
769 reg = <0x8ec 2>;
770 bits = <5 5>;
771 };
772
773 comb_intr_p0: usb3-intr@8ec {
774 reg = <0x8ec 2>;
775 bits = <10 6>;
776 };
777
778 u2_auto_load_valid_p0: usb2-alv-p0@8cc {
779 reg = <0x8cc 1>;
780 bits = <0 1>;
781 };
782
783 u2_intr_p0: usb2-intr-p0@8cc {
784 reg = <0x8cc 1>;
785 bits = <1 5>;
786 };
787 };
788
789 devapc: devapc@1a110000 {
790 compatible = "mediatek,mt7987-devapc";
791 reg = <0 0x1a110000 0 0x1000>;
792 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
793 };
794 };
795
796 netsys: soc_netsys {
797 #address-cells = <2>;
798 #size-cells = <2>;
799 compatible = "simple-bus";
800 ranges;
801 };
802};