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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / dts / mt7987-pinctrl-u-boot.dtsi
blob: 991f38efef9289b96efca727fa73a10be837788b [file] [log] [blame]
developer2de1f362025-01-23 16:55:01 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2025 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/pinctrl/mt65xx.h>
9
10&pio {
11 /delete-node/ mmc-pins-default;
12 /delete-node/ mmc-pins-uhs;
13 /delete-node/ sd-pins-default;
14 /delete-node/ sd-pins-uhs;
15 /delete-node/ spi0-pins;
16 /delete-node/ spi2-pins;
17
18 mmc_pins_default: mmc0default {
19 mux {
20 function = "flash";
21 groups = "emmc_45";
22 };
23
24 conf-cmd-dat {
25 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
26 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
27 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
28 input-enable;
29 drive-strength = <MTK_DRIVE_4mA>;
30 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
31 };
32
33 conf-clk {
34 pins = "SPI1_CS";
35 drive-strength = <MTK_DRIVE_6mA>;
36 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
37 };
38
39 conf-rst {
40 pins = "USB_VBUS";
41 drive-strength = <MTK_DRIVE_4mA>;
42 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
43 };
44 };
45
46 mmc_pins_uhs: mmc-pins-uhs {
47 mux {
48 function = "flash";
49 groups = "emmc_45";
50 };
51 conf-cmd-dat {
52 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
53 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
54 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
55 input-enable;
56 drive-strength = <MTK_DRIVE_4mA>;
57 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
58 };
59 conf-clk {
60 pins = "SPI1_CS";
61 drive-strength = <MTK_DRIVE_6mA>;
62 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
63 };
64 conf-rst {
65 pins = "USB_VBUS";
66 drive-strength = <MTK_DRIVE_4mA>;
67 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
68 };
69 };
70
71 sd_pins_default: sd-pins-default {
72 mux {
73 function = "flash";
74 groups = "sd";
75 };
76 conf-cmd-dat {
77 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
78 "SPI0_CS", "SPI1_MISO";
79 input-enable;
80 drive-strength = <MTK_DRIVE_4mA>;
81 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
82 };
83 conf-clk {
84 pins = "SPI1_CS";
85 drive-strength = <MTK_DRIVE_6mA>;
86 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
87 };
88 };
89
90 sd_pins_uhs: sd-pins-uhs {
91 mux {
92 function = "flash";
93 groups = "sd";
94 };
95 conf-cmd-dat {
96 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
97 "SPI0_CS", "SPI1_MISO";
98 input-enable;
99 drive-strength = <MTK_DRIVE_4mA>;
100 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
101 };
102 conf-clk {
103 pins = "SPI1_CS";
104 drive-strength = <MTK_DRIVE_6mA>;
105 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
106 };
107 };
108
109 spi0_flash_pins: spi0-pins {
110 mux {
111 function = "spi";
112 groups = "spi0", "spi0_wp_hold";
113 };
114
115 conf-pu {
116 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
117 drive-strength = <MTK_DRIVE_8mA>;
118 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
119 };
120
121 conf-pd {
122 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
123 drive-strength = <MTK_DRIVE_8mA>;
124 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
125 };
126 };
127
128 spi2_flash_pins: spi2-pins {
129 mux {
130 function = "spi";
131 groups = "spi2", "spi2_wp_hold";
132 };
133
134 conf-pu {
135 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
136 drive-strength = <MTK_DRIVE_8mA>;
137 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
138 };
139
140 conf-pd {
141 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
142 drive-strength = <MTK_DRIVE_8mA>;
143 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
144 };
145 };
146};