| Garrett Giordano | e1b8c39 | 2024-11-18 15:16:05 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| 2 | /* |
| 3 | * phyCORE-AM62Ax dts file for SPLs |
| 4 | * Copyright (C) 2024 PHYTEC America LLC |
| 5 | * Author: Garrett Giordano <ggiordano@phytec.com> |
| 6 | * |
| 7 | * Product homepage: |
| 8 | * https://www.phytec.com/product/phycore-am62ax |
| 9 | */ |
| 10 | |
| 11 | #include "k3-am62a-phycore-som-binman.dtsi" |
| 12 | |
| 13 | / { |
| 14 | chosen { |
| 15 | stdout-path = "serial2:115200n8"; |
| 16 | tick-timer = &main_timer0; |
| 17 | }; |
| 18 | |
| 19 | aliases { |
| 20 | mmc0 = &sdhci0; |
| 21 | mmc1 = &sdhci1; |
| 22 | }; |
| 23 | |
| 24 | memory@80000000 { |
| 25 | bootph-all; |
| 26 | }; |
| 27 | }; |
| 28 | |
| 29 | &cbass_main { |
| 30 | bootph-all; |
| 31 | }; |
| 32 | |
| 33 | &cbass_mcu { |
| 34 | bootph-all; |
| 35 | }; |
| 36 | |
| 37 | &cbass_wakeup { |
| 38 | bootph-all; |
| 39 | }; |
| 40 | |
| 41 | &chipid { |
| 42 | bootph-all; |
| 43 | }; |
| 44 | |
| 45 | &cpsw3g { |
| 46 | bootph-all; |
| 47 | ethernet-ports { |
| 48 | bootph-all; |
| 49 | }; |
| 50 | }; |
| 51 | |
| 52 | &cpsw3g_mdio { |
| 53 | bootph-all; |
| 54 | }; |
| 55 | |
| 56 | &cpsw3g_phy1 { |
| 57 | bootph-all; |
| 58 | }; |
| 59 | |
| 60 | &cpsw3g_phy3 { |
| 61 | bootph-all; |
| 62 | }; |
| 63 | |
| 64 | &cpsw_port1 { |
| 65 | bootph-all; |
| 66 | }; |
| 67 | |
| 68 | &cpsw_port2 { |
| Daniel Schultz | e6b018d2 | 2025-03-25 04:58:20 +0100 | [diff] [blame] | 69 | status = "disabled"; |
| Garrett Giordano | e1b8c39 | 2024-11-18 15:16:05 -0800 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | &dmsc { |
| 73 | bootph-all; |
| 74 | }; |
| 75 | |
| 76 | &dmss { |
| 77 | bootph-all; |
| 78 | }; |
| 79 | |
| 80 | &fss { |
| 81 | bootph-all; |
| 82 | }; |
| 83 | |
| 84 | &k3_pds { |
| 85 | bootph-all; |
| 86 | }; |
| 87 | |
| 88 | &k3_clks { |
| 89 | bootph-all; |
| 90 | }; |
| 91 | |
| 92 | &k3_reset { |
| 93 | bootph-all; |
| 94 | }; |
| 95 | |
| 96 | &main_bcdma { |
| 97 | bootph-all; |
| 98 | reg = <0x00 0x485c0100 0x00 0x100>, |
| 99 | <0x00 0x4c000000 0x00 0x20000>, |
| 100 | <0x00 0x4a820000 0x00 0x20000>, |
| 101 | <0x00 0x4aa40000 0x00 0x20000>, |
| 102 | <0x00 0x4bc00000 0x00 0x100000>, |
| 103 | <0x00 0x48600000 0x00 0x8000>, |
| 104 | <0x00 0x484a4000 0x00 0x2000>, |
| 105 | <0x00 0x484c2000 0x00 0x2000>; |
| 106 | reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", |
| 107 | "ringrt", "cfg", "tchan", "rchan"; |
| 108 | }; |
| 109 | |
| 110 | &main_conf { |
| 111 | bootph-all; |
| 112 | }; |
| 113 | |
| 114 | &main_gpio0 { |
| 115 | bootph-all; |
| 116 | }; |
| 117 | |
| 118 | &main_i2c0 { |
| 119 | bootph-all; |
| 120 | }; |
| 121 | |
| 122 | &main_i2c0_pins_default { |
| 123 | bootph-all; |
| 124 | }; |
| 125 | |
| 126 | &main_mdio1_pins_default { |
| 127 | bootph-all; |
| 128 | }; |
| 129 | |
| 130 | &main_mmc0_pins_default { |
| 131 | bootph-all; |
| 132 | }; |
| 133 | |
| 134 | &main_mmc1_pins_default { |
| 135 | bootph-all; |
| 136 | }; |
| 137 | |
| 138 | &main_pktdma { |
| 139 | bootph-all; |
| 140 | reg = <0x00 0x485c0000 0x00 0x100>, |
| 141 | <0x00 0x4a800000 0x00 0x20000>, |
| 142 | <0x00 0x4aa00000 0x00 0x40000>, |
| 143 | <0x00 0x4b800000 0x00 0x400000>, |
| 144 | <0x00 0x485e0000 0x00 0x20000>, |
| 145 | <0x00 0x484a0000 0x00 0x4000>, |
| 146 | <0x00 0x484c0000 0x00 0x2000>, |
| 147 | <0x00 0x48430000 0x00 0x4000>; |
| 148 | reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", |
| 149 | "cfg", "tchan", "rchan", "rflow"; |
| 150 | }; |
| 151 | |
| 152 | &main_pmx0 { |
| 153 | bootph-all; |
| 154 | }; |
| 155 | |
| 156 | &main_rgmii1_pins_default { |
| 157 | bootph-all; |
| 158 | }; |
| 159 | |
| 160 | &main_timer0 { |
| 161 | bootph-all; |
| 162 | }; |
| 163 | |
| 164 | &main_uart0 { |
| 165 | bootph-all; |
| 166 | }; |
| 167 | |
| 168 | &main_uart0_pins_default { |
| 169 | bootph-all; |
| 170 | }; |
| 171 | |
| 172 | &main_uart1 { |
| 173 | bootph-all; |
| 174 | }; |
| 175 | |
| 176 | &mcu_pmx0 { |
| 177 | bootph-all; |
| 178 | }; |
| 179 | |
| 180 | &ospi0_pins_default { |
| 181 | bootph-all; |
| 182 | }; |
| 183 | |
| 184 | &ospi0 { |
| 185 | bootph-all; |
| 186 | flash@0 { |
| 187 | bootph-all; |
| 188 | partitions { |
| 189 | compatible = "fixed-partitions"; |
| 190 | #address-cells = <1>; |
| 191 | #size-cells = <1>; |
| 192 | |
| 193 | partition@0 { |
| 194 | label = "ospi.tiboot3"; |
| 195 | reg = <0x00000 0x80000>; |
| 196 | }; |
| 197 | partition@80000 { |
| 198 | label = "ospi.tispl"; |
| 199 | reg = <0x080000 0x200000>; |
| 200 | }; |
| 201 | partition@280000 { |
| 202 | label = "ospi.u-boot"; |
| 203 | reg = <0x280000 0x400000>; |
| 204 | }; |
| 205 | partition@680000 { |
| 206 | label = "ospi.env"; |
| 207 | reg = <0x680000 0x40000>; |
| 208 | }; |
| 209 | partition@6c0000 { |
| 210 | label = "ospi.env.backup"; |
| 211 | reg = <0x6c0000 0x40000>; |
| 212 | }; |
| 213 | }; |
| 214 | }; |
| 215 | }; |
| 216 | |
| 217 | &phy_gmii_sel { |
| 218 | bootph-all; |
| 219 | }; |
| 220 | |
| 221 | &sdhci0 { |
| 222 | bootph-all; |
| 223 | }; |
| 224 | |
| 225 | &sdhci1 { |
| 226 | bootph-all; |
| 227 | }; |
| 228 | |
| 229 | &secure_proxy_main { |
| 230 | bootph-all; |
| 231 | }; |
| 232 | |
| 233 | &usbss0 { |
| 234 | bootph-all; |
| 235 | }; |
| 236 | |
| 237 | &usb0 { |
| 238 | dr_mode = "peripheral"; |
| 239 | bootph-all; |
| 240 | }; |
| 241 | |
| Wadim Egorov | 351e3bc | 2025-03-05 05:58:33 +0100 | [diff] [blame] | 242 | &usb0_phy_ctrl { |
| 243 | bootph-all; |
| 244 | }; |
| 245 | |
| Garrett Giordano | e1b8c39 | 2024-11-18 15:16:05 -0800 | [diff] [blame] | 246 | &vcc_3v3_mmc { |
| 247 | bootph-all; |
| 248 | }; |
| 249 | |
| 250 | &wkup_conf { |
| 251 | bootph-all; |
| 252 | }; |
| 253 | |
| 254 | &wkup_uart0 { |
| 255 | bootph-all; |
| 256 | }; |