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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / dts / imx8mp-toradex-smarc.dtsi
blob: 0a8b9eee5ed9e3df8eb2426f1900a6ba8ad76011 [file] [log] [blame]
Vitor Soares987c7362025-04-07 14:04:36 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/* Copyright (C) 2025 Toradex */
3
4#include <dt-bindings/phy/phy-imx8-pcie.h>
5#include <dt-bindings/net/ti-dp83867.h>
6#include "imx8mp.dtsi"
7
8/ {
9 aliases {
10 can0 = &flexcan2;
11 can1 = &flexcan1;
12 ethernet0 = &eqos;
13 ethernet1 = &fec;
14 mmc0 = &usdhc3;
15 mmc1 = &usdhc2;
16 mmc2 = &usdhc1;
17 rtc0 = &rtc_i2c;
18 rtc1 = &snvs_rtc;
19 serial0 = &uart1;
20 serial1 = &uart4;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 };
24
25 chosen {
26 stdout-path = &uart4;
27 };
28
29 connector {
30 compatible = "gpio-usb-b-connector", "usb-b-connector";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_usb0_id>;
33 id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
34 label = "USB0";
35 self-powered;
36 type = "micro";
37 vbus-supply = <&reg_usb0_vbus>;
38
39 port {
40 usb_dr_connector: endpoint {
41 remote-endpoint = <&usb3_0_dwc>;
42 };
43 };
44 };
45
46 gpio-keys {
47 compatible = "gpio-keys";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_sleep>;
50
51 smarc_key_sleep: key-sleep {
52 gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
53 label = "SMARC_SLEEP#";
54 wakeup-source;
55 linux,code = <KEY_SLEEP>;
56 };
57 };
58
59 reg_usb0_vbus: regulator-usb0-vbus {
60 compatible = "regulator-fixed";
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_usb0_en_oc>;
63 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
64 enable-active-high;
65 regulator-name = "USB0_EN_OC#";
66 };
67
68 reg_usb1_vbus: regulator-usb1-vbus {
69 compatible = "regulator-fixed";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_usb1_en_oc>;
72 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
73 enable-active-high;
74 regulator-name = "USB2_EN_OC#";
75 };
76
77 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
78 compatible = "regulator-fixed";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
81 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
82 enable-active-high;
83 off-on-delay-us = <100000>;
84 regulator-max-microvolt = <3300000>;
85 regulator-min-microvolt = <3300000>;
86 regulator-name = "3V3_SD";
87 startup-delay-us = <20000>;
88 };
89
90 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
91 compatible = "regulator-gpio";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_usdhc2_vsel>;
94 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
95 regulator-max-microvolt = <3300000>;
96 regulator-min-microvolt = <1800000>;
97 states = <1800000 0x1>,
98 <3300000 0x0>;
99 regulator-name = "PMIC_USDHC_VSELECT";
100 vin-supply = <&reg_sd_3v3_1v8>;
101 };
102
103 reg_wifi_en: regulator-wifi-en {
104 compatible = "regulator-fixed";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
107 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
108 enable-active-high;
109 regulator-max-microvolt = <3300000>;
110 regulator-min-microvolt = <3300000>;
111 regulator-name = "CTRL_EN_WIFI";
112 startup-delay-us = <2000>;
113 };
114
115 reserved-memory {
116 linux,cma {
117 size = <0 0x20000000>;
118 alloc-ranges = <0 0x40000000 0 0x80000000>;
119 };
120 };
121
122 sound_hdmi: sound-hdmi {
123 compatible = "fsl,imx-audio-hdmi";
124 model = "audio-hdmi";
125 audio-cpu = <&aud2htx>;
126 hdmi-out;
127 status = "disabled";
128 };
129};
130
131&A53_0 {
132 cpu-supply = <&reg_vdd_arm>;
133};
134
135&A53_1 {
136 cpu-supply = <&reg_vdd_arm>;
137};
138
139&A53_2 {
140 cpu-supply = <&reg_vdd_arm>;
141};
142
143&A53_3 {
144 cpu-supply = <&reg_vdd_arm>;
145};
146
147/* SMARC SPI0 */
148&ecspi1 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_ecspi1>;
151 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio4 28 GPIO_ACTIVE_LOW>;
152};
153
154/* SMARC SPI1 */
155&ecspi2 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>;
158 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
159 <&gpio4 3 GPIO_ACTIVE_LOW>,
160 <&gpio3 6 GPIO_ACTIVE_LOW>;
161 status = "okay";
162
163 tpm@2 {
164 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
165 reg = <2>;
166 spi-max-frequency = <18500000>;
167 };
168};
169
170/* SMARC GBE0 */
171&eqos {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_eqos>,
174 <&pinctrl_eth_mdio>,
175 <&pinctrl_eqos_1588_event>;
176 phy-handle = <&eqos_phy>;
177 phy-mode = "rgmii-id";
178 snps,force_thresh_dma_mode;
179 snps,mtl-rx-config = <&mtl_rx_setup>;
180 snps,mtl-tx-config = <&mtl_tx_setup>;
181
182 mdio: mdio {
183 compatible = "snps,dwmac-mdio";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 };
187
188 mtl_rx_setup: rx-queues-config {
189 snps,rx-queues-to-use = <5>;
190
191 queue0 {
192 snps,dcb-algorithm;
193 snps,priority = <0x1>;
194 snps,map-to-dma-channel = <0>;
195 };
196
197 queue1 {
198 snps,dcb-algorithm;
199 snps,priority = <0x2>;
200 snps,map-to-dma-channel = <1>;
201 };
202
203 queue2 {
204 snps,dcb-algorithm;
205 snps,priority = <0x4>;
206 snps,map-to-dma-channel = <2>;
207 };
208
209 queue3 {
210 snps,dcb-algorithm;
211 snps,priority = <0x8>;
212 snps,map-to-dma-channel = <3>;
213 };
214
215 queue4 {
216 snps,dcb-algorithm;
217 snps,priority = <0xf0>;
218 snps,map-to-dma-channel = <4>;
219 };
220 };
221
222 mtl_tx_setup: tx-queues-config {
223 snps,tx-queues-to-use = <5>;
224
225 queue0 {
226 snps,dcb-algorithm;
227 snps,priority = <0x1>;
228 };
229
230 queue1 {
231 snps,dcb-algorithm;
232 snps,priority = <0x2>;
233 };
234
235 queue2 {
236 snps,dcb-algorithm;
237 snps,priority = <0x4>;
238 };
239
240 queue3 {
241 snps,dcb-algorithm;
242 snps,priority = <0x8>;
243 };
244
245 queue4 {
246 snps,dcb-algorithm;
247 snps,priority = <0xf0>;
248 };
249 };
250};
251
252/* SMARC GBE1 */
253&fec {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_1588_event>;
256 phy-handle = <&fec_phy>;
257 phy-mode = "rgmii-id";
258 fsl,magic-packet;
259};
260
261/* SMARC CAN1 */
262&flexcan1 {
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_flexcan1>;
265};
266
267/* SMARC CAN0 */
268&flexcan2 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_flexcan2>;
271};
272
273&gpio1 {
274 gpio-line-names = "SMARC_GPIO7", /* 0 */
275 "SMARC_GPIO8",
276 "",
277 "PMIC_INT#",
278 "PMIC_USDHC_VSELECT",
279 "SMARC_GPIO9",
280 "SMARC_GPIO10",
281 "SMARC_GPIO11",
282 "SMARC_GPIO12",
283 "",
284 "SMARC_GPIO5", /* 10 */
285 "",
286 "SMARC_USB0_EN_OC#",
287 "SMARC_GPIO13",
288 "SMARC_USB2_EN_OC#";
289};
290
291&gpio2 {
292 gpio-line-names = "", /* 0 */
293 "",
294 "",
295 "",
296 "",
297 "",
298 "",
299 "",
300 "",
301 "",
302 "", /* 10 */
303 "",
304 "SMARC_SDIO_CD#",
305 "",
306 "",
307 "",
308 "",
309 "",
310 "",
311 "SMARC_SDIO_PWR_EN",
312 "SMARC_SDIO_WP"; /* 20 */
313};
314
315&gpio3 {
316 gpio-line-names = "ETH_0_INT#", /* 0 */
317 "SLEEP#",
318 "",
319 "",
320 "",
321 "",
322 "TPM_CS#",
323 "LVDS_DSI_SEL",
324 "MCU_INT#",
325 "GPIO_EX_INT#",
326 "", /* 10 */
327 "",
328 "",
329 "",
330 "",
331 "",
332 "SMARC_SMB_ALERT#",
333 "",
334 "",
335 "",
336 "SMARC_I2C_PM_DAT", /* 20 */
337 "",
338 "",
339 "",
340 "",
341 "",
342 "",
343 "",
344 "SMARC_I2C_PM_CK";
345
346 lvds_dsi_mux_hog: lvds-dsi-mux-hog {
347 gpio-hog;
348 gpios = <7 GPIO_ACTIVE_HIGH>;
349 line-name = "LVDS_DSI_SEL";
350 /* LVDS_DSI_SEL as DSI */
351 output-low;
352 };
353};
354
355&gpio4 {
356 gpio-line-names = "SMARC_PCIE_WAKE#", /* 0 */
357 "",
358 "",
359 "SMARC_SPI1_CS1#",
360 "",
361 "",
362 "",
363 "",
364 "",
365 "",
366 "", /* 10 */
367 "",
368 "",
369 "",
370 "",
371 "",
372 "",
373 "",
374 "SMARC_GPIO4",
375 "SMARC_PCIE_A_RST#",
376 "", /* 20 */
377 "",
378 "",
379 "",
380 "",
381 "",
382 "",
383 "",
384 "SMARC_SPI0_CS1#",
385 "SMARC_GPIO6";
386};
387
388&gpio5 {
389 gpio-line-names = "", /* 0 */
390 "",
391 "SMARC_USB0_OTG_ID",
392 "SMARC_I2C_CAM1_CK",
393 "SMARC_I2C_CAM1_DAT",
394 "",
395 "",
396 "",
397 "",
398 "SMARC_SPI0_CS0#",
399 "", /* 10 */
400 "",
401 "",
402 "SMARC_SPI1_CS0#",
403 "CTRL_I2C_SCL",
404 "CTRL_I2C_SDA",
405 "SMARC_I2C_LCD_CK",
406 "SMARC_I2C_LCD_DAT",
407 "SMARC_I2C_CAM0_CK",
408 "SMARC_I2C_CAM0_DAT",
409 "SMARC_I2C_GP_CK", /* 20 */
410 "SMARC_I2C_GP_DAT";
411};
412
413/* SMARC HDMI */
414&hdmi_tx {
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_hdmi>;
417};
418
419/* On-module I2C */
420&i2c1 {
421 pinctrl-names = "default", "gpio";
422 pinctrl-0 = <&pinctrl_i2c1>;
423 pinctrl-1 = <&pinctrl_i2c1_gpio>;
424 clock-frequency = <400000>;
425 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
426 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
427 single-master;
428 status = "okay";
429
430 som_gpio_expander: gpio-expander@21 {
431 compatible = "nxp,pcal6408";
432 reg = <0x21>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_pcal6408>;
435 #interrupt-cells = <2>;
436 interrupt-controller;
437 interrupt-parent = <&gpio3>;
438 interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
439 #gpio-cells = <2>;
440 gpio-controller;
441 gpio-line-names =
442 "SMARC_GPIO0",
443 "SMARC_GPIO1",
444 "SMARC_GPIO2",
445 "SMARC_GPIO3",
446 "SMARC_LCD0_VDD_EN",
447 "SMARC_LCD0_BKLT_EN",
448 "SMARC_LCD1_VDD_EN",
449 "SMARC_LCD1_BKLT_EN";
450 };
451
452 pca9450: pmic@25 {
453 compatible = "nxp,pca9450c";
454 reg = <0x25>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_pmic>;
457 interrupt-parent = <&gpio1>;
458 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
459
460 regulators {
461 BUCK1 {
462 regulator-always-on;
463 regulator-boot-on;
464 regulator-max-microvolt = <1000000>;
465 regulator-min-microvolt = <805000>;
466 regulator-name = "+VDD_SOC (PMIC BUCK1)";
467 regulator-ramp-delay = <3125>;
468 };
469
470 reg_vdd_arm: BUCK2 {
471 regulator-always-on;
472 regulator-boot-on;
473 regulator-max-microvolt = <1000000>;
474 regulator-min-microvolt = <805000>;
475 regulator-name = "+VDD_ARM (PMIC BUCK2)";
476 regulator-ramp-delay = <3125>;
477 nxp,dvs-run-voltage = <950000>;
478 nxp,dvs-standby-voltage = <850000>;
479 };
480
481 reg_3v3: BUCK4 {
482 regulator-always-on;
483 regulator-boot-on;
484 regulator-max-microvolt = <3300000>;
485 regulator-min-microvolt = <3300000>;
486 regulator-name = "+V3.3 (PMIC BUCK4)";
487 };
488
489 reg_1v8: BUCK5 {
490 regulator-always-on;
491 regulator-boot-on;
492 regulator-max-microvolt = <1800000>;
493 regulator-min-microvolt = <1800000>;
494 regulator-name = "+V1.8 (PMIC BUCK5)";
495 };
496
497 BUCK6 {
498 regulator-always-on;
499 regulator-boot-on;
500 regulator-max-microvolt = <1155000>;
501 regulator-min-microvolt = <1045000>;
502 regulator-name = "+VDD_DDR (PMIC BUCK6)";
503 };
504
505 LDO1 {
506 regulator-always-on;
507 regulator-boot-on;
508 regulator-max-microvolt = <1950000>;
509 regulator-min-microvolt = <1710000>;
510 regulator-name = "+V1.8_SNVS (PMIC LDO1)";
511 };
512
513 LDO3 {
514 regulator-always-on;
515 regulator-boot-on;
516 regulator-max-microvolt = <1800000>;
517 regulator-min-microvolt = <1800000>;
518 regulator-name = "+V1.8A (PMIC LDO3)";
519 };
520
521 LDO4 {
522 regulator-always-on;
523 regulator-boot-on;
524 regulator-max-microvolt = <3300000>;
525 regulator-min-microvolt = <3300000>;
526 regulator-name = "+V3.3_ADC (PMIC LDO4)";
527 };
528
529 reg_sd_3v3_1v8: LDO5 {
530 regulator-max-microvolt = <3300000>;
531 regulator-min-microvolt = <1800000>;
532 regulator-name = "+V3.3_1.8_SD (PMIC LDO5)";
533 };
534 };
535 };
536
537 rtc_i2c: rtc@32 {
538 compatible = "epson,rx8130";
539 reg = <0x32>;
540 };
541
542 temperature-sensor@48 {
543 compatible = "ti,tmp1075";
544 reg = <0x48>;
545 };
546
547 eeprom@50 {
548 compatible = "st,24c02", "atmel,24c02";
549 reg = <0x50>;
550 pagesize = <16>;
551 };
552};
553
554/* SMARC I2C_LCD */
555&i2c2 {
556 pinctrl-names = "default", "gpio";
557 pinctrl-0 = <&pinctrl_i2c2>;
558 pinctrl-1 = <&pinctrl_i2c2_gpio>;
559 clock-frequency = <100000>;
560 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
561 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
562 single-master;
563};
564
565/* SMARC I2C_CAM0 */
566&i2c3 {
567 pinctrl-names = "default", "gpio";
568 pinctrl-0 = <&pinctrl_i2c3>;
569 pinctrl-1 = <&pinctrl_i2c3_gpio>;
570 clock-frequency = <400000>;
571 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
572 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
573 single-master;
574};
575
576/* SMARC I2C_GP */
577&i2c4 {
578 pinctrl-names = "default", "gpio";
579 pinctrl-0 = <&pinctrl_i2c4>;
580 pinctrl-1 = <&pinctrl_i2c4_gpio>;
581 clock-frequency = <400000>;
582 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
583 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
584 single-master;
585 status = "okay";
586
587 eeprom@50 {
588 compatible = "st,24c32", "atmel,24c32";
589 reg = <0x50>;
590 pagesize = <32>;
591 };
592};
593
594/* SMARC I2C_CAM1 */
595&i2c5 {
596 pinctrl-names = "default", "gpio";
597 pinctrl-0 = <&pinctrl_i2c5>;
598 pinctrl-1 = <&pinctrl_i2c5_gpio>;
599 clock-frequency = <400000>;
600 scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
601 sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
602 single-master;
603};
604
605/* SMARC I2C_PM */
606&i2c6 {
607 pinctrl-names = "default", "gpio";
608 pinctrl-0 = <&pinctrl_i2c6>;
609 pinctrl-1 = <&pinctrl_i2c6_gpio>;
610 clock-frequency = <400000>;
611 scl-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
612 sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
613 single-master;
614};
615
616&mdio {
617 eqos_phy: ethernet-phy@1 {
618 reg = <1>;
619 interrupt-parent = <&gpio3>;
620 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
621 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
622 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
623 };
624
625 fec_phy: ethernet-phy@2 {
626 reg = <2>;
627 interrupt-parent = <&gpio3>;
628 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
629 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
630 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
631 };
632};
633
634/* SMARC PCIE_A */
635&pcie {
636 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_pcie>;
638 reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
639};
640
641&pcie_phy {
642 clocks = <&hsio_blk_ctrl>;
643 clock-names = "ref";
644 fsl,clkreq-unsupported;
645 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
646};
647
648/* SMARC LCD1_BKLT_PWM */
649&pwm1 {
650 pinctrl-names = "default";
651 pinctrl-0 = <&pinctrl_lcd1_bklt_pwm1>;
652};
653
654/* SMARC LCD0_BKLT_PWM */
655&pwm2 {
656 pinctrl-names = "default";
657 pinctrl-0 = <&pinctrl_lcd0_bklt_pwm2>;
658};
659
660/* SMARC GPIO5 as PWM */
661&pwm3 {
662 pinctrl-names = "default";
663 pinctrl-0 = <&pinctrl_gpio5_pwm>;
664};
665
666&snvs_pwrkey {
667 status = "okay";
668};
669
670/* SMARC SER0 */
671&uart1 {
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_uart1>;
674 uart-has-rtscts;
675};
676
677/* SMARC SER2 */
678&uart2 {
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_uart2>;
681 uart-has-rtscts;
682};
683
684/* On-module Bluetooth, optional SMARC SER3 */
685&uart3 {
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_bt_uart>;
688 uart-has-rtscts;
689 status = "okay";
690
691 som_bt: bluetooth {
692 compatible = "mrvl,88w8997";
693 max-speed = <921600>;
694 };
695};
696
697/* SMARC SER1, used as the Linux Console */
698&uart4 {
699 pinctrl-names = "default";
700 pinctrl-0 = <&pinctrl_uart4>;
701};
702
703/* SMARC USB0 */
704&usb3_0 {
705 fsl,disable-port-power-control;
706};
707
708/* SMARC USB1..4 */
709&usb3_1 {
710 fsl,disable-port-power-control;
711};
712
713&usb3_phy1 {
714 vbus-supply = <&reg_usb1_vbus>;
715};
716
717&usb_dwc3_0 {
718 adp-disable;
719 dr_mode = "otg";
720 hnp-disable;
721 maximum-speed = "high-speed";
722 srp-disable;
723 usb-role-switch;
724
725 port {
726 usb3_0_dwc: endpoint {
727 remote-endpoint = <&usb_dr_connector>;
728 };
729 };
730};
731
732&usb_dwc3_1 {
733 dr_mode = "host";
734};
735
736/* On-module Wi-Fi */
737&usdhc1 {
738 pinctrl-names = "default", "state_100mhz", "state_200mhz";
739 pinctrl-0 = <&pinctrl_usdhc1>;
740 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
741 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
742 keep-power-in-suspend;
743 non-removable;
744 vmmc-supply = <&reg_wifi_en>;
745 status = "okay";
746};
747
748/* SMARC SDIO */
749&usdhc2 {
750 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
751 pinctrl-0 = <&pinctrl_usdhc2>,
752 <&pinctrl_usdhc2_cd>,
753 <&pinctrl_usdhc2_wp>;
754 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
755 <&pinctrl_usdhc2_cd>,
756 <&pinctrl_usdhc2_wp>;
757 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
758 <&pinctrl_usdhc2_cd>,
759 <&pinctrl_usdhc2_wp>;
760 pinctrl-3 = <&pinctrl_usdhc2_sleep>,
761 <&pinctrl_usdhc2_cd_sleep>,
762 <&pinctrl_usdhc2_wp>;
763 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
764 assigned-clock-rates = <400000000>;
765 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
766 vmmc-supply = <&reg_usdhc2_vmmc>;
767 vqmmc-supply = <&reg_usdhc2_vqmmc>;
768 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
769};
770
771/* On-module eMMC */
772&usdhc3 {
773 pinctrl-names = "default", "state_100mhz", "state_200mhz";
774 pinctrl-0 = <&pinctrl_usdhc3>;
775 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
776 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
777 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
778 assigned-clock-rates = <400000000>;
779 bus-width = <8>;
780 non-removable;
781 status = "okay";
782};
783
784&wdog1 {
785 pinctrl-names = "default";
786 pinctrl-0 = <&pinctrl_wdog>;
787 fsl,ext-reset-output;
788 status = "okay";
789};
790
791&iomuxc {
792 /* On-module Bluetooth */
793 pinctrl_bt_uart: btuartgrp {
794 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x1c4>, /* WiFi_UART_TXD */
795 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x1c4>, /* WiFi_UART_RXD */
796 <MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x1c4>, /* WiFi_UART_RTS */
797 <MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x1c4>; /* WiFi_UART_CTS */
798 };
799
800 /* SMARC CAM_MCK */
801 pinctrl_csi_mclk: csimclkgrp {
802 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x16>; /* SMARC S6 - CAM_MCK */
803 };
804
805 /* SMARC SPI0 */
806 pinctrl_ecspi1: ecspi1grp {
807 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SMARC P45 - SPI0_DIN */
808 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SMARC P46 - SPI0_DO */
809 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SMARC P44 - SPI0_CK */
810 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>, /* SMARC P43 - SPI0_CS0# */
811 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SMARC P31 - SPI0_CS1# */
812 };
813
814 /* SMARC SPI1 */
815 pinctrl_ecspi2: ecspi2grp {
816 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c4>, /* SMARC P56 - SPI1_DIN */
817 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x4>, /* SMARC P57 - SPI1_DO */
818 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x4>, /* SMARC P58 - SPI1_CK */
819 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>, /* SMARC P54 - SPI1_CS0# */
820 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c4>; /* SMARC P55 - SPI1_CS1# */
821 };
822
823 /* ETH_0 RGMII (On-module PHY) */
824 pinctrl_eqos: eqosgrp {
825 fsl,pins = <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, /* ETH0_RGMII_RXD0 */
826 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, /* ETH0_RGMII_RXD1 */
827 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, /* ETH0_RGMII_RXD2 */
828 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, /* ETH0_RGMII_RXD3 */
829 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, /* ETH0_RGMII_RXC */
830 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, /* ETH0_RGMII_RX_CTL */
831 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16>, /* ETH0_RGMII_TXD0 */
832 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16>, /* ETH0_RGMII_TXD1 */
833 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16>, /* ETH0_RGMII_TXD2 */
834 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16>, /* ETH0_RGMII_TXD3 */
835 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16>, /* ETH0_RGMII_TX_CTL */
836 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16>; /* ETH0_RGMII_TXC */
837 };
838
839 /* SMARC GBE0_SDP */
840 pinctrl_eqos_1588_event: eqos1588eventgrp {
841 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x4>; /* SMARC P6 - GBE0_SDP */
842 };
843
844 /* ETH_0_MDIO and ETH_0_INT# shared between ETH_PHY0 and ETH_PHY1 */
845 pinctrl_eth_mdio: ethmdiogrp {
846 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2>, /* ETH_0_MDC */
847 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2>, /* ETH_0_MDIO */
848 <MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x80>; /* ETH_0_INT# */
849 };
850
851 /* ETH_1 RGMII (On-module PHY) */
852 pinctrl_fec: fecgrp {
853 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, /* ETH1_RGMII_RXD0 */
854 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, /* ETH1_RGMII_RXD1 */
855 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, /* ETH1_RGMII_RXD2 */
856 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, /* ETH1_RGMII_RXD3 */
857 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, /* ETH1_RGMII_RXC */
858 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, /* ETH1_RGMII_RX_CTL */
859 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16>, /* ETH1_RGMII_TXD0 */
860 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16>, /* ETH1_RGMII_TXD1 */
861 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16>, /* ETH1_RGMII_TXD2 */
862 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16>, /* ETH1_RGMII_TXD3 */
863 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16>, /* ETH1_RGMII_TX_CTL */
864 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16>; /* ETH1_RGMII_TXC */
865 };
866
867 /* SMARC GBE1_SDP */
868 pinctrl_fec_1588_event: fec1588eventgrp {
869 fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x4>; /* SMARC P5 - GBE1_SDP */
870 };
871
872 /* SMARC CAN1 */
873 pinctrl_flexcan1: flexcan1grp {
874 fsl,pins = <MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154>, /* SMARC P146 - CAN1_RX */
875 <MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154>; /* SMARC P145 - CAN1_TX */
876 };
877
878 /* SMARC CAN0 */
879 pinctrl_flexcan2: flexcan2grp {
880 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SMARC P144 - CAN0_RX */
881 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SMARC P143 - CAN0_TX */
882 };
883
884 /* SMARC GPIO4 */
885 pinctrl_gpio4: gpio4grp {
886 fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x144>; /* SMARC P112 - GPIO4 */
887 };
888
889 /* SMARC GPIO5 */
890 pinctrl_gpio5: gpio5grp {
891 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x144>; /* SMARC P113 - GPIO5 */
892 };
893
894 /* SMARC GPIO5 as PWM */
895 pinctrl_gpio5_pwm: gpio5pwmgrp {
896 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x12>; /* SMARC P113 - PWM_OUT */
897 };
898
899 /* SMARC GPIO6 */
900 pinctrl_gpio6: gpio6grp {
901 fsl,pins = <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x144>; /* SMARC P114 - GPIO6 */
902 };
903
904 /* SMARC GPIO7 */
905 pinctrl_gpio7: gpio7grp {
906 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x144>; /* SMARC P115 - GPIO7 */
907 };
908
909 /* SMARC GPIO8 */
910 pinctrl_gpio8: gpio8grp {
911 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x144>; /* SMARC P116 - GPIO8 */
912 };
913
914 /* SMARC GPIO9 */
915 pinctrl_gpio9: gpio9grp {
916 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x144>; /* SMARC P117 - GPIO9 */
917 };
918
919 /* SMARC GPIO10 */
920 pinctrl_gpio10: gpio10grp {
921 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x144>; /* SMARC P118 - GPIO10 */
922 };
923
924 /* SMARC GPIO11 */
925 pinctrl_gpio11: gpio11grp {
926 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x144>; /* SMARC P119 - GPIO11 */
927 };
928
929 /* SMARC GPIO12 */
930 pinctrl_gpio12: gpio12grp {
931 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x144>; /* SMARC S142 - GPIO12 */
932 };
933
934 /* SMARC GPIO13 */
935 pinctrl_gpio13: gpio13grp {
936 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144>; /* SMARC S123 - GPIO13 */
937 };
938
939 /* SMARC HDMI */
940 pinctrl_hdmi: hdmigrp {
941 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c6>, /* SMARC P105 - HDMI_CTRL_CK */
942 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c6>, /* SMARC P106 - HDMI_CTRL_DAT */
943 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SMARC P104 - HDMI_HPD */
944 };
945
946 /* On-module I2C */
947 pinctrl_i2c1: i2c1grp {
948 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* CTRL_I2C_SCL */
949 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* CTRL_I2C_SDA */
950 };
951
952 /* On-module I2C as GPIOs */
953 pinctrl_i2c1_gpio: i2c1gpiogrp {
954 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* CTRL_I2C_SCL */
955 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* CTRL_I2C_SDA */
956 };
957
958 /* SMARC I2C_LCD */
959 pinctrl_i2c2: i2c2grp {
960 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */
961 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */
962 };
963
964 /* SMARC I2C_LCD as GPIOs */
965 pinctrl_i2c2_gpio: i2c2gpiogrp {
966 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */
967 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */
968 };
969
970 /* SMARC I2C_CAM0 */
971 pinctrl_i2c3: i2c3grp {
972 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */
973 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */
974 };
975
976 /* SMARC I2C_CAM0 as GPIOs */
977 pinctrl_i2c3_gpio: i2c3gpiogrp {
978 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */
979 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */
980 };
981
982 /* SMARC I2C_GP */
983 pinctrl_i2c4: i2c4grp {
984 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SMARC S48 - I2C_GP_CK */
985 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */
986 };
987
988 /* SMARC I2C_GP as GPIOs */
989 pinctrl_i2c4_gpio: i2c4gpiogrp {
990 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SMARC S48 - I2C_GP_CK */
991 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */
992 };
993
994 /* SMARC I2C_CAM1 */
995 pinctrl_i2c5: i2c5grp {
996 fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */
997 <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */
998 };
999
1000 /* SMARC I2C_CAM1 as GPIOs */
1001 pinctrl_i2c5_gpio: i2c5gpiogrp {
1002 fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */
1003 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */
1004 };
1005
1006 /* SMARC I2C_PM */
1007 pinctrl_i2c6: i2c6grp {
1008 fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x400001c6>, /* SMARC P121 - I2C_PM_CK */
1009 <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */
1010 };
1011
1012 /* SMARC I2C_PM as GPIOs */
1013 pinctrl_i2c6_gpio: i2c6gpiogrp {
1014 fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x400001c6>, /* SMARC P121 - I2C_PM_CK */
1015 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */
1016 };
1017
1018 pinctrl_lvds_dsi_sel: lvdsdsiselgrp {
1019 fsl,pins = <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x104>; /* LVDS_DSI_SEL */
1020 };
1021
1022 pinctrl_mcu_int: mcuintgrp {
1023 fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */
1024 };
1025
1026 /* SMARC LCD1_BKLT_PWM */
1027 pinctrl_lcd1_bklt_pwm1: pwm1grp {
1028 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x12>; /* SMARC S122 - LCD1_BKLT_PWM */
1029 };
1030
1031 /* SMARC LCD0_BKLT_PWM */
1032 pinctrl_lcd0_bklt_pwm2: pwm2grp {
1033 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x12>; /* SMARC S141 - LCD0_BKLT_PWM */
1034 };
1035
1036 /* PCAL6408 Interrupt */
1037 pinctrl_pcal6408: pcal6408intgrp {
1038 fsl,pins = <MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x1c4>; /* GPIO_EX_INT# */
1039 };
1040
1041 /* SMARC PCIE_A */
1042 pinctrl_pcie: pciegrp {
1043 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c0>, /* SMARC S146 - PCIE_WAKE# */
1044 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x04>; /* SMARC P75 - PCIE_A_RST# */
1045 };
1046
1047 /* PMIC Interrupt */
1048 pinctrl_pmic: pmicintgrp {
1049 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
1050 };
1051
1052 /* SMARC I2S0 */
1053 pinctrl_sai1: sai1grp {
1054 fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x94>, /* SMARC S42 - I2S0_CK */
1055 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x94>, /* SMARC S39 - I2S0_LRCLK */
1056 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x94>, /* SMARC S41 - I2S0_SDIN */
1057 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x94>; /* SMARC S40 - I2S0_SDOUT */
1058 };
1059
1060 /* SMARC AUDIO_MCK */
1061 pinctrl_sai1_mclk: sai1mclkgrp {
1062 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>; /* SMARC S38 - AUDIO_MCK */
1063 };
1064
1065 /* SMARC I2S2 */
1066 pinctrl_sai3: sai3grp {
1067 fsl,pins = <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94>, /* SMARC S52 - I2S2_SDIN */
1068 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94>, /* SMARC S53 - I2S2_CK */
1069 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94>, /* SMARC S51 - I2S2_SDOUT */
1070 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94>; /* SMARC S50 - I2S2_LRCLK */
1071 };
1072
1073 /* SMARC SLEEP# */
1074 pinctrl_sleep: sleepgrp {
1075 fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */
1076 };
1077
1078 /* SMARC SMB_ALERT# */
1079 pinctrl_smb_alert: smbalertgrp {
1080 fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */
1081 };
1082
1083 /* TPM_CS# */
1084 pinctrl_tpm_cs: tpmcsgrp {
1085 fsl,pins = <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x82>; /* TPM_CS# */
1086 };
1087
1088 /* WIFI_BT_WKUP_HOST/TPM_INT# */
1089 pinctrl_tpm_irq_wifi_bt_wkup: tpmirq-wifibtwkupgrp {
1090 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x16>; /* WIFI_BT_WKUP_HOST/TPM_INT# */
1091 };
1092
1093 /* SMARC SER0 */
1094 pinctrl_uart1: uart1grp {
1095 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SMARC P132 - SER2_CTS */
1096 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SMARC P131 - SER2_RTS */
1097 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SMARC P130 - SER2_RX */
1098 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SMARC P139 - SER2_TX */
1099 };
1100
1101 /* SMARC SER2 */
1102 pinctrl_uart2: uart2grp {
1103 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SMARC P139 - SER2_CTS */
1104 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SMARC P138 - SER2_RTS */
1105 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SMARC P137 - SER2_RX */
1106 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SMARC P136 - SER2_TX */
1107 };
1108
1109 /* SMARC SER3 */
1110 pinctrl_uart3: uart3grp {
1111 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SMARC P141 - SER3_RX */
1112 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SMARC P140 - SER3_TX */
1113 };
1114
1115 /* SMARC SER1 */
1116 pinctrl_uart4: uart4grp {
1117 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SMARC P135 - SER1_RX */
1118 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SMARC P134 - SER1_TX */
1119 };
1120
1121 /* SMARC USB0_OTG_ID */
1122 pinctrl_usb0_id: usb0idgrp {
1123 fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SMARC P64 - USB0_OTG_ID */
1124 };
1125
1126 /* SMARC USB0_EN_OC# */
1127 pinctrl_usb0_en_oc: usb0enocgrp {
1128 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x04>; /* SMARC P62 - USB0_EN_OC# */
1129 };
1130
1131 /* On module USB Hub VBUS, or SMARC USB2_EN_OC# depending on assembling */
1132 pinctrl_usb1_en_oc: usb1enocgrp {
1133 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04>; /* SMARC P71 - USB2_EN_OC# */
1134 };
1135
1136 /* On-module Wi-Fi */
1137 pinctrl_usdhc1: usdhc1grp {
1138 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, /* WiFi_SDIO_CLK */
1139 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, /* WiFi_SDIO_CMD */
1140 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, /* WiFi_SDIO_DATA0 */
1141 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, /* WiFi_SDIO_DATA1 */
1142 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, /* WiFi_SDIO_DATA2 */
1143 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; /* WiFi_SDIO_DATA3 */
1144 };
1145
1146 /* On-module Wi-Fi */
1147 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1148 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, /* WiFi_SDIO_CLK */
1149 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, /* WiFi_SDIO_CMD */
1150 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, /* WiFi_SDIO_DATA0 */
1151 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, /* WiFi_SDIO_DATA1 */
1152 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, /* WiFi_SDIO_DATA2 */
1153 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; /* WiFi_SDIO_DATA3 */
1154 };
1155
1156 /* On-module Wi-Fi */
1157 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1158 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, /* WiFi_SDIO_CLK */
1159 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, /* WiFi_SDIO_CMD */
1160 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, /* WiFi_SDIO_DATA0 */
1161 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, /* WiFi_SDIO_DATA1 */
1162 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, /* WiFi_SDIO_DATA2 */
1163 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; /* WiFi_SDIO_DATA3 */
1164 };
1165
1166 /* SMARC SDIO */
1167 pinctrl_usdhc2: usdhc2grp {
1168 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SMARC P36 - SDIO_CK */
1169 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SMARC P34 - SDIO_CMD */
1170 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SMARC P39 - SDIO_DO */
1171 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SMARC P40 - SDIO_D1 */
1172 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SMARC P41 - SDIO_D2 */
1173 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SMARC P42 - SDIO_D3 */
1174 };
1175
1176 /* SMARC SDIO 100MHz */
1177 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1178 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, /* SMARC P36 - SDIO_CK */
1179 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, /* SMARC P34 - SDIO_CMD */
1180 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, /* SMARC P39 - SDIO_DO */
1181 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, /* SMARC P40 - SDIO_D1 */
1182 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, /* SMARC P41 - SDIO_D2 */
1183 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; /* SMARC P42 - SDIO_D3 */
1184 };
1185
1186 /* SMARC SDIO 200MHz */
1187 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1188 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, /* SMARC P36 - SDIO_CK */
1189 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, /* SMARC P34 - SDIO_CMD */
1190 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, /* SMARC P39 - SDIO_DO */
1191 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, /* SMARC P40 - SDIO_D1 */
1192 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, /* SMARC P41 - SDIO_D2 */
1193 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; /* SMARC P42 - SDIO_D3 */
1194 };
1195
1196 /* SMARC SDIO_CD# */
1197 pinctrl_usdhc2_cd: usdhc2cdgrp {
1198 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SMARC P35 - SDIO_CD# */
1199 };
1200
1201 /* SMARC SDIO_CD# */
1202 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1203 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SMARC P35 - SDIO_CD# */
1204 };
1205
1206 /* SMARC SDIO_PWR_EN */
1207 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1208 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* SMARC P37 - SDIO_PWR_EN */
1209 };
1210
1211 /* SMARC SDIO Sleep - Avoid backfeeding with removed card power */
1212 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1213 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, /* SMARC P36 - SDIO_CK */
1214 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, /* SMARC P34 - SDIO_CMD */
1215 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, /* SMARC P39 - SDIO_DO */
1216 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, /* SMARC P39 - SDIO_D1 */
1217 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, /* SMARC P39 - SDIO_D2 */
1218 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; /* SMARC P39 - SDIO_D3 */
1219 };
1220
1221 pinctrl_usdhc2_vsel: usdhc2vselgrp {
1222 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x4>; /* PMIC_USDHC_VSELECT */
1223 };
1224
1225 /* SMARC SDIO_WP */
1226 pinctrl_usdhc2_wp: usdhc2wpgrp {
1227 fsl,pins = <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x144>; /* SMARC P33 - SDIO_WP */
1228 };
1229
1230 /* On-module eMMC */
1231 pinctrl_usdhc3: usdhc3grp {
1232 fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, /* eMMC_STROBE */
1233 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, /* eMMC_DATA5 */
1234 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, /* eMMC_DATA6 */
1235 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, /* eMMC_DATA7 */
1236 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, /* eMMC_DATA0 */
1237 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, /* eMMC_DATA1 */
1238 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, /* eMMC_DATA2 */
1239 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, /* eMMC_DATA3 */
1240 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, /* eMMC_DATA4 */
1241 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, /* eMMC_CLK */
1242 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; /* eMMC_CMD */
1243 };
1244
1245 /* On-module eMMC */
1246 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1247 fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, /* eMMC_STROBE */
1248 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, /* eMMC_DATA5 */
1249 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, /* eMMC_DATA6 */
1250 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, /* eMMC_DATA7 */
1251 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, /* eMMC_DATA0 */
1252 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, /* eMMC_DATA1 */
1253 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, /* eMMC_DATA2 */
1254 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, /* eMMC_DATA3 */
1255 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, /* eMMC_DATA4 */
1256 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, /* eMMC_CLK */
1257 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; /* eMMC_CMD */
1258 };
1259
1260 /* On-module eMMC */
1261 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1262 fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, /* eMMC_STROBE */
1263 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, /* eMMC_DATA5 */
1264 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, /* eMMC_DATA6 */
1265 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, /* eMMC_DATA7 */
1266 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, /* eMMC_DATA0 */
1267 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, /* eMMC_DATA1 */
1268 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, /* eMMC_DATA2 */
1269 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, /* eMMC_DATA3 */
1270 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, /* eMMC_DATA4 */
1271 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, /* eMMC_CLK */
1272 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; /* eMMC_CMD */
1273 };
1274
1275 /* SoC Watchdog */
1276 pinctrl_wdog: wdoggrp {
1277 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x4>; /* CTRL_SOC_WDOG */
1278 };
1279
1280 /* On-module Wi-Fi power enable */
1281 pinctrl_wifi_pwr_en: wifipwrengrp {
1282 fsl,pins = <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x104>; /* CTRL_EN_WIFI */
1283 };
1284};