Blame - board/ti/beagle/beagle.h - filogic/uboot

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Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	1	/*
				2	* (C) Copyright 2008
				3	* Dirk Behme <dirk.behme@gmail.com>
				4	*
Wolfgang Denk	d79de1d	2013-07-08 09:37:19 +0200	[diff] [blame]	5	* SPDX-License-Identifier: GPL-2.0+
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	6	*/
				7	#ifndef _BEAGLE_H_
				8	#define _BEAGLE_H_
				9
Jason Kridner	b8f6ac5	2011-04-19 14:01:13 -0500	[diff] [blame]	10	#include <asm/arch/dss.h>
				11
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	12	const omap3_sysinfo sysinfo = {
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	13	DDR_STACKED,
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	14	"OMAP3 Beagle board",
				15	#if defined(CONFIG_ENV_IS_IN_ONENAND)
				16	"OneNAND",
				17	#else
				18	"NAND",
				19	#endif
				20	};
				21
Steve Sakoman	3ca3376	2010-08-12 15:17:37 -0700	[diff] [blame]	22	/* BeagleBoard revisions */
				23	#define REVISION_AXBX 0x7
				24	#define REVISION_CX 0x6
				25	#define REVISION_C4 0x5
Nishanth Menon	1d65fb3	2013-07-15 07:11:30 -0500	[diff] [blame]	26	#define REVISION_XM_AB 0x0
Koen Kooi	6330844	2011-06-17 09:37:37 +0200	[diff] [blame]	27	#define REVISION_XM_C 0x2
Dirk Behme	7871611	2009-02-12 18:55:41 +0100	[diff] [blame]	28
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	29	/*
				30	* IEN - Input Enable
				31	* IDIS - Input Disable
				32	* PTD - Pull type Down
				33	* PTU - Pull type Up
				34	* DIS - Pull type selection is inactive
				35	* EN - Pull type selection is active
				36	* M0 - Mode 0
				37	* The commented string gives the final mux configuration for that pin
				38	*/
				39	#define MUX_BEAGLE() \
				40	/SDRC/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	41	MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /SDRC_D0/\
				42	MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) /SDRC_D1/\
				43	MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) /SDRC_D2/\
				44	MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) /SDRC_D3/\
				45	MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) /SDRC_D4/\
				46	MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) /SDRC_D5/\
				47	MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) /SDRC_D6/\
				48	MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) /SDRC_D7/\
				49	MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) /SDRC_D8/\
				50	MUX_VAL(CP(SDRC_D9), (IEN \| PTD \| DIS \| M0)) /SDRC_D9/\
				51	MUX_VAL(CP(SDRC_D10), (IEN \| PTD \| DIS \| M0)) /SDRC_D10/\
				52	MUX_VAL(CP(SDRC_D11), (IEN \| PTD \| DIS \| M0)) /SDRC_D11/\
				53	MUX_VAL(CP(SDRC_D12), (IEN \| PTD \| DIS \| M0)) /SDRC_D12/\
				54	MUX_VAL(CP(SDRC_D13), (IEN \| PTD \| DIS \| M0)) /SDRC_D13/\
				55	MUX_VAL(CP(SDRC_D14), (IEN \| PTD \| DIS \| M0)) /SDRC_D14/\
				56	MUX_VAL(CP(SDRC_D15), (IEN \| PTD \| DIS \| M0)) /SDRC_D15/\
				57	MUX_VAL(CP(SDRC_D16), (IEN \| PTD \| DIS \| M0)) /SDRC_D16/\
				58	MUX_VAL(CP(SDRC_D17), (IEN \| PTD \| DIS \| M0)) /SDRC_D17/\
				59	MUX_VAL(CP(SDRC_D18), (IEN \| PTD \| DIS \| M0)) /SDRC_D18/\
				60	MUX_VAL(CP(SDRC_D19), (IEN \| PTD \| DIS \| M0)) /SDRC_D19/\
				61	MUX_VAL(CP(SDRC_D20), (IEN \| PTD \| DIS \| M0)) /SDRC_D20/\
				62	MUX_VAL(CP(SDRC_D21), (IEN \| PTD \| DIS \| M0)) /SDRC_D21/\
				63	MUX_VAL(CP(SDRC_D22), (IEN \| PTD \| DIS \| M0)) /SDRC_D22/\
				64	MUX_VAL(CP(SDRC_D23), (IEN \| PTD \| DIS \| M0)) /SDRC_D23/\
				65	MUX_VAL(CP(SDRC_D24), (IEN \| PTD \| DIS \| M0)) /SDRC_D24/\
				66	MUX_VAL(CP(SDRC_D25), (IEN \| PTD \| DIS \| M0)) /SDRC_D25/\
				67	MUX_VAL(CP(SDRC_D26), (IEN \| PTD \| DIS \| M0)) /SDRC_D26/\
				68	MUX_VAL(CP(SDRC_D27), (IEN \| PTD \| DIS \| M0)) /SDRC_D27/\
				69	MUX_VAL(CP(SDRC_D28), (IEN \| PTD \| DIS \| M0)) /SDRC_D28/\
				70	MUX_VAL(CP(SDRC_D29), (IEN \| PTD \| DIS \| M0)) /SDRC_D29/\
				71	MUX_VAL(CP(SDRC_D30), (IEN \| PTD \| DIS \| M0)) /SDRC_D30/\
				72	MUX_VAL(CP(SDRC_D31), (IEN \| PTD \| DIS \| M0)) /SDRC_D31/\
				73	MUX_VAL(CP(SDRC_CLK), (IEN \| PTD \| DIS \| M0)) /SDRC_CLK/\
				74	MUX_VAL(CP(SDRC_DQS0), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS0/\
				75	MUX_VAL(CP(SDRC_DQS1), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS1/\
				76	MUX_VAL(CP(SDRC_DQS2), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS2/\
				77	MUX_VAL(CP(SDRC_DQS3), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS3/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	78	/GPMC/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	79	MUX_VAL(CP(GPMC_A1), (IDIS \| PTD \| DIS \| M0)) /GPMC_A1/\
				80	MUX_VAL(CP(GPMC_A2), (IDIS \| PTD \| DIS \| M0)) /GPMC_A2/\
				81	MUX_VAL(CP(GPMC_A3), (IDIS \| PTD \| DIS \| M0)) /GPMC_A3/\
				82	MUX_VAL(CP(GPMC_A4), (IDIS \| PTD \| DIS \| M0)) /GPMC_A4/\
				83	MUX_VAL(CP(GPMC_A5), (IDIS \| PTD \| DIS \| M0)) /GPMC_A5/\
				84	MUX_VAL(CP(GPMC_A6), (IDIS \| PTD \| DIS \| M0)) /GPMC_A6/\
				85	MUX_VAL(CP(GPMC_A7), (IDIS \| PTD \| DIS \| M0)) /GPMC_A7/\
				86	MUX_VAL(CP(GPMC_A8), (IDIS \| PTD \| DIS \| M0)) /GPMC_A8/\
				87	MUX_VAL(CP(GPMC_A9), (IDIS \| PTD \| DIS \| M0)) /GPMC_A9/\
				88	MUX_VAL(CP(GPMC_A10), (IDIS \| PTD \| DIS \| M0)) /GPMC_A10/\
				89	MUX_VAL(CP(GPMC_D0), (IEN \| PTD \| DIS \| M0)) /GPMC_D0/\
				90	MUX_VAL(CP(GPMC_D1), (IEN \| PTD \| DIS \| M0)) /GPMC_D1/\
				91	MUX_VAL(CP(GPMC_D2), (IEN \| PTD \| DIS \| M0)) /GPMC_D2/\
				92	MUX_VAL(CP(GPMC_D3), (IEN \| PTD \| DIS \| M0)) /GPMC_D3/\
				93	MUX_VAL(CP(GPMC_D4), (IEN \| PTD \| DIS \| M0)) /GPMC_D4/\
				94	MUX_VAL(CP(GPMC_D5), (IEN \| PTD \| DIS \| M0)) /GPMC_D5/\
				95	MUX_VAL(CP(GPMC_D6), (IEN \| PTD \| DIS \| M0)) /GPMC_D6/\
				96	MUX_VAL(CP(GPMC_D7), (IEN \| PTD \| DIS \| M0)) /GPMC_D7/\
				97	MUX_VAL(CP(GPMC_D8), (IEN \| PTD \| DIS \| M0)) /GPMC_D8/\
				98	MUX_VAL(CP(GPMC_D9), (IEN \| PTD \| DIS \| M0)) /GPMC_D9/\
				99	MUX_VAL(CP(GPMC_D10), (IEN \| PTD \| DIS \| M0)) /GPMC_D10/\
				100	MUX_VAL(CP(GPMC_D11), (IEN \| PTD \| DIS \| M0)) /GPMC_D11/\
				101	MUX_VAL(CP(GPMC_D12), (IEN \| PTD \| DIS \| M0)) /GPMC_D12/\
				102	MUX_VAL(CP(GPMC_D13), (IEN \| PTD \| DIS \| M0)) /GPMC_D13/\
				103	MUX_VAL(CP(GPMC_D14), (IEN \| PTD \| DIS \| M0)) /GPMC_D14/\
				104	MUX_VAL(CP(GPMC_D15), (IEN \| PTD \| DIS \| M0)) /GPMC_D15/\
				105	MUX_VAL(CP(GPMC_NCS0), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS0/\
				106	MUX_VAL(CP(GPMC_NCS1), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS1/\
				107	MUX_VAL(CP(GPMC_NCS2), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS2/\
				108	MUX_VAL(CP(GPMC_NCS3), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS3/\
				109	MUX_VAL(CP(GPMC_NCS4), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS4/\
				110	MUX_VAL(CP(GPMC_NCS5), (IDIS \| PTD \| DIS \| M0)) /GPMC_nCS5/\
				111	MUX_VAL(CP(GPMC_NCS6), (IEN \| PTD \| DIS \| M1)) /SYS_nDMA_REQ2/\
				112	MUX_VAL(CP(GPMC_NCS7), (IEN \| PTU \| EN \| M1)) /SYS_nDMA_REQ3/\
				113	MUX_VAL(CP(GPMC_NBE1), (IEN \| PTD \| DIS \| M0)) /GPMC_nBE1/\
				114	MUX_VAL(CP(GPMC_WAIT2), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT2/\
				115	MUX_VAL(CP(GPMC_WAIT3), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT3/\
				116	MUX_VAL(CP(GPMC_CLK), (IDIS \| PTD \| DIS \| M0)) /GPMC_CLK/\
				117	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nADV_ALE/\
				118	MUX_VAL(CP(GPMC_NOE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nOE/\
				119	MUX_VAL(CP(GPMC_NWE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nWE/\
				120	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nBE0_CLE/\
				121	MUX_VAL(CP(GPMC_NWP), (IEN \| PTD \| DIS \| M0)) /GPMC_nWP/\
				122	MUX_VAL(CP(GPMC_WAIT0), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT0/\
				123	MUX_VAL(CP(GPMC_WAIT1), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT1/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	124	/DSS/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	125	MUX_VAL(CP(DSS_PCLK), (IDIS \| PTD \| DIS \| M0)) /DSS_PCLK/\
				126	MUX_VAL(CP(DSS_HSYNC), (IDIS \| PTD \| DIS \| M0)) /DSS_HSYNC/\
				127	MUX_VAL(CP(DSS_VSYNC), (IDIS \| PTD \| DIS \| M0)) /DSS_VSYNC/\
				128	MUX_VAL(CP(DSS_ACBIAS), (IDIS \| PTD \| DIS \| M0)) /DSS_ACBIAS/\
				129	MUX_VAL(CP(DSS_DATA0), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA0/\
				130	MUX_VAL(CP(DSS_DATA1), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA1/\
				131	MUX_VAL(CP(DSS_DATA2), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA2/\
				132	MUX_VAL(CP(DSS_DATA3), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA3/\
				133	MUX_VAL(CP(DSS_DATA4), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA4/\
				134	MUX_VAL(CP(DSS_DATA5), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA5/\
				135	MUX_VAL(CP(DSS_DATA6), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA6/\
				136	MUX_VAL(CP(DSS_DATA7), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA7/\
				137	MUX_VAL(CP(DSS_DATA8), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA8/\
				138	MUX_VAL(CP(DSS_DATA9), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA9/\
				139	MUX_VAL(CP(DSS_DATA10), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA10/\
				140	MUX_VAL(CP(DSS_DATA11), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA11/\
				141	MUX_VAL(CP(DSS_DATA12), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA12/\
				142	MUX_VAL(CP(DSS_DATA13), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA13/\
				143	MUX_VAL(CP(DSS_DATA14), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA14/\
				144	MUX_VAL(CP(DSS_DATA15), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA15/\
				145	MUX_VAL(CP(DSS_DATA16), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA16/\
				146	MUX_VAL(CP(DSS_DATA17), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA17/\
				147	MUX_VAL(CP(DSS_DATA18), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA18/\
				148	MUX_VAL(CP(DSS_DATA19), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA19/\
				149	MUX_VAL(CP(DSS_DATA20), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA20/\
				150	MUX_VAL(CP(DSS_DATA21), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA21/\
				151	MUX_VAL(CP(DSS_DATA22), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA22/\
				152	MUX_VAL(CP(DSS_DATA23), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA23/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	153	/CAMERA/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	154	MUX_VAL(CP(CAM_HS), (IEN \| PTU \| EN \| M0)) /CAM_HS /\
				155	MUX_VAL(CP(CAM_VS), (IEN \| PTU \| EN \| M0)) /CAM_VS /\
				156	MUX_VAL(CP(CAM_XCLKA), (IDIS \| PTD \| DIS \| M0)) /CAM_XCLKA/\
				157	MUX_VAL(CP(CAM_PCLK), (IEN \| PTU \| EN \| M0)) /CAM_PCLK/\
				158	MUX_VAL(CP(CAM_FLD), (IDIS \| PTD \| DIS \| M4)) /GPIO_98/\
				159	MUX_VAL(CP(CAM_D0), (IEN \| PTD \| DIS \| M0)) /CAM_D0/\
				160	MUX_VAL(CP(CAM_D1), (IEN \| PTD \| DIS \| M0)) /CAM_D1/\
				161	MUX_VAL(CP(CAM_D2), (IEN \| PTD \| DIS \| M0)) /CAM_D2/\
				162	MUX_VAL(CP(CAM_D3), (IEN \| PTD \| DIS \| M0)) /CAM_D3/\
				163	MUX_VAL(CP(CAM_D4), (IEN \| PTD \| DIS \| M0)) /CAM_D4/\
				164	MUX_VAL(CP(CAM_D5), (IEN \| PTD \| DIS \| M0)) /CAM_D5/\
				165	MUX_VAL(CP(CAM_D6), (IEN \| PTD \| DIS \| M0)) /CAM_D6/\
				166	MUX_VAL(CP(CAM_D7), (IEN \| PTD \| DIS \| M0)) /CAM_D7/\
				167	MUX_VAL(CP(CAM_D8), (IEN \| PTD \| DIS \| M0)) /CAM_D8/\
				168	MUX_VAL(CP(CAM_D9), (IEN \| PTD \| DIS \| M0)) /CAM_D9/\
				169	MUX_VAL(CP(CAM_D10), (IEN \| PTD \| DIS \| M0)) /CAM_D10/\
				170	MUX_VAL(CP(CAM_D11), (IEN \| PTD \| DIS \| M0)) /CAM_D11/\
				171	MUX_VAL(CP(CAM_XCLKB), (IDIS \| PTD \| DIS \| M0)) /CAM_XCLKB/\
				172	MUX_VAL(CP(CAM_WEN), (IEN \| PTD \| DIS \| M4)) /GPIO_167/\
				173	MUX_VAL(CP(CAM_STROBE), (IDIS \| PTD \| DIS \| M0)) /CAM_STROBE/\
				174	MUX_VAL(CP(CSI2_DX0), (IEN \| PTD \| DIS \| M0)) /CSI2_DX0/\
				175	MUX_VAL(CP(CSI2_DY0), (IEN \| PTD \| DIS \| M0)) /CSI2_DY0/\
				176	MUX_VAL(CP(CSI2_DX1), (IEN \| PTD \| DIS \| M0)) /CSI2_DX1/\
				177	MUX_VAL(CP(CSI2_DY1), (IEN \| PTD \| DIS \| M0)) /CSI2_DY1/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	178	/Audio Interface /\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	179	MUX_VAL(CP(MCBSP2_FSX), (IEN \| PTD \| DIS \| M0)) /McBSP2_FSX/\
				180	MUX_VAL(CP(MCBSP2_CLKX), (IEN \| PTD \| DIS \| M0)) /McBSP2_CLKX/\
				181	MUX_VAL(CP(MCBSP2_DR), (IEN \| PTD \| DIS \| M0)) /McBSP2_DR/\
				182	MUX_VAL(CP(MCBSP2_DX), (IDIS \| PTD \| DIS \| M0)) /McBSP2_DX/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	183	/Expansion card /\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	184	MUX_VAL(CP(MMC1_CLK), (IDIS \| PTU \| EN \| M0)) /MMC1_CLK/\
				185	MUX_VAL(CP(MMC1_CMD), (IEN \| PTU \| EN \| M0)) /MMC1_CMD/\
				186	MUX_VAL(CP(MMC1_DAT0), (IEN \| PTU \| EN \| M0)) /MMC1_DAT0/\
				187	MUX_VAL(CP(MMC1_DAT1), (IEN \| PTU \| EN \| M0)) /MMC1_DAT1/\
				188	MUX_VAL(CP(MMC1_DAT2), (IEN \| PTU \| EN \| M0)) /MMC1_DAT2/\
				189	MUX_VAL(CP(MMC1_DAT3), (IEN \| PTU \| EN \| M0)) /MMC1_DAT3/\
				190	MUX_VAL(CP(MMC1_DAT4), (IEN \| PTU \| EN \| M0)) /MMC1_DAT4/\
				191	MUX_VAL(CP(MMC1_DAT5), (IEN \| PTU \| EN \| M0)) /MMC1_DAT5/\
				192	MUX_VAL(CP(MMC1_DAT6), (IEN \| PTU \| EN \| M0)) /MMC1_DAT6/\
				193	MUX_VAL(CP(MMC1_DAT7), (IEN \| PTU \| EN \| M0)) /MMC1_DAT7/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	194	/Wireless LAN /\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	195	MUX_VAL(CP(MMC2_CLK), (IEN \| PTU \| EN \| M4)) /GPIO_130/\
				196	MUX_VAL(CP(MMC2_CMD), (IEN \| PTU \| EN \| M4)) /GPIO_131/\
				197	MUX_VAL(CP(MMC2_DAT0), (IEN \| PTU \| EN \| M4)) /GPIO_132/\
				198	MUX_VAL(CP(MMC2_DAT1), (IEN \| PTU \| EN \| M4)) /GPIO_133/\
				199	MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M4)) /GPIO_134/\
				200	MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M4)) /GPIO_135/\
				201	MUX_VAL(CP(MMC2_DAT4), (IEN \| PTU \| EN \| M4)) /GPIO_136/\
				202	MUX_VAL(CP(MMC2_DAT5), (IEN \| PTU \| EN \| M4)) /GPIO_137/\
				203	MUX_VAL(CP(MMC2_DAT6), (IEN \| PTU \| EN \| M4)) /GPIO_138/\
				204	MUX_VAL(CP(MMC2_DAT7), (IEN \| PTU \| EN \| M4)) /GPIO_139/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	205	/Bluetooth/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	206	MUX_VAL(CP(MCBSP3_DX), (IEN \| PTD \| DIS \| M1)) /UART2_CTS/\
				207	MUX_VAL(CP(MCBSP3_DR), (IDIS \| PTD \| DIS \| M1)) /UART2_RTS/\
				208	MUX_VAL(CP(MCBSP3_CLKX), (IDIS \| PTD \| DIS \| M1)) /UART2_TX/\
				209	MUX_VAL(CP(MCBSP3_FSX), (IEN \| PTD \| DIS \| M1)) /UART2_RX/\
				210	MUX_VAL(CP(UART2_CTS), (IEN \| PTD \| DIS \| M4)) /GPIO_144/\
				211	MUX_VAL(CP(UART2_RTS), (IEN \| PTD \| DIS \| M4)) /GPIO_145/\
				212	MUX_VAL(CP(UART2_TX), (IEN \| PTD \| DIS \| M4)) /GPIO_146/\
				213	MUX_VAL(CP(UART2_RX), (IEN \| PTD \| DIS \| M4)) /GPIO_147/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	214	/Modem Interface /\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	215	MUX_VAL(CP(UART1_TX), (IDIS \| PTD \| DIS \| M0)) /UART1_TX/\
				216	MUX_VAL(CP(UART1_RTS), (IDIS \| PTD \| DIS \| M4)) /GPIO_149/ \
				217	MUX_VAL(CP(UART1_CTS), (IDIS \| PTD \| DIS \| M4)) /GPIO_150/ \
				218	MUX_VAL(CP(UART1_RX), (IEN \| PTD \| DIS \| M0)) /UART1_RX/\
				219	MUX_VAL(CP(MCBSP4_CLKX), (IEN \| PTD \| DIS \| M1)) /SSI1_DAT_RX/\
				220	MUX_VAL(CP(MCBSP4_DR), (IEN \| PTD \| DIS \| M1)) /SSI1_FLAG_RX/\
				221	MUX_VAL(CP(MCBSP4_DX), (IEN \| PTD \| DIS \| M1)) /SSI1_RDY_RX/\
				222	MUX_VAL(CP(MCBSP4_FSX), (IEN \| PTD \| DIS \| M1)) /SSI1_WAKE/\
				223	MUX_VAL(CP(MCBSP1_CLKR), (IDIS \| PTD \| DIS \| M4)) /GPIO_156/\
				224	MUX_VAL(CP(MCBSP1_FSR), (IDIS \| PTU \| EN \| M4)) /GPIO_157/\
				225	MUX_VAL(CP(MCBSP1_DX), (IDIS \| PTD \| DIS \| M4)) /GPIO_158/\
				226	MUX_VAL(CP(MCBSP1_DR), (IDIS \| PTD \| DIS \| M4)) /GPIO_159/\
				227	MUX_VAL(CP(MCBSP_CLKS), (IEN \| PTU \| DIS \| M0)) /McBSP_CLKS/\
				228	MUX_VAL(CP(MCBSP1_FSX), (IDIS \| PTD \| DIS \| M4)) /GPIO_161/\
				229	MUX_VAL(CP(MCBSP1_CLKX), (IDIS \| PTD \| DIS \| M4)) /GPIO_162/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	230	/Serial Interface/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	231	MUX_VAL(CP(UART3_CTS_RCTX), (IEN \| PTD \| EN \| M0)) /UART3_CTS_RCTX/\
				232	MUX_VAL(CP(UART3_RTS_SD), (IDIS \| PTD \| DIS \| M0)) /UART3_RTS_SD /\
				233	MUX_VAL(CP(UART3_RX_IRRX), (IEN \| PTD \| DIS \| M0)) /UART3_RX_IRRX/\
				234	MUX_VAL(CP(UART3_TX_IRTX), (IDIS \| PTD \| DIS \| M0)) /UART3_TX_IRTX/\
				235	MUX_VAL(CP(HSUSB0_CLK), (IEN \| PTD \| DIS \| M0)) /HSUSB0_CLK/\
				236	MUX_VAL(CP(HSUSB0_STP), (IDIS \| PTU \| EN \| M0)) /HSUSB0_STP/\
				237	MUX_VAL(CP(HSUSB0_DIR), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DIR/\
				238	MUX_VAL(CP(HSUSB0_NXT), (IEN \| PTD \| DIS \| M0)) /HSUSB0_NXT/\
				239	MUX_VAL(CP(HSUSB0_DATA0), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA0/\
				240	MUX_VAL(CP(HSUSB0_DATA1), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA1/\
				241	MUX_VAL(CP(HSUSB0_DATA2), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA2/\
				242	MUX_VAL(CP(HSUSB0_DATA3), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA3/\
				243	MUX_VAL(CP(HSUSB0_DATA4), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA4/\
				244	MUX_VAL(CP(HSUSB0_DATA5), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA5/\
				245	MUX_VAL(CP(HSUSB0_DATA6), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA6/\
				246	MUX_VAL(CP(HSUSB0_DATA7), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA7/\
				247	MUX_VAL(CP(I2C1_SCL), (IEN \| PTU \| EN \| M0)) /I2C1_SCL/\
				248	MUX_VAL(CP(I2C1_SDA), (IEN \| PTU \| EN \| M0)) /I2C1_SDA/\
Koen Kooi	b6241c2	2010-09-20 10:21:33 -0700	[diff] [blame]	249	MUX_VAL(CP(I2C2_SCL), (IEN \| PTU \| EN \| M0)) /I2C2_SCL/\
				250	MUX_VAL(CP(I2C2_SDA), (IEN \| PTU \| EN \| M0)) /I2C2_SDA/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	251	MUX_VAL(CP(I2C3_SCL), (IEN \| PTU \| EN \| M0)) /I2C3_SCL/\
				252	MUX_VAL(CP(I2C3_SDA), (IEN \| PTU \| EN \| M0)) /I2C3_SDA/\
				253	MUX_VAL(CP(I2C4_SCL), (IEN \| PTU \| EN \| M0)) /I2C4_SCL/\
				254	MUX_VAL(CP(I2C4_SDA), (IEN \| PTU \| EN \| M0)) /I2C4_SDA/\
				255	MUX_VAL(CP(HDQ_SIO), (IDIS \| PTU \| EN \| M4)) /GPIO_170/\
				256	MUX_VAL(CP(MCSPI1_CLK), (IEN \| PTU \| EN \| M4)) /GPIO_171/\
				257	MUX_VAL(CP(MCSPI1_SIMO), (IEN \| PTU \| EN \| M4)) /GPIO_172/\
Steve Sakoman	3ca3376	2010-08-12 15:17:37 -0700	[diff] [blame]	258	MUX_VAL(CP(MCSPI1_SOMI), (IEN \| PTU \| EN \| M4)) /GPIO_173/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	259	MUX_VAL(CP(MCSPI1_CS0), (IEN \| PTD \| EN \| M0)) /McSPI1_CS0/\
				260	MUX_VAL(CP(MCSPI1_CS1), (IDIS \| PTD \| EN \| M0)) /McSPI1_CS1/\
				261	MUX_VAL(CP(MCSPI1_CS2), (IDIS \| PTD \| DIS \| M4)) /GPIO_176/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	262	/* USB EHCI (port 2) */\
Alexander Holler	e1a2957	2011-04-19 09:27:23 -0400	[diff] [blame]	263	MUX_VAL(CP(MCSPI1_CS3), (IEN \| PTD \| EN \| M3)) /HSUSB2_DATA2/\
				264	MUX_VAL(CP(MCSPI2_CLK), (IEN \| PTD \| EN \| M3)) /HSUSB2_DATA7/\
				265	MUX_VAL(CP(MCSPI2_SIMO), (IEN \| PTD \| EN \| M3)) /HSUSB2_DATA4/\
				266	MUX_VAL(CP(MCSPI2_SOMI), (IEN \| PTD \| EN \| M3)) /HSUSB2_DATA5/\
				267	MUX_VAL(CP(MCSPI2_CS0), (IEN \| PTD \| EN \| M3)) /HSUSB2_DATA6/\
				268	MUX_VAL(CP(MCSPI2_CS1), (IEN \| PTD \| EN \| M3)) /HSUSB2_DATA3/\
				269	MUX_VAL(CP(ETK_D10_ES2), (IDIS \| PTD \| DIS \| M3)) /HSUSB2_CLK/\
				270	MUX_VAL(CP(ETK_D11_ES2), (IDIS \| PTD \| DIS \| M3)) /HSUSB2_STP/\
				271	MUX_VAL(CP(ETK_D12_ES2), (IEN \| PTD \| EN \| M3)) /HSUSB2_DIR/\
				272	MUX_VAL(CP(ETK_D13_ES2), (IEN \| PTD \| EN \| M3)) /HSUSB2_NXT/\
				273	MUX_VAL(CP(ETK_D14_ES2), (IEN \| PTD \| EN \| M3)) /HSUSB2_DATA0/\
				274	MUX_VAL(CP(ETK_D15_ES2), (IEN \| PTD \| EN \| M3)) /HSUSB2_DATA1/\
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	275	/Control and debug /\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	276	MUX_VAL(CP(SYS_32K), (IEN \| PTD \| DIS \| M0)) /SYS_32K/\
				277	MUX_VAL(CP(SYS_CLKREQ), (IEN \| PTD \| DIS \| M0)) /SYS_CLKREQ/\
				278	MUX_VAL(CP(SYS_NIRQ), (IEN \| PTU \| EN \| M0)) /SYS_nIRQ/\
				279	MUX_VAL(CP(SYS_BOOT0), (IEN \| PTD \| DIS \| M4)) /GPIO_2/\
				280	MUX_VAL(CP(SYS_BOOT1), (IEN \| PTD \| DIS \| M4)) /GPIO_3/\
				281	MUX_VAL(CP(SYS_BOOT2), (IEN \| PTD \| DIS \| M4)) /GPIO_4 - MMC1_WP/\
				282	MUX_VAL(CP(SYS_BOOT3), (IEN \| PTD \| DIS \| M4)) /GPIO_5/\
				283	MUX_VAL(CP(SYS_BOOT4), (IEN \| PTD \| DIS \| M4)) /GPIO_6/\
				284	MUX_VAL(CP(SYS_BOOT5), (IEN \| PTD \| DIS \| M4)) /GPIO_7/\
				285	MUX_VAL(CP(SYS_BOOT6), (IDIS \| PTD \| DIS \| M4)) /GPIO_8/ \
				286	MUX_VAL(CP(SYS_OFF_MODE), (IEN \| PTD \| DIS \| M0)) /SYS_OFF_MODE/\
				287	MUX_VAL(CP(SYS_CLKOUT1), (IEN \| PTD \| DIS \| M0)) /SYS_CLKOUT1/\
				288	MUX_VAL(CP(SYS_CLKOUT2), (IEN \| PTU \| EN \| M4)) /GPIO_186/\
				289	MUX_VAL(CP(ETK_CLK_ES2), (IDIS \| PTU \| EN \| M3)) /HSUSB1_STP/\
				290	MUX_VAL(CP(ETK_CTL_ES2), (IDIS \| PTU \| DIS \| M3)) /HSUSB1_CLK/\
				291	MUX_VAL(CP(ETK_D0_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DATA0/\
				292	MUX_VAL(CP(ETK_D1_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DATA1/\
				293	MUX_VAL(CP(ETK_D2_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DATA2/\
				294	MUX_VAL(CP(ETK_D3_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DATA7/\
				295	MUX_VAL(CP(ETK_D4_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DATA4/\
				296	MUX_VAL(CP(ETK_D5_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DATA5/\
				297	MUX_VAL(CP(ETK_D6_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DATA6/\
				298	MUX_VAL(CP(ETK_D7_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DATA3/\
				299	MUX_VAL(CP(ETK_D8_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_DIR/\
				300	MUX_VAL(CP(ETK_D9_ES2), (IEN \| PTU \| DIS \| M3)) /HSUSB1_NXT/\
				301	MUX_VAL(CP(D2D_MCAD1), (IEN \| PTD \| EN \| M0)) /d2d_mcad1/\
				302	MUX_VAL(CP(D2D_MCAD2), (IEN \| PTD \| EN \| M0)) /d2d_mcad2/\
				303	MUX_VAL(CP(D2D_MCAD3), (IEN \| PTD \| EN \| M0)) /d2d_mcad3/\
				304	MUX_VAL(CP(D2D_MCAD4), (IEN \| PTD \| EN \| M0)) /d2d_mcad4/\
				305	MUX_VAL(CP(D2D_MCAD5), (IEN \| PTD \| EN \| M0)) /d2d_mcad5/\
				306	MUX_VAL(CP(D2D_MCAD6), (IEN \| PTD \| EN \| M0)) /d2d_mcad6/\
				307	MUX_VAL(CP(D2D_MCAD7), (IEN \| PTD \| EN \| M0)) /d2d_mcad7/\
				308	MUX_VAL(CP(D2D_MCAD8), (IEN \| PTD \| EN \| M0)) /d2d_mcad8/\
				309	MUX_VAL(CP(D2D_MCAD9), (IEN \| PTD \| EN \| M0)) /d2d_mcad9/\
				310	MUX_VAL(CP(D2D_MCAD10), (IEN \| PTD \| EN \| M0)) /d2d_mcad10/\
				311	MUX_VAL(CP(D2D_MCAD11), (IEN \| PTD \| EN \| M0)) /d2d_mcad11/\
				312	MUX_VAL(CP(D2D_MCAD12), (IEN \| PTD \| EN \| M0)) /d2d_mcad12/\
				313	MUX_VAL(CP(D2D_MCAD13), (IEN \| PTD \| EN \| M0)) /d2d_mcad13/\
				314	MUX_VAL(CP(D2D_MCAD14), (IEN \| PTD \| EN \| M0)) /d2d_mcad14/\
				315	MUX_VAL(CP(D2D_MCAD15), (IEN \| PTD \| EN \| M0)) /d2d_mcad15/\
				316	MUX_VAL(CP(D2D_MCAD16), (IEN \| PTD \| EN \| M0)) /d2d_mcad16/\
				317	MUX_VAL(CP(D2D_MCAD17), (IEN \| PTD \| EN \| M0)) /d2d_mcad17/\
				318	MUX_VAL(CP(D2D_MCAD18), (IEN \| PTD \| EN \| M0)) /d2d_mcad18/\
				319	MUX_VAL(CP(D2D_MCAD19), (IEN \| PTD \| EN \| M0)) /d2d_mcad19/\
				320	MUX_VAL(CP(D2D_MCAD20), (IEN \| PTD \| EN \| M0)) /d2d_mcad20/\
				321	MUX_VAL(CP(D2D_MCAD21), (IEN \| PTD \| EN \| M0)) /d2d_mcad21/\
				322	MUX_VAL(CP(D2D_MCAD22), (IEN \| PTD \| EN \| M0)) /d2d_mcad22/\
				323	MUX_VAL(CP(D2D_MCAD23), (IEN \| PTD \| EN \| M0)) /d2d_mcad23/\
				324	MUX_VAL(CP(D2D_MCAD24), (IEN \| PTD \| EN \| M0)) /d2d_mcad24/\
				325	MUX_VAL(CP(D2D_MCAD25), (IEN \| PTD \| EN \| M0)) /d2d_mcad25/\
				326	MUX_VAL(CP(D2D_MCAD26), (IEN \| PTD \| EN \| M0)) /d2d_mcad26/\
				327	MUX_VAL(CP(D2D_MCAD27), (IEN \| PTD \| EN \| M0)) /d2d_mcad27/\
				328	MUX_VAL(CP(D2D_MCAD28), (IEN \| PTD \| EN \| M0)) /d2d_mcad28/\
				329	MUX_VAL(CP(D2D_MCAD29), (IEN \| PTD \| EN \| M0)) /d2d_mcad29/\
				330	MUX_VAL(CP(D2D_MCAD30), (IEN \| PTD \| EN \| M0)) /d2d_mcad30/\
				331	MUX_VAL(CP(D2D_MCAD31), (IEN \| PTD \| EN \| M0)) /d2d_mcad31/\
				332	MUX_VAL(CP(D2D_MCAD32), (IEN \| PTD \| EN \| M0)) /d2d_mcad32/\
				333	MUX_VAL(CP(D2D_MCAD33), (IEN \| PTD \| EN \| M0)) /d2d_mcad33/\
				334	MUX_VAL(CP(D2D_MCAD34), (IEN \| PTD \| EN \| M0)) /d2d_mcad34/\
				335	MUX_VAL(CP(D2D_MCAD35), (IEN \| PTD \| EN \| M0)) /d2d_mcad35/\
				336	MUX_VAL(CP(D2D_MCAD36), (IEN \| PTD \| EN \| M0)) /d2d_mcad36/\
				337	MUX_VAL(CP(D2D_CLK26MI), (IEN \| PTD \| DIS \| M0)) /d2d_clk26mi/\
				338	MUX_VAL(CP(D2D_NRESPWRON), (IEN \| PTD \| EN \| M0)) /d2d_nrespwron/\
				339	MUX_VAL(CP(D2D_NRESWARM), (IEN \| PTU \| EN \| M0)) /d2d_nreswarm /\
				340	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN \| PTD \| DIS \| M0)) /d2d_arm9nirq /\
				341	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN \| PTD \| DIS \| M0)) /d2d_uma2p6fiq/\
				342	MUX_VAL(CP(D2D_SPINT), (IEN \| PTD \| EN \| M0)) /d2d_spint/\
				343	MUX_VAL(CP(D2D_FRINT), (IEN \| PTD \| EN \| M0)) /d2d_frint/\
				344	MUX_VAL(CP(D2D_DMAREQ0), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq0/\
				345	MUX_VAL(CP(D2D_DMAREQ1), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq1/\
				346	MUX_VAL(CP(D2D_DMAREQ2), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq2/\
				347	MUX_VAL(CP(D2D_DMAREQ3), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq3/\
				348	MUX_VAL(CP(D2D_N3GTRST), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtrst/\
				349	MUX_VAL(CP(D2D_N3GTDI), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtdi/\
				350	MUX_VAL(CP(D2D_N3GTDO), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtdo/\
				351	MUX_VAL(CP(D2D_N3GTMS), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtms/\
				352	MUX_VAL(CP(D2D_N3GTCK), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtck/\
				353	MUX_VAL(CP(D2D_N3GRTCK), (IEN \| PTD \| DIS \| M0)) /d2d_n3grtck/\
				354	MUX_VAL(CP(D2D_MSTDBY), (IEN \| PTU \| EN \| M0)) /d2d_mstdby/\
				355	MUX_VAL(CP(D2D_SWAKEUP), (IEN \| PTD \| EN \| M0)) /d2d_swakeup/\
				356	MUX_VAL(CP(D2D_IDLEREQ), (IEN \| PTD \| DIS \| M0)) /d2d_idlereq/\
				357	MUX_VAL(CP(D2D_IDLEACK), (IEN \| PTU \| EN \| M0)) /d2d_idleack/\
				358	MUX_VAL(CP(D2D_MWRITE), (IEN \| PTD \| DIS \| M0)) /d2d_mwrite/\
				359	MUX_VAL(CP(D2D_SWRITE), (IEN \| PTD \| DIS \| M0)) /d2d_swrite/\
				360	MUX_VAL(CP(D2D_MREAD), (IEN \| PTD \| DIS \| M0)) /d2d_mread/\
				361	MUX_VAL(CP(D2D_SREAD), (IEN \| PTD \| DIS \| M0)) /d2d_sread/\
				362	MUX_VAL(CP(D2D_MBUSFLAG), (IEN \| PTD \| DIS \| M0)) /d2d_mbusflag/\
				363	MUX_VAL(CP(D2D_SBUSFLAG), (IEN \| PTD \| DIS \| M0)) /d2d_sbusflag/\
				364	MUX_VAL(CP(SDRC_CKE0), (IDIS \| PTU \| EN \| M0)) /sdrc_cke0/\
				365	MUX_VAL(CP(SDRC_CKE1), (IDIS \| PTU \| EN \| M0)) /sdrc_cke1/
Dirk Behme	d76070b	2009-04-17 14:27:56 +0200	[diff] [blame]	366
				367	#define MUX_BEAGLE_C() \
Steve Sakoman	ac92995	2010-08-19 20:56:11 -0700	[diff] [blame]	368	MUX_VAL(CP(MCBSP3_DX), (IEN \| PTD \| DIS \| M4)) /GPIO_140/\
				369	MUX_VAL(CP(MCBSP3_DR), (IEN \| PTD \| DIS \| M4)) /GPIO_142/\
				370	MUX_VAL(CP(MCBSP3_CLKX), (IEN \| PTD \| DIS \| M4)) /GPIO_141/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	371	MUX_VAL(CP(UART2_CTS), (IEN \| PTU \| EN \| M0)) /UART2_CTS/\
				372	MUX_VAL(CP(UART2_RTS), (IDIS \| PTD \| DIS \| M0)) /UART2_RTS/\
Alexander Holler	e1a2957	2011-04-19 09:27:23 -0400	[diff] [blame]	373	MUX_VAL(CP(UART2_TX), (IDIS \| PTD \| DIS \| M0)) /UART2_TX/\
				374	MUX_VAL(CP(UART2_RX), (IDIS \| PTU \| EN \| M4)) /GPIO_147/
Dirk Behme	d76070b	2009-04-17 14:27:56 +0200	[diff] [blame]	375
Steve Sakoman	ac92995	2010-08-19 20:56:11 -0700	[diff] [blame]	376	#define MUX_BEAGLE_XM() \
Steve Sakoman	c3b9983	2010-09-20 09:55:24 -0700	[diff] [blame]	377	MUX_VAL(CP(GPMC_NCS5), (IDIS \| PTD \| EN \| M4)) /GPIO_56/\
Evgeniy Dushistov	d65f50c	2015-05-12 22:17:10 +0300	[diff] [blame]	378	MUX_VAL(CP(GPMC_WAIT1), (IDIS \| PTU \| EN \| M4)) /GPIO_63/\
Steve Sakoman	c3b9983	2010-09-20 09:55:24 -0700	[diff] [blame]	379	MUX_VAL(CP(MMC1_DAT7), (IDIS \| PTU \| EN \| M4)) /GPIO_129/\
				380	MUX_VAL(CP(HDQ_SIO), (IDIS \| PTU \| EN \| M4)) /GPIO_170/\
Steve Sakoman	ac92995	2010-08-19 20:56:11 -0700	[diff] [blame]	381	MUX_VAL(CP(MCBSP3_DX), (IEN \| PTD \| DIS \| M4)) /GPIO_140/\
				382	MUX_VAL(CP(MCBSP3_DR), (IEN \| PTD \| DIS \| M4)) /GPIO_142/\
				383	MUX_VAL(CP(MCBSP3_CLKX), (IEN \| PTD \| DIS \| M4)) /GPIO_141/\
				384	MUX_VAL(CP(UART2_CTS), (IEN \| PTU \| EN \| M0)) /UART2_CTS/\
				385	MUX_VAL(CP(UART2_RTS), (IDIS \| PTD \| DIS \| M0)) /UART2_RTS/\
				386	MUX_VAL(CP(UART2_TX), (IDIS \| PTD \| DIS \| M0)) /UART2_TX/\
				387	MUX_VAL(CP(DSS_DATA0), (IDIS \| PTD \| DIS \| M7)) /safe_mode/\
				388	MUX_VAL(CP(DSS_DATA1), (IDIS \| PTD \| DIS \| M7)) /safe_mode/\
				389	MUX_VAL(CP(DSS_DATA2), (IDIS \| PTD \| DIS \| M7)) /safe_mode/\
				390	MUX_VAL(CP(DSS_DATA3), (IDIS \| PTD \| DIS \| M7)) /safe_mode/\
				391	MUX_VAL(CP(DSS_DATA4), (IDIS \| PTD \| DIS \| M7)) /safe_mode/\
				392	MUX_VAL(CP(DSS_DATA5), (IDIS \| PTD \| DIS \| M7)) /safe_mode/\
				393	MUX_VAL(CP(DSS_DATA18), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA0/\
				394	MUX_VAL(CP(DSS_DATA19), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA1/\
				395	MUX_VAL(CP(DSS_DATA20), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA2/\
				396	MUX_VAL(CP(DSS_DATA21), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA3/\
				397	MUX_VAL(CP(DSS_DATA22), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA4/\
				398	MUX_VAL(CP(DSS_DATA23), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA5/\
				399	MUX_VAL(CP(SYS_BOOT0), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA18/\
				400	MUX_VAL(CP(SYS_BOOT1), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA19/\
				401	MUX_VAL(CP(SYS_BOOT3), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA20/\
				402	MUX_VAL(CP(SYS_BOOT4), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA21/\
				403	MUX_VAL(CP(SYS_BOOT5), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA22/\
				404	MUX_VAL(CP(SYS_BOOT6), (IDIS \| PTD \| DIS \| M3)) /DSS_DATA23/
				405
Koen Kooi	b6241c2	2010-09-20 10:21:33 -0700	[diff] [blame]	406	#define MUX_TINCANTOOLS_ZIPPY() \
				407	MUX_VAL(CP(MMC2_CLK), (IEN \| PTU \| EN \| M0)) /MMC2_CLK/\
				408	MUX_VAL(CP(MMC2_CMD), (IEN \| PTU \| EN \| M0)) /MMC2_CMD/\
				409	MUX_VAL(CP(MMC2_DAT0), (IEN \| PTU \| EN \| M0)) /MMC2_DAT0/\
				410	MUX_VAL(CP(MMC2_DAT1), (IEN \| PTU \| EN \| M0)) /MMC2_DAT1/\
				411	MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M0)) /MMC2_DAT2/\
				412	MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M0)) /MMC2_DAT3/\
				413	MUX_VAL(CP(MMC2_DAT4), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_DAT0/\
				414	MUX_VAL(CP(MMC2_DAT5), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_DAT1/\
				415	MUX_VAL(CP(MMC2_DAT6), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_CMD/\
				416	MUX_VAL(CP(MMC2_DAT7), (IEN \| PTU \| EN \| M1)) /MMC2_CLKIN/\
				417	MUX_VAL(CP(MCBSP1_CLKR), (IEN \| PTU \| EN \| M1)) /MCSPI4_CLK/\
				418	MUX_VAL(CP(MCBSP1_FSR), (IEN \| PTU \| EN \| M4)) /GPIO_157/\
				419	MUX_VAL(CP(MCBSP1_DX), (IEN \| PTD \| EN \| M1)) /MCSPI4_SIMO/\
				420	MUX_VAL(CP(MCBSP1_DR), (IEN \| PTD \| DIS \| M1)) /MCSPI4_SOMI/\
				421	MUX_VAL(CP(MCBSP1_FSX), (IEN \| PTD \| EN \| M1)) /MCSPI4_CS0/\
				422	MUX_VAL(CP(MCBSP1_CLKX), (IEN \| PTD \| DIS \| M4)) /GPIO_162/\
				423	MUX_VAL(CP(MCBSP3_DX), (IEN \| PTD \| DIS \| M4)) /GPIO_140/\
				424	MUX_VAL(CP(MCBSP3_DR), (IEN \| PTD \| DIS \| M4)) /GPIO_142/\
				425	MUX_VAL(CP(MCBSP3_CLKX), (IEN \| PTD \| DIS \| M4)) /GPIO_141/
				426
				427	#define MUX_TINCANTOOLS_TRAINER() \
				428	MUX_VAL(CP(MMC2_CLK), (IEN \| PTU \| EN \| M4)) /GPIO_130/\
				429	MUX_VAL(CP(MMC2_CMD), (IEN \| PTU \| EN \| M4)) /GPIO_131/\
				430	MUX_VAL(CP(MMC2_DAT0), (IEN \| PTU \| EN \| M4)) /GPIO_132/\
				431	MUX_VAL(CP(MMC2_DAT1), (IEN \| PTU \| EN \| M4)) /GPIO_133/\
				432	MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M4)) /GPIO_134/\
				433	MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M4)) /GPIO_135/\
				434	MUX_VAL(CP(MMC2_DAT4), (IEN \| PTU \| EN \| M4)) /GPIO_136/\
				435	MUX_VAL(CP(MMC2_DAT5), (IEN \| PTU \| EN \| M4)) /GPIO_137/\
				436	MUX_VAL(CP(MMC2_DAT6), (IEN \| PTU \| EN \| M4)) /GPIO_138/\
				437	MUX_VAL(CP(MMC2_DAT7), (IEN \| PTU \| EN \| M4)) /GPIO_139/\
				438	MUX_VAL(CP(MCBSP3_DX), (IEN \| PTU \| EN \| M4)) /GPIO_140/\
				439	MUX_VAL(CP(MCBSP3_CLKX), (IEN \| PTU \| EN \| M4)) /GPIO_141/\
				440	MUX_VAL(CP(MCBSP1_CLKX), (IEN \| PTU \| EN \| M4)) /GPIO_162/
				441
				442	#define MUX_KBADC_BEAGLEFPGA() \
				443	MUX_VAL(CP(MCBSP1_CLKR), (IEN \| PTU \| DIS \| M1)) /MCSPI4_CLK/\
				444	MUX_VAL(CP(MCBSP1_DX), (IDIS \| PTU \| DIS \| M1)) /MCSPI4_SIMO/\
				445	MUX_VAL(CP(MCBSP1_DR), (IEN \| PTU \| EN \| M1)) /MCSPI4_SOMI/\
				446	MUX_VAL(CP(MCBSP1_FSX), (IDIS \| PTU \| DIS \| M1)) /MCSPI4_CS0/
				447
Koen Kooi	3d5dac6	2011-04-18 17:29:35 -0400	[diff] [blame]	448	#define MUX_BBTOYS_WIFI() \
				449	MUX_VAL(CP(MMC2_CLK), (IEN \| PTU \| EN \| M0)) /MMC2_CLK/\
				450	MUX_VAL(CP(MMC2_CMD), (IEN \| PTU \| EN \| M0)) /MMC2_CMD/\
				451	MUX_VAL(CP(MMC2_DAT0), (IEN \| PTU \| EN \| M0)) /MMC2_DAT0/\
				452	MUX_VAL(CP(MMC2_DAT1), (IEN \| PTU \| EN \| M0)) /MMC2_DAT1/\
				453	MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M0)) /MMC2_DAT2/\
				454	MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M0)) /MMC2_DAT3/\
				455	MUX_VAL(CP(MMC2_DAT4), (IDIS \| PTU \| EN \| M4)) /GPIO_136 FM_EN/BT_WU/\
				456	MUX_VAL(CP(MMC2_DAT5), (IEN \| PTU \| EN \| M4)) /GPIO_137 WLAN_IRQ/\
				457	MUX_VAL(CP(MMC2_DAT6), (IDIS \| PTU \| EN \| M4)) /GPIO_138 BT_EN/\
				458	MUX_VAL(CP(MMC2_DAT7), (IDIS \| PTU \| EN \| M4)) /GPIO_139 WLAN_EN/
				459
Jason Kridner	b8f6ac5	2011-04-19 14:01:13 -0500	[diff] [blame]	460	/*
				461	* Display Configuration
				462	*/
				463
				464	#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
				465	#define VENC_HEIGHT 0x00ef
				466	#define VENC_WIDTH 0x027f
				467
				468	/*
				469	* Configure VENC in DSS for Beagle to generate Color Bar
				470	*
				471	* Kindly refer to OMAP TRM for definition of these values.
				472	*/
				473	static const struct venc_regs venc_config_std_tv = {
				474	.status = 0x0000001B,
				475	.f_control = 0x00000040,
				476	.vidout_ctrl = 0x00000000,
				477	.sync_ctrl = 0x00008000,
				478	.llen = 0x00008359,
				479	.flens = 0x0000020C,
				480	.hfltr_ctrl = 0x00000000,
				481	.cc_carr_wss_carr = 0x043F2631,
				482	.c_phase = 0x00000024,
				483	.gain_u = 0x00000130,
				484	.gain_v = 0x00000198,
				485	.gain_y = 0x000001C0,
				486	.black_level = 0x0000006A,
				487	.blank_level = 0x0000005C,
				488	.x_color = 0x00000000,
				489	.m_control = 0x00000001,
				490	.bstamp_wss_data = 0x0000003F,
				491	.s_carr = 0x21F07C1F,
				492	.line21 = 0x00000000,
				493	.ln_sel = 0x00000015,
				494	.l21__wc_ctl = 0x00001400,
				495	.htrigger_vtrigger = 0x00000000,
				496	.savid__eavid = 0x069300F4,
				497	.flen__fal = 0x0016020C,
				498	.lal__phase_reset = 0x00060107,
				499	.hs_int_start_stop_x = 0x008D034E,
				500	.hs_ext_start_stop_x = 0x000F0359,
				501	.vs_int_start_x = 0x01A00000,
				502	.vs_int_stop_x__vs_int_start_y = 0x020501A0,
				503	.vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
				504	.vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
				505	.vs_ext_stop_y = 0x00000006,
				506	.avid_start_stop_x = 0x03480079,
				507	.avid_start_stop_y = 0x02040024,
				508	.fid_int_start_x__fid_int_start_y = 0x0001008A,
				509	.fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
				510	.fid_ext_start_y__fid_ext_offset_y = 0x01060006,
				511	.tvdetgp_int_start_stop_x = 0x00140001,
				512	.tvdetgp_int_start_stop_y = 0x00010001,
				513	.gen_ctrl = 0x00FF0000,
				514	.output_control = 0x0000000D,
				515	.dac_b__dac_c = 0x00000000
				516	};
				517
				518	/*
				519	* Configure Timings for DVI D
				520	*/
				521	static const struct panel_config dvid_cfg = {
Peter Meerwald	6c65484	2012-02-02 12:51:01 +0000	[diff] [blame]	522	.timing_h = 0x0ff03f31, /* Horizontal timing */
Jason Kridner	b8f6ac5	2011-04-19 14:01:13 -0500	[diff] [blame]	523	.timing_v = 0x01400504, /* Vertical timing */
				524	.pol_freq = 0x00007028, /* Pol Freq */
				525	.divisor = 0x00010006, /* 72Mhz Pixel Clock */
				526	.lcd_size = 0x02ff03ff, /* 1024x768 */
				527	.panel_type = 0x01, /* TFT */
				528	.data_lines = 0x03, /* 24 Bit RGB */
				529	.load_mode = 0x02, /* Frame Mode */
Nikita Kiryanov	65bd0af	2013-01-30 21:39:55 +0000	[diff] [blame]	530	.panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
				531	.gfx_format = GFXFORMAT_RGB24_UNPACKED,
Jason Kridner	b8f6ac5	2011-04-19 14:01:13 -0500	[diff] [blame]	532	};
				533
				534	static const struct panel_config dvid_cfg_xm = {
Peter Meerwald	6c65484	2012-02-02 12:51:01 +0000	[diff] [blame]	535	.timing_h = 0x1a4024c9, /* Horizontal timing */
Jason Kridner	b8f6ac5	2011-04-19 14:01:13 -0500	[diff] [blame]	536	.timing_v = 0x02c00509, /* Vertical timing */
				537	.pol_freq = 0x00007028, /* Pol Freq */
				538	.divisor = 0x00010001, /* 96MHz Pixel Clock */
				539	.lcd_size = 0x02ff03ff, /* 1024x768 */
				540	.panel_type = 0x01, /* TFT */
				541	.data_lines = 0x03, /* 24 Bit RGB */
				542	.load_mode = 0x02, /* Frame Mode */
Nikita Kiryanov	65bd0af	2013-01-30 21:39:55 +0000	[diff] [blame]	543	.panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
				544	.gfx_format = GFXFORMAT_RGB24_UNPACKED,
Jason Kridner	b8f6ac5	2011-04-19 14:01:13 -0500	[diff] [blame]	545	};
Dirk Behme	2781f80	2009-01-27 18:19:12 +0100	[diff] [blame]	546	#endif