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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkda55c6e2004-01-20 23:12:12 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk0f8c9762002-08-19 11:57:05 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
wdenkda55c6e2004-01-20 23:12:12 +000037#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */
wdenk0f8c9762002-08-19 11:57:05 +000038
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
40
wdenkda55c6e2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenk0f8c9762002-08-19 11:57:05 +000042
wdenkda55c6e2004-01-20 23:12:12 +000043#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
wdenk0f8c9762002-08-19 11:57:05 +000044
wdenkda55c6e2004-01-20 23:12:12 +000045#define CONFIG_CPUCLOCK 66
46#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
wdenk0f8c9762002-08-19 11:57:05 +000047
wdenkda55c6e2004-01-20 23:12:12 +000048#define CONFIG_BAUDRATE 9600
wdenk0f8c9762002-08-19 11:57:05 +000049#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
50#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */
51
wdenkda55c6e2004-01-20 23:12:12 +000052#undef CONFIG_BOOTARGS
wdenk0f8c9762002-08-19 11:57:05 +000053
54#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk0f8c9762002-08-19 11:57:05 +000056
57#undef CONFIG_WATCHDOG /* watchdog disabled */
58
59#define CONFIG_IPADDR 10.0.18.222
60#define CONFIG_SERVERIP 10.0.18.190
61
Jon Loeliger4e4f2072007-07-07 20:40:43 -050062
63/*
Jon Loeligerf5709d12007-07-10 09:02:57 -050064 * BOOTP options
65 */
66#define CONFIG_BOOTP_BOOTFILESIZE
67#define CONFIG_BOOTP_BOOTPATH
68#define CONFIG_BOOTP_GATEWAY
69#define CONFIG_BOOTP_HOSTNAME
70
71
72/*
Jon Loeliger4e4f2072007-07-07 20:40:43 -050073 * Command line configuration.
74 */
75#include <config_cmd_default.h>
76
77#define CONFIG_CMD_BSP
78
wdenk0f8c9762002-08-19 11:57:05 +000079
80#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
81#define CONFIG_SOFT_I2C /* Software I2C support enabled */
82#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenk0f8c9762002-08-19 11:57:05 +000084
wdenk0f8c9762002-08-19 11:57:05 +000085/*
86 * Miscellaneous configurable options
87 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_LONGHELP /* undef to save memory */
89#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger4e4f2072007-07-07 20:40:43 -050090#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000092#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000094#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020095#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
96#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
97#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000098
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenk0f8c9762002-08-19 11:57:05 +0000100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
102#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000103
104/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk57b2d802003-06-27 21:31:46 +0000106 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
wdenk0f8c9762002-08-19 11:57:05 +0000107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000109
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000111
112#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
113
114/*-----------------------------------------------------------------------
115 * Definitions for initial stack pointer and data area (in DPRAM)
116 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200118#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200119#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000121
122/*-----------------------------------------------------------------------
123 * Start addresses for the final memory configuration
124 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000126 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchsc20a8722009-02-20 10:19:16 +0100128#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Matthias Fuchsc20a8722009-02-20 10:19:16 +0100130#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk0f8c9762002-08-19 11:57:05 +0000132
133/*
134 * For booting Linux, the board info and command line data
135 * have to be in the first 8 MB of memory, since this is
136 * the maximum mapped by the Linux kernel during initialization.
137 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000139/*-----------------------------------------------------------------------
140 * FLASH organization
141 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
143#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
146#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000147
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
149#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
150#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
wdenk0f8c9762002-08-19 11:57:05 +0000151/*
152 * The following defines are added for buggy IOP480 byte interface.
153 * All other boards should use the standard values (CPCI405 etc.)
154 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */
156#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */
157#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */
wdenk0f8c9762002-08-19 11:57:05 +0000158
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk0f8c9762002-08-19 11:57:05 +0000160
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200161#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200162#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
163#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000164
165#if 0
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200166#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
wdenk0f8c9762002-08-19 11:57:05 +0000167#else
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200168#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
wdenk0f8c9762002-08-19 11:57:05 +0000169#endif
170
171/*-----------------------------------------------------------------------
172 * PCI stuff
173 */
174#define CONFIG_PCI /* include pci support */
175#undef CONFIG_PCI_PNP
176
wdenkda55c6e2004-01-20 23:12:12 +0000177#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenk0f8c9762002-08-19 11:57:05 +0000178
179#define CONFIG_TULIP
180
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_ETH_DEV_FN 0x0000
182#define CONFIG_SYS_ETH_IOBASE 0x0fff0000
183#define CONFIG_SYS_PCI9054_DEV_FN 0x0800
184#define CONFIG_SYS_PCI9054_IOBASE 0x0eff0000
wdenk0f8c9762002-08-19 11:57:05 +0000185
wdenk0f8c9762002-08-19 11:57:05 +0000186/*
187 * Init Memory Controller:
188 *
189 * BR0/1 and OR0/1 (FLASH)
190 */
191
192#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
193
wdenk0f8c9762002-08-19 11:57:05 +0000194#endif /* __CONFIG_H */