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Lokesh Vutla5af02db2018-08-27 15:57:32 +05301/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Texas Instruments System Control Interface Protocol
4 * Based on include/linux/soc/ti/ti_sci_protocol.h from Linux.
5 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -05006 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutla5af02db2018-08-27 15:57:32 +05307 * Nishanth Menon
8 * Lokesh Vutla <lokeshvutla@ti.com>
9 */
10
11#ifndef __TISCI_PROTOCOL_H
12#define __TISCI_PROTOCOL_H
13
Suman Anna2cde1a22021-07-27 18:24:39 -050014#include <linux/bitops.h>
15#include <linux/err.h>
16
Lokesh Vutla5af02db2018-08-27 15:57:32 +053017/**
18 * struct ti_sci_version_info - version information structure
19 * @abi_major: Major ABI version. Change here implies risk of backward
20 * compatibility break.
21 * @abi_minor: Minor ABI version. Change here implies new feature addition,
22 * or compatible change in ABI.
23 * @firmware_revision: Firmware revision (not usually used).
24 * @firmware_description: Firmware description (not usually used).
25 */
26struct ti_sci_version_info {
27 u8 abi_major;
28 u8 abi_minor;
29 u16 firmware_revision;
30 char firmware_description[32];
31};
32
33struct ti_sci_handle;
34
35/**
Andreas Dannenberg5299c4c2018-08-27 15:57:33 +053036 * struct ti_sci_board_ops - Board config operations
37 * @board_config: Command to set the board configuration
38 * Returns 0 for successful exclusive request, else returns
39 * corresponding error message.
40 * @board_config_rm: Command to set the board resource management
41 * configuration
42 * Returns 0 for successful exclusive request, else returns
43 * corresponding error message.
44 * @board_config_security: Command to set the board security configuration
45 * Returns 0 for successful exclusive request, else returns
46 * corresponding error message.
47 * @board_config_pm: Command to trigger and set the board power and clock
48 * management related configuration
49 * Returns 0 for successful exclusive request, else returns
50 * corresponding error message.
51 */
52struct ti_sci_board_ops {
53 int (*board_config)(const struct ti_sci_handle *handle,
54 u64 addr, u32 size);
55 int (*board_config_rm)(const struct ti_sci_handle *handle,
56 u64 addr, u32 size);
57 int (*board_config_security)(const struct ti_sci_handle *handle,
58 u64 addr, u32 size);
59 int (*board_config_pm)(const struct ti_sci_handle *handle,
60 u64 addr, u32 size);
61};
62
63/**
Andreas Dannenberg24a4d5e2018-08-27 15:57:34 +053064 * struct ti_sci_dev_ops - Device control operations
65 * @get_device: Command to request for device managed by TISCI
66 * Returns 0 for successful exclusive request, else returns
67 * corresponding error message.
68 * @idle_device: Command to idle a device managed by TISCI
69 * Returns 0 for successful exclusive request, else returns
70 * corresponding error message.
71 * @put_device: Command to release a device managed by TISCI
72 * Returns 0 for successful release, else returns corresponding
73 * error message.
74 * @is_valid: Check if the device ID is a valid ID.
75 * Returns 0 if the ID is valid, else returns corresponding error.
76 * @get_context_loss_count: Command to retrieve context loss counter - this
77 * increments every time the device looses context. Overflow
78 * is possible.
79 * - count: pointer to u32 which will retrieve counter
80 * Returns 0 for successful information request and count has
81 * proper data, else returns corresponding error message.
82 * @is_idle: Reports back about device idle state
83 * - req_state: Returns requested idle state
84 * Returns 0 for successful information request and req_state and
85 * current_state has proper data, else returns corresponding error
86 * message.
87 * @is_stop: Reports back about device stop state
88 * - req_state: Returns requested stop state
89 * - current_state: Returns current stop state
90 * Returns 0 for successful information request and req_state and
91 * current_state has proper data, else returns corresponding error
92 * message.
93 * @is_on: Reports back about device ON(or active) state
94 * - req_state: Returns requested ON state
95 * - current_state: Returns current ON state
96 * Returns 0 for successful information request and req_state and
97 * current_state has proper data, else returns corresponding error
98 * message.
99 * @is_transitioning: Reports back if the device is in the middle of transition
100 * of state.
101 * -current_state: Returns 'true' if currently transitioning.
102 * @set_device_resets: Command to configure resets for device managed by TISCI.
103 * -reset_state: Device specific reset bit field
104 * Returns 0 for successful request, else returns
105 * corresponding error message.
106 * @get_device_resets: Command to read state of resets for device managed
107 * by TISCI.
108 * -reset_state: pointer to u32 which will retrieve resets
109 * Returns 0 for successful request, else returns
110 * corresponding error message.
Lokesh Vutla0d0412a2019-06-07 19:24:41 +0530111 * @release_exclusive_devices: Command to release all the exclusive devices
112 * attached to this host. This should be used very carefully
113 * and only at the end of execution of your software.
Andreas Dannenberg24a4d5e2018-08-27 15:57:34 +0530114 *
115 * NOTE: for all these functions, the following parameters are generic in
116 * nature:
117 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
118 * -id: Device Identifier
119 *
120 * Request for the device - NOTE: the client MUST maintain integrity of
121 * usage count by balancing get_device with put_device. No refcounting is
122 * managed by driver for that purpose.
123 */
124struct ti_sci_dev_ops {
125 int (*get_device)(const struct ti_sci_handle *handle, u32 id);
Lokesh Vutlaf5613002019-06-07 19:24:39 +0530126 int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
Andreas Dannenberg24a4d5e2018-08-27 15:57:34 +0530127 int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
Lokesh Vutlaf5613002019-06-07 19:24:39 +0530128 int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
129 u32 id);
Andreas Dannenberg24a4d5e2018-08-27 15:57:34 +0530130 int (*put_device)(const struct ti_sci_handle *handle, u32 id);
131 int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
132 int (*get_context_loss_count)(const struct ti_sci_handle *handle,
133 u32 id, u32 *count);
134 int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
135 bool *requested_state);
136 int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
137 bool *req_state, bool *current_state);
138 int (*is_on)(const struct ti_sci_handle *handle, u32 id,
139 bool *req_state, bool *current_state);
140 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
141 bool *current_state);
142 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
143 u32 reset_state);
144 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
145 u32 *reset_state);
Lokesh Vutla0d0412a2019-06-07 19:24:41 +0530146 int (*release_exclusive_devices)(const struct ti_sci_handle *handle);
Andreas Dannenberg24a4d5e2018-08-27 15:57:34 +0530147};
148
149/**
Lokesh Vutlad10c80c2018-08-27 15:57:35 +0530150 * struct ti_sci_clk_ops - Clock control operations
151 * @get_clock: Request for activation of clock and manage by processor
152 * - needs_ssc: 'true' if Spread Spectrum clock is desired.
153 * - can_change_freq: 'true' if frequency change is desired.
154 * - enable_input_term: 'true' if input termination is desired.
155 * @idle_clock: Request for Idling a clock managed by processor
156 * @put_clock: Release the clock to be auto managed by TISCI
157 * @is_auto: Is the clock being auto managed
158 * - req_state: state indicating if the clock is auto managed
159 * @is_on: Is the clock ON
160 * - req_state: if the clock is requested to be forced ON
161 * - current_state: if the clock is currently ON
162 * @is_off: Is the clock OFF
163 * - req_state: if the clock is requested to be forced OFF
164 * - current_state: if the clock is currently Gated
165 * @set_parent: Set the clock source of a specific device clock
166 * - parent_id: Parent clock identifier to set.
167 * @get_parent: Get the current clock source of a specific device clock
168 * - parent_id: Parent clock identifier which is the parent.
169 * @get_num_parents: Get the number of parents of the current clock source
170 * - num_parents: returns the number of parent clocks.
171 * @get_best_match_freq: Find a best matching frequency for a frequency
172 * range.
173 * - match_freq: Best matching frequency in Hz.
174 * @set_freq: Set the Clock frequency
175 * @get_freq: Get the Clock frequency
176 * - current_freq: Frequency in Hz that the clock is at.
177 *
178 * NOTE: for all these functions, the following parameters are generic in
179 * nature:
180 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
181 * -did: Device identifier this request is for
182 * -cid: Clock identifier for the device for this request.
183 * Each device has it's own set of clock inputs. This indexes
184 * which clock input to modify.
185 * -min_freq: The minimum allowable frequency in Hz. This is the minimum
186 * allowable programmed frequency and does not account for clock
187 * tolerances and jitter.
188 * -target_freq: The target clock frequency in Hz. A frequency will be
189 * processed as close to this target frequency as possible.
190 * -max_freq: The maximum allowable frequency in Hz. This is the maximum
191 * allowable programmed frequency and does not account for clock
192 * tolerances and jitter.
193 *
194 * Request for the clock - NOTE: the client MUST maintain integrity of
195 * usage count by balancing get_clock with put_clock. No refcounting is
196 * managed by driver for that purpose.
197 */
198struct ti_sci_clk_ops {
199 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid,
200 bool needs_ssc, bool can_change_freq,
201 bool enable_input_term);
202 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
203 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
204 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u8 cid,
205 bool *req_state);
206 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u8 cid,
207 bool *req_state, bool *current_state);
208 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u8 cid,
209 bool *req_state, bool *current_state);
210 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
211 u8 parent_id);
212 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
213 u8 *parent_id);
214 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
215 u8 cid, u8 *num_parents);
216 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
217 u8 cid, u64 min_freq, u64 target_freq,
218 u64 max_freq, u64 *match_freq);
219 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
220 u64 min_freq, u64 target_freq, u64 max_freq);
221 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
222 u64 *current_freq);
223};
224
225/**
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530226 * struct ti_sci_rm_core_ops - Resource management core operations
227 * @get_range: Get a range of resources belonging to ti sci host.
228 * @get_rage_from_shost: Get a range of resources belonging to
229 * specified host id.
230 * - s_host: Host processing entity to which the
231 * resources are allocated
232 *
233 * NOTE: for these functions, all the parameters are consolidated and defined
234 * as below:
235 * - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
236 * - dev_id: TISCI device ID.
237 * - subtype: Resource assignment subtype that is being requested
238 * from the given device.
239 * - range_start: Start index of the resource range
240 * - range_end: Number of resources in the range
241 */
242struct ti_sci_rm_core_ops {
243 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
244 u8 subtype, u16 *range_start, u16 *range_num);
245 int (*get_range_from_shost)(const struct ti_sci_handle *handle,
246 u32 dev_id, u8 subtype, u8 s_host,
247 u16 *range_start, u16 *range_num);
248};
249
250/**
Andreas Dannenberg5bd08372018-08-27 15:57:36 +0530251 * struct ti_sci_core_ops - SoC Core Operations
252 * @reboot_device: Reboot the SoC
253 * Returns 0 for successful request(ideally should never return),
254 * else returns corresponding error value.
Lokesh Vutla032dce82019-03-08 11:47:32 +0530255 * @query_msmc: Query the size of available msmc
256 * Return 0 for successful query else appropriate error value.
Andreas Dannenberg5bd08372018-08-27 15:57:36 +0530257 */
258struct ti_sci_core_ops {
259 int (*reboot_device)(const struct ti_sci_handle *handle);
Lokesh Vutla032dce82019-03-08 11:47:32 +0530260 int (*query_msmc)(const struct ti_sci_handle *handle,
261 u64 *msmc_start, u64 *msmc_end);
Andreas Dannenberg5bd08372018-08-27 15:57:36 +0530262};
263
264/**
Lokesh Vutlab8856af2018-08-27 15:57:37 +0530265 * struct ti_sci_proc_ops - Processor specific operations.
266 *
267 * @proc_request: Request for controlling a physical processor.
268 * The requesting host should be in the processor access list.
269 * @proc_release: Relinquish a physical processor control
270 * @proc_handover: Handover a physical processor control to another host
271 * in the permitted list.
272 * @set_proc_boot_cfg: Base configuration of the processor
273 * @set_proc_boot_ctrl: Setup limited control flags in specific cases.
274 * @proc_auth_boot_image:
275 * @get_proc_boot_status: Get the state of physical processor
Andreas Dannenbergca08cb32019-06-07 19:24:40 +0530276 * @proc_shutdown_no_wait: Shutdown a core without requesting or waiting for a
277 * response.
Lokesh Vutlab8856af2018-08-27 15:57:37 +0530278 *
279 * NOTE: for all these functions, the following parameters are generic in
280 * nature:
281 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
282 * -pid: Processor ID
283 *
284 */
285struct ti_sci_proc_ops {
286 int (*proc_request)(const struct ti_sci_handle *handle, u8 pid);
287 int (*proc_release)(const struct ti_sci_handle *handle, u8 pid);
288 int (*proc_handover)(const struct ti_sci_handle *handle, u8 pid,
289 u8 hid);
290 int (*set_proc_boot_cfg)(const struct ti_sci_handle *handle, u8 pid,
291 u64 bv, u32 cfg_set, u32 cfg_clr);
292 int (*set_proc_boot_ctrl)(const struct ti_sci_handle *handle, u8 pid,
293 u32 ctrl_set, u32 ctrl_clr);
Andrew F. Davis7aa9a082019-04-12 12:54:44 -0400294 int (*proc_auth_boot_image)(const struct ti_sci_handle *handle,
295 u64 *image_addr, u32 *image_size);
Lokesh Vutlab8856af2018-08-27 15:57:37 +0530296 int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
297 u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
298 u32 *sts_flags);
Andreas Dannenbergca08cb32019-06-07 19:24:40 +0530299 int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle,
300 u8 pid);
Lokesh Vutlab8856af2018-08-27 15:57:37 +0530301};
302
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530303#define TI_SCI_RING_MODE_RING (0)
304#define TI_SCI_RING_MODE_MESSAGE (1)
305#define TI_SCI_RING_MODE_CREDENTIALS (2)
306#define TI_SCI_RING_MODE_QM (3)
307
308#define TI_SCI_MSG_UNUSED_SECONDARY_HOST TI_SCI_RM_NULL_U8
309
310/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
311#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
312/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
313#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
314 /* RA config.count parameter is valid for RM ring configure TI_SCI message */
315#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
316/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
317#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
318/* RA config.size parameter is valid for RM ring configure TI_SCI message */
319#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
320/* RA config.order_id parameter is valid for RM ring configure TISCI message */
321#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
322
323#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
324 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
325 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
326 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
327 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
328 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
329
330/**
331 * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
332 * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530333 */
334struct ti_sci_rm_ringacc_ops {
335 int (*config)(const struct ti_sci_handle *handle,
336 u32 valid_params, u16 nav_id, u16 index,
337 u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
338 u8 size, u8 order_id
339 );
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530340};
341
342/**
343 * struct ti_sci_rm_psil_ops - PSI-L thread operations
344 * @pair: pair PSI-L source thread to a destination thread.
345 * If the src_thread is mapped to UDMA tchan, the corresponding channel's
346 * TCHAN_THRD_ID register is updated.
347 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
348 * RCHAN_THRD_ID register is updated.
349 * @unpair: unpair PSI-L source thread from a destination thread.
350 * If the src_thread is mapped to UDMA tchan, the corresponding channel's
351 * TCHAN_THRD_ID register is cleared.
352 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
353 * RCHAN_THRD_ID register is cleared.
354 */
355struct ti_sci_rm_psil_ops {
356 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
357 u32 src_thread, u32 dst_thread);
358 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
359 u32 src_thread, u32 dst_thread);
360};
361
362/* UDMAP channel types */
363#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
364#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
365#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
366#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
367#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
368#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
369
370/* UDMAP channel atypes */
371#define TI_SCI_RM_UDMAP_ATYPE_PHYS 0
372#define TI_SCI_RM_UDMAP_ATYPE_INTERMEDIATE 1
373#define TI_SCI_RM_UDMAP_ATYPE_VIRTUAL 2
374
375/* UDMAP channel scheduling priorities */
376#define TI_SCI_RM_UDMAP_SCHED_PRIOR_HIGH 0
377#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDHIGH 1
378#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDLOW 2
379#define TI_SCI_RM_UDMAP_SCHED_PRIOR_LOW 3
380
381#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
382#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
383
Vignesh Raghavendraa8a2b8a2021-05-10 20:06:02 +0530384#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
385#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
386#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
387
388#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
389#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
390
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530391/* UDMAP TX/RX channel valid_params common declarations */
392#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
393#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
394#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
395#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
396#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
397#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
398#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
399#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
400#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
Vignesh Raghavendraa8a2b8a2021-05-10 20:06:02 +0530401#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530402
403/**
404 * Configures a Navigator Subsystem UDMAP transmit channel
405 *
406 * Configures a Navigator Subsystem UDMAP transmit channel registers.
407 * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
408 */
409struct ti_sci_msg_rm_udmap_tx_ch_cfg {
410 u32 valid_params;
411#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
412#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
413#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
414#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
415#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
Vignesh Raghavendraa8a2b8a2021-05-10 20:06:02 +0530416#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
417#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530418 u16 nav_id;
419 u16 index;
420 u8 tx_pause_on_err;
421 u8 tx_filt_einfo;
422 u8 tx_filt_pswords;
423 u8 tx_atype;
424 u8 tx_chan_type;
425 u8 tx_supr_tdpkt;
426 u16 tx_fetch_size;
427 u8 tx_credit_count;
428 u16 txcq_qnum;
429 u8 tx_priority;
430 u8 tx_qos;
431 u8 tx_orderid;
432 u16 fdepth;
433 u8 tx_sched_priority;
Vignesh Raghavendraa8a2b8a2021-05-10 20:06:02 +0530434 u8 tx_burst_size;
435 u8 tx_tdtype;
436 u8 extended_ch_type;
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530437};
438
439/**
440 * Configures a Navigator Subsystem UDMAP receive channel
441 *
442 * Configures a Navigator Subsystem UDMAP receive channel registers.
443 * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
444 */
445struct ti_sci_msg_rm_udmap_rx_ch_cfg {
446 u32 valid_params;
447#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
448#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
449#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
450#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
451 u16 nav_id;
452 u16 index;
453 u16 rx_fetch_size;
454 u16 rxcq_qnum;
455 u8 rx_priority;
456 u8 rx_qos;
457 u8 rx_orderid;
458 u8 rx_sched_priority;
459 u16 flowid_start;
460 u16 flowid_cnt;
461 u8 rx_pause_on_err;
462 u8 rx_atype;
463 u8 rx_chan_type;
464 u8 rx_ignore_short;
465 u8 rx_ignore_long;
Vignesh Raghavendraa8a2b8a2021-05-10 20:06:02 +0530466 u8 rx_burst_size;
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530467};
468
469/**
470 * Configures a Navigator Subsystem UDMAP receive flow
471 *
472 * Configures a Navigator Subsystem UDMAP receive flow's registers.
473 * See @tis_ci_msg_rm_udmap_flow_cfg_req
474 */
475struct ti_sci_msg_rm_udmap_flow_cfg {
476 u32 valid_params;
477#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
478#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
479#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
480#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
481#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
482#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
483#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
484#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
485#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
486#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
487#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
488#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
489#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
490#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
491#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
492#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
493#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
494#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
495#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
496 u16 nav_id;
497 u16 flow_index;
498 u8 rx_einfo_present;
499 u8 rx_psinfo_present;
500 u8 rx_error_handling;
501 u8 rx_desc_type;
502 u16 rx_sop_offset;
503 u16 rx_dest_qnum;
504 u8 rx_src_tag_hi;
505 u8 rx_src_tag_lo;
506 u8 rx_dest_tag_hi;
507 u8 rx_dest_tag_lo;
508 u8 rx_src_tag_hi_sel;
509 u8 rx_src_tag_lo_sel;
510 u8 rx_dest_tag_hi_sel;
511 u8 rx_dest_tag_lo_sel;
512 u16 rx_fdq0_sz0_qnum;
513 u16 rx_fdq1_qnum;
514 u16 rx_fdq2_qnum;
515 u16 rx_fdq3_qnum;
516 u8 rx_ps_location;
517};
518
Lokesh Vutlab8856af2018-08-27 15:57:37 +0530519/**
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530520 * struct ti_sci_rm_udmap_ops - UDMA Management operations
521 * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
522 * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
523 * @rx_flow_cfg: configure SoC Navigator Subsystem UDMA receive flow.
524 */
525struct ti_sci_rm_udmap_ops {
526 int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
527 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
528 int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
529 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
530 int (*rx_flow_cfg)(
531 const struct ti_sci_handle *handle,
532 const struct ti_sci_msg_rm_udmap_flow_cfg *params);
533};
534
535/**
Andrew F. Davis2aafc0c2019-04-12 12:54:43 -0400536 * struct ti_sci_msg_fwl_region_cfg - Request and Response for firewalls settings
537 *
538 * @fwl_id: Firewall ID in question
539 * @region: Region or channel number to set config info
540 * This field is unused in case of a simple firewall and must be initialized
541 * to zero. In case of a region based firewall, this field indicates the
542 * region in question. (index starting from 0) In case of a channel based
543 * firewall, this field indicates the channel in question (index starting
544 * from 0)
545 * @n_permission_regs: Number of permission registers to set
546 * @control: Contents of the firewall CONTROL register to set
547 * @permissions: Contents of the firewall PERMISSION register to set
548 * @start_address: Contents of the firewall START_ADDRESS register to set
549 * @end_address: Contents of the firewall END_ADDRESS register to set
550 */
551struct ti_sci_msg_fwl_region {
552 u16 fwl_id;
553 u16 region;
554 u32 n_permission_regs;
555 u32 control;
556 u32 permissions[3];
557 u64 start_address;
558 u64 end_address;
559} __packed;
560
561/**
562 * \brief Request and Response for firewall owner change
563 *
564 * @fwl_id: Firewall ID in question
565 * @region: Region or channel number to set config info
566 * This field is unused in case of a simple firewall and must be initialized
567 * to zero. In case of a region based firewall, this field indicates the
568 * region in question. (index starting from 0) In case of a channel based
569 * firewall, this field indicates the channel in question (index starting
570 * from 0)
571 * @n_permission_regs: Number of permission registers <= 3
572 * @control: Control register value for this region
573 * @owner_index: New owner index to change to. Owner indexes are setup in DMSC firmware boot configuration data
574 * @owner_privid: New owner priv-id, used to lookup owner_index is not known, must be set to zero otherwise
575 * @owner_permission_bits: New owner permission bits
576 */
577struct ti_sci_msg_fwl_owner {
578 u16 fwl_id;
579 u16 region;
580 u8 owner_index;
581 u8 owner_privid;
582 u16 owner_permission_bits;
583} __packed;
584
585/**
586 * struct ti_sci_fwl_ops - Firewall specific operations
587 * @set_fwl_region: Request for configuring the firewall permissions.
588 * @get_fwl_region: Request for retrieving the firewall permissions.
589 * @change_fwl_owner: Request for a change of firewall owner.
590 */
591struct ti_sci_fwl_ops {
592 int (*set_fwl_region)(const struct ti_sci_handle *handle, const struct ti_sci_msg_fwl_region *region);
593 int (*get_fwl_region)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_region *region);
594 int (*change_fwl_owner)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_owner *owner);
595};
596
597/**
Andreas Dannenberg5299c4c2018-08-27 15:57:33 +0530598 * struct ti_sci_ops - Function support for TI SCI
599 * @board_ops: Miscellaneous operations
Andreas Dannenberg24a4d5e2018-08-27 15:57:34 +0530600 * @dev_ops: Device specific operations
Lokesh Vutlad10c80c2018-08-27 15:57:35 +0530601 * @clk_ops: Clock specific operations
Andreas Dannenberg5bd08372018-08-27 15:57:36 +0530602 * @core_ops: Core specific operations
Lokesh Vutlab8856af2018-08-27 15:57:37 +0530603 * @proc_ops: Processor specific operations
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530604 * @ring_ops: Ring Accelerator Management operations
Andrew F. Davis2aafc0c2019-04-12 12:54:43 -0400605 * @fw_ops: Firewall specific operations
Andreas Dannenberg5299c4c2018-08-27 15:57:33 +0530606 */
607struct ti_sci_ops {
608 struct ti_sci_board_ops board_ops;
Andreas Dannenberg24a4d5e2018-08-27 15:57:34 +0530609 struct ti_sci_dev_ops dev_ops;
Lokesh Vutlad10c80c2018-08-27 15:57:35 +0530610 struct ti_sci_clk_ops clk_ops;
Andreas Dannenberg5bd08372018-08-27 15:57:36 +0530611 struct ti_sci_core_ops core_ops;
Lokesh Vutlab8856af2018-08-27 15:57:37 +0530612 struct ti_sci_proc_ops proc_ops;
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530613 struct ti_sci_rm_core_ops rm_core_ops;
614 struct ti_sci_rm_ringacc_ops rm_ring_ops;
615 struct ti_sci_rm_psil_ops rm_psil_ops;
616 struct ti_sci_rm_udmap_ops rm_udmap_ops;
Andrew F. Davis2aafc0c2019-04-12 12:54:43 -0400617 struct ti_sci_fwl_ops fwl_ops;
Andreas Dannenberg5299c4c2018-08-27 15:57:33 +0530618};
619
620/**
Lokesh Vutla5af02db2018-08-27 15:57:32 +0530621 * struct ti_sci_handle - Handle returned to TI SCI clients for usage.
Andreas Dannenberg5299c4c2018-08-27 15:57:33 +0530622 * @ops: operations that are made available to TI SCI clients
Lokesh Vutla5af02db2018-08-27 15:57:32 +0530623 * @version: structure containing version information
624 */
625struct ti_sci_handle {
Andreas Dannenberg5299c4c2018-08-27 15:57:33 +0530626 struct ti_sci_ops ops;
Lokesh Vutla5af02db2018-08-27 15:57:32 +0530627 struct ti_sci_version_info version;
628};
629
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530630#define TI_SCI_RESOURCE_NULL 0xffff
631
632/**
633 * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
634 * @start: Start index of the resource.
635 * @num: Number of resources.
636 * @res_map: Bitmap to manage the allocation of these resources.
637 */
638struct ti_sci_resource_desc {
639 u16 start;
640 u16 num;
641 unsigned long *res_map;
642};
643
644/**
645 * struct ti_sci_resource - Structure representing a resource assigned
646 * to a device.
647 * @sets: Number of sets available from this resource type
648 * @desc: Array of resource descriptors.
649 */
650struct ti_sci_resource {
651 u16 sets;
652 struct ti_sci_resource_desc *desc;
653};
654
Lokesh Vutla5af02db2018-08-27 15:57:32 +0530655#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
656
657const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev);
658const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev);
659const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
660 const char *property);
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530661u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
662void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
663struct ti_sci_resource *
664devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
665 struct udevice *dev, u32 dev_id, char *of_prop);
Lokesh Vutla5af02db2018-08-27 15:57:32 +0530666
667#else /* CONFIG_TI_SCI_PROTOCOL */
668
669static inline
670const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev)
671{
672 return ERR_PTR(-EINVAL);
673}
674
675static inline const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev)
676{
677 return ERR_PTR(-EINVAL);
678}
679
680static inline
681const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
682 const char *property)
683{
684 return ERR_PTR(-EINVAL);
685}
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530686
687static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
688{
689 return TI_SCI_RESOURCE_NULL;
690}
691
692static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
693{
694}
695
696static inline struct ti_sci_resource *
697devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
698 struct udevice *dev, u32 dev_id, char *of_prop)
699{
700 return ERR_PTR(-EINVAL);
701}
Lokesh Vutla5af02db2018-08-27 15:57:32 +0530702#endif /* CONFIG_TI_SCI_PROTOCOL */
703
704#endif /* __TISCI_PROTOCOL_H */