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git01.mediatek.com / filogic / uboot / 5e017409383c3677e376fa7a359d2c71c0db31b8 / . / dts / upstream / Bindings / pinctrl / st,stm32-pinctrl.yaml
blob: e1eb45a9eda44f45d3bc6885e3210fab46865db6 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2019.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 GPIO and Pin Mux/Config controller
9
10maintainers:
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
12
13description: |
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15 controller. It controls the input/output settings on the available pins and
16 also provides ability to multiplex and configure the output of various
17 on-chip controllers onto these pads.
18
19properties:
20 compatible:
21 enum:
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp135-pinctrl
28 - st,stm32mp157-pinctrl
29 - st,stm32mp157-z-pinctrl
30 - st,stm32mp257-pinctrl
31 - st,stm32mp257-z-pinctrl
32
33 '#address-cells':
34 const: 1
35 '#size-cells':
36 const: 1
37
38 ranges: true
39 pins-are-numbered:
40 $ref: /schemas/types.yaml#/definitions/flag
41 deprecated: true
42 hwlocks: true
43
44 interrupts:
45 maxItems: 1
46
47 st,syscfg:
48 description: Phandle+args to the syscon node which includes IRQ mux selection.
49 $ref: /schemas/types.yaml#/definitions/phandle-array
50 items:
51 - minItems: 2
52 items:
53 - description: syscon node which includes IRQ mux selection
54 - description: The offset of the IRQ mux selection register
55 - description: The field mask of IRQ mux, needed if different of 0xf
56
57 st,package:
58 description:
59 Indicates the SOC package used.
60 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
61 $ref: /schemas/types.yaml#/definitions/uint32
62 enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
63
64patternProperties:
65 '^gpio@[0-9a-f]*$':
66 type: object
67 additionalProperties: false
68 properties:
69 gpio-controller: true
70 '#gpio-cells':
71 const: 2
72 interrupt-controller: true
73 '#interrupt-cells':
74 const: 2
75
76 reg:
77 maxItems: 1
78 clocks:
79 maxItems: 1
80 resets:
81 maxItems: 1
82 gpio-line-names: true
83 gpio-ranges:
84 minItems: 1
85 maxItems: 16
86 ngpios:
87 description:
88 Number of available gpios in a bank.
89 minimum: 1
90 maximum: 16
91
92 st,bank-name:
93 description:
94 Should be a name string for this bank as specified in the datasheet.
95 $ref: /schemas/types.yaml#/definitions/string
96 enum:
97 - GPIOA
98 - GPIOB
99 - GPIOC
100 - GPIOD
101 - GPIOE
102 - GPIOF
103 - GPIOG
104 - GPIOH
105 - GPIOI
106 - GPIOJ
107 - GPIOK
108 - GPIOZ
109
110 st,bank-ioport:
111 description:
112 Should correspond to the EXTI IOport selection (EXTI line used
113 to select GPIOs as interrupts).
114 $ref: /schemas/types.yaml#/definitions/uint32
115 minimum: 0
116 maximum: 11
117
118 patternProperties:
119 "^(.+-hog(-[0-9]+)?)$":
120 type: object
121 required:
122 - gpio-hog
123
124 required:
125 - gpio-controller
126 - '#gpio-cells'
127 - reg
128 - clocks
129 - st,bank-name
130
131 '-[0-9]*$':
132 type: object
133 additionalProperties: false
134
135 patternProperties:
136 '^pins':
137 type: object
138 additionalProperties: false
139 description: |
140 A pinctrl node should contain at least one subnode representing the
141 pinctrl group available on the machine. Each subnode will list the
142 pins it needs, and how they should be configured, with regard to muxer
143 configuration, pullups, drive, output high/low and output speed.
144 properties:
145 pinmux:
146 $ref: /schemas/types.yaml#/definitions/uint32-array
147 description: |
148 Integer array, represents gpio pin number and mux setting.
149 Supported pin number and mux varies for different SoCs, and are
150 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
151 These defines are calculated as: ((port * 16 + line) << 8) | function
152 With:
153 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
154 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
155 - function: The function number, can be:
156 * 0 : GPIO
157 * 1 : Alternate Function 0
158 * 2 : Alternate Function 1
159 * 3 : Alternate Function 2
160 * ...
161 * 16 : Alternate Function 15
162 * 17 : Analog
163 To simplify the usage, macro is available to generate "pinmux" field.
164 This macro is available here:
165 - include/dt-bindings/pinctrl/stm32-pinfunc.h
166 Some examples of using macro:
167 /* GPIO A9 set as alernate function 2 */
168 ... {
169 pinmux = <STM32_PINMUX('A', 9, AF2)>;
170 };
171 /* GPIO A9 set as GPIO */
172 ... {
173 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
174 };
175 /* GPIO A9 set as analog */
176 ... {
177 pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
178 };
179
180 bias-disable:
181 type: boolean
182 bias-pull-down:
183 type: boolean
184 bias-pull-up:
185 type: boolean
186 drive-push-pull:
187 type: boolean
188 drive-open-drain:
189 type: boolean
190 output-low:
191 type: boolean
192 output-high:
193 type: boolean
194 slew-rate:
195 description: |
196 0: Low speed
197 1: Medium speed
198 2: Fast speed
199 3: High speed
200 $ref: /schemas/types.yaml#/definitions/uint32
201 enum: [0, 1, 2, 3]
202
203 required:
204 - pinmux
205
206allOf:
207 - $ref: pinctrl.yaml#
208
209required:
210 - compatible
211 - '#address-cells'
212 - '#size-cells'
213 - ranges
214
215additionalProperties: false
216
217examples:
218 - |
219 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
220 #include <dt-bindings/mfd/stm32f4-rcc.h>
221 //Example 1
222 pinctrl@40020000 {
223 #address-cells = <1>;
224 #size-cells = <1>;
225 compatible = "st,stm32f429-pinctrl";
226 ranges = <0 0x40020000 0x3000>;
227
228 gpioa: gpio@0 {
229 gpio-controller;
230 #gpio-cells = <2>;
231 reg = <0x0 0x400>;
232 resets = <&reset_ahb1 0>;
233 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
234 st,bank-name = "GPIOA";
235 };
236 };
237
238 //Example 2 (using gpio-ranges)
239 pinctrl@50020000 {
240 #address-cells = <1>;
241 #size-cells = <1>;
242 compatible = "st,stm32f429-pinctrl";
243 ranges = <0 0x50020000 0x3000>;
244
245 gpiob: gpio@1000 {
246 gpio-controller;
247 #gpio-cells = <2>;
248 reg = <0x1000 0x400>;
249 resets = <&reset_ahb1 0>;
250 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
251 st,bank-name = "GPIOB";
252 gpio-ranges = <&pinctrl 0 0 16>;
253 };
254
255 gpioc: gpio@2000 {
256 gpio-controller;
257 #gpio-cells = <2>;
258 reg = <0x2000 0x400>;
259 resets = <&reset_ahb1 0>;
260 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
261 st,bank-name = "GPIOC";
262 ngpios = <5>;
263 gpio-ranges = <&pinctrl 0 16 3>,
264 <&pinctrl 14 30 2>;
265 };
266 };
267
268 //Example 3 pin groups
269 pinctrl {
270 usart1_pins_a: usart1-0 {
271 pins1 {
272 pinmux = <STM32_PINMUX('A', 9, AF7)>;
273 bias-disable;
274 drive-push-pull;
275 slew-rate = <0>;
276 };
277 pins2 {
278 pinmux = <STM32_PINMUX('A', 10, AF7)>;
279 bias-disable;
280 };
281 };
282 };
283
284 usart1 {
285 pinctrl-0 = <&usart1_pins_a>;
286 pinctrl-names = "default";
287 };
288
289...