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git01.mediatek.com / filogic / uboot / 5e017409383c3677e376fa7a359d2c71c0db31b8 / . / dts / upstream / Bindings / interconnect / mediatek,cci.yaml
blob: 58611ba2a0f440b25aa8aa37c36ca339eecbbc85 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
8
9maintainers:
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
12
13description: |
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
15 MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
16 hardware. It can also optimize the voltage to reduce the power consumption.
17
18properties:
19 compatible:
20 enum:
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
23
24 clocks:
25 items:
26 - description:
27 The multiplexer for clock input of the bus.
28 - description:
29 A parent of "bus" clock which is used as an intermediate clock source
30 when the original clock source (PLL) is under transition and not
31 stable yet.
32
33 clock-names:
34 items:
35 - const: cci
36 - const: intermediate
37
38 operating-points-v2: true
39 opp-table:
40 type: object
41
42 proc-supply:
43 description:
44 Phandle of the regulator for CCI that provides the supply voltage.
45
46 sram-supply:
47 description:
48 Phandle of the regulator for sram of CCI that provides the supply
49 voltage. When it is present, the implementation needs to do
50 "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
51 SoC specific needs. When absent, the voltage scaling flow is handled by
52 hardware, hence no software "voltage tracking" is needed.
53
54required:
55 - compatible
56 - clocks
57 - clock-names
58 - operating-points-v2
59 - proc-supply
60
61additionalProperties: false
62
63examples:
64 - |
65 #include <dt-bindings/clock/mt8183-clk.h>
66 cci: cci {
67 compatible = "mediatek,mt8183-cci";
68 clocks = <&mcucfg CLK_MCU_BUS_SEL>,
69 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
70 clock-names = "cci", "intermediate";
71 operating-points-v2 = <&cci_opp>;
72 proc-supply = <&mt6358_vproc12_reg>;
73 };
74
75 cci_opp: opp-table-cci {
76 compatible = "operating-points-v2";
77 opp-shared;
78 opp2_00: opp-273000000 {
79 opp-hz = /bits/ 64 <273000000>;
80 opp-microvolt = <650000>;
81 };
82 opp2_01: opp-338000000 {
83 opp-hz = /bits/ 64 <338000000>;
84 opp-microvolt = <687500>;
85 };
86 opp2_02: opp-403000000 {
87 opp-hz = /bits/ 64 <403000000>;
88 opp-microvolt = <718750>;
89 };
90 opp2_03: opp-463000000 {
91 opp-hz = /bits/ 64 <463000000>;
92 opp-microvolt = <756250>;
93 };
94 opp2_04: opp-546000000 {
95 opp-hz = /bits/ 64 <546000000>;
96 opp-microvolt = <800000>;
97 };
98 opp2_05: opp-624000000 {
99 opp-hz = /bits/ 64 <624000000>;
100 opp-microvolt = <818750>;
101 };
102 opp2_06: opp-689000000 {
103 opp-hz = /bits/ 64 <689000000>;
104 opp-microvolt = <850000>;
105 };
106 opp2_07: opp-767000000 {
107 opp-hz = /bits/ 64 <767000000>;
108 opp-microvolt = <868750>;
109 };
110 opp2_08: opp-845000000 {
111 opp-hz = /bits/ 64 <845000000>;
112 opp-microvolt = <893750>;
113 };
114 opp2_09: opp-871000000 {
115 opp-hz = /bits/ 64 <871000000>;
116 opp-microvolt = <906250>;
117 };
118 opp2_10: opp-923000000 {
119 opp-hz = /bits/ 64 <923000000>;
120 opp-microvolt = <931250>;
121 };
122 opp2_11: opp-962000000 {
123 opp-hz = /bits/ 64 <962000000>;
124 opp-microvolt = <943750>;
125 };
126 opp2_12: opp-1027000000 {
127 opp-hz = /bits/ 64 <1027000000>;
128 opp-microvolt = <975000>;
129 };
130 opp2_13: opp-1092000000 {
131 opp-hz = /bits/ 64 <1092000000>;
132 opp-microvolt = <1000000>;
133 };
134 opp2_14: opp-1144000000 {
135 opp-hz = /bits/ 64 <1144000000>;
136 opp-microvolt = <1025000>;
137 };
138 opp2_15: opp-1196000000 {
139 opp-hz = /bits/ 64 <1196000000>;
140 opp-microvolt = <1050000>;
141 };
142 };