| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Tom Warren | b7ea6d1 | 2014-01-24 12:46:13 -0700 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 |
| 4 | * NVIDIA Corporation <www.nvidia.com> |
| Tom Warren | b7ea6d1 | 2014-01-24 12:46:13 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _TEGRA124_H_ |
| 8 | #define _TEGRA124_H_ |
| 9 | |
| Tom Warren | b7ea6d1 | 2014-01-24 12:46:13 -0700 | [diff] [blame] | 10 | #define NV_PA_SDRAM_BASE 0x80000000 |
| 11 | #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ |
| 12 | #define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ |
| 13 | #define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ |
| 14 | |
| 15 | #include <asm/arch-tegra/tegra.h> |
| 16 | |
| 17 | #define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ |
| 18 | |
| 19 | #undef NVBOOTINFOTABLE_BCTSIZE |
| 20 | #undef NVBOOTINFOTABLE_BCTPTR |
| 21 | #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ |
| 22 | #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ |
| 23 | |
| 24 | #define MAX_NUM_CPU 4 |
| 25 | #define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) |
| 26 | |
| 27 | #define TEGRA_USB1_BASE 0x7D000000 |
| 28 | |
| 29 | #endif /* _TEGRA124_H_ */ |