blob: c76372ee826a9b29cd017d3053ec11a15a76bf95 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kever Yang50fb9982017-02-22 16:56:35 +08002/*
3 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
Kever Yang50fb9982017-02-22 16:56:35 +08004 */
5
6#ifndef _ASM_ARCH_SDRAM_RK3399_H
7#define _ASM_ARCH_SDRAM_RK3399_H
Kever Yang38a99b62019-11-15 11:04:34 +08008#include <asm/arch-rockchip/sdram_common.h>
YouMin Chen23ae72e2019-11-15 11:04:45 +08009#include <asm/arch-rockchip/sdram_msch.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060010#ifndef __ASSEMBLY__
11#include <linux/bitops.h>
12#endif
Kever Yang50fb9982017-02-22 16:56:35 +080013
Kever Yang50fb9982017-02-22 16:56:35 +080014struct rk3399_ddr_pctl_regs {
15 u32 denali_ctl[332];
16};
17
18struct rk3399_ddr_publ_regs {
19 u32 denali_phy[959];
20};
21
22struct rk3399_ddr_pi_regs {
23 u32 denali_pi[200];
24};
25
Kever Yang50fb9982017-02-22 16:56:35 +080026struct rk3399_ddr_cic_regs {
27 u32 cic_ctrl0;
28 u32 cic_ctrl1;
29 u32 cic_idle_th;
30 u32 cic_cg_wait_th;
31 u32 cic_status0;
32 u32 cic_status1;
33 u32 cic_ctrl2;
34 u32 cic_ctrl3;
35 u32 cic_ctrl4;
36};
37
38/* DENALI_CTL_00 */
39#define START 1
40
41/* DENALI_CTL_68 */
YouMin Chen23ae72e2019-11-15 11:04:45 +080042#define PWRUP_SREFRESH_EXIT BIT(16)
Kever Yang50fb9982017-02-22 16:56:35 +080043
44/* DENALI_CTL_274 */
45#define MEM_RST_VALID 1
46
YouMin Chen23ae72e2019-11-15 11:04:45 +080047struct msch_regs {
48 u32 coreid;
49 u32 revisionid;
50 u32 ddrconf;
51 u32 ddrsize;
52 union noc_ddrtiminga0 ddrtiminga0;
53 union noc_ddrtimingb0 ddrtimingb0;
54 union noc_ddrtimingc0 ddrtimingc0;
55 union noc_devtodev0 devtodev0;
56 u32 reserved0[(0x110 - 0x20) / 4];
57 union noc_ddrmode ddrmode;
58 u32 reserved1[(0x1000 - 0x114) / 4];
59 u32 agingx0;
60};
61
62struct sdram_msch_timings {
63 union noc_ddrtiminga0 ddrtiminga0;
64 union noc_ddrtimingb0 ddrtimingb0;
65 union noc_ddrtimingc0 ddrtimingc0;
66 union noc_devtodev0 devtodev0;
67 union noc_ddrmode ddrmode;
68 u32 agingx0;
69};
70
Jagan Teki97867c82019-07-15 23:51:05 +053071struct rk3399_sdram_channel {
72 struct sdram_cap_info cap_info;
YouMin Chen23ae72e2019-11-15 11:04:45 +080073 struct sdram_msch_timings noc_timings;
Kever Yang50fb9982017-02-22 16:56:35 +080074};
75
Kever Yang50fb9982017-02-22 16:56:35 +080076struct rk3399_sdram_params {
77 struct rk3399_sdram_channel ch[2];
Jagan Tekid2f92d02019-07-15 23:51:06 +053078 struct sdram_base_params base;
Kever Yang50fb9982017-02-22 16:56:35 +080079 struct rk3399_ddr_pctl_regs pctl_regs;
80 struct rk3399_ddr_pi_regs pi_regs;
81 struct rk3399_ddr_publ_regs phy_regs;
82};
83
YouMin Chen23ae72e2019-11-15 11:04:45 +080084#define PI_CA_TRAINING BIT(0)
85#define PI_WRITE_LEVELING BIT(1)
86#define PI_READ_GATE_TRAINING BIT(2)
87#define PI_READ_LEVELING BIT(3)
88#define PI_WDQ_LEVELING BIT(4)
Kever Yang50fb9982017-02-22 16:56:35 +080089#define PI_FULL_TRAINING 0xff
90
Kever Yange2b64fd2019-11-15 11:04:52 +080091enum {
92 STRIDE_128B = 0,
93 STRIDE_256B = 1,
94 STRIDE_512B = 2,
95 STRIDE_4KB = 3,
96 UN_STRIDE = 4,
97 PART_STRIDE = 5,
98};
99
Kever Yang50fb9982017-02-22 16:56:35 +0800100#endif