blob: 988cc445438ea2244a04935f3bf61ce6d7e91d87 [file] [log] [blame]
Paweł Anikiel347cb5e2022-06-17 12:47:18 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2022 Google LLC
4 */
5/dts-v1/;
6#include "socfpga_arria10_mercury_aa1.dtsi"
7
8/ {
9 model = "Google Chameleon V3";
10 compatible = "google,chameleon-v3",
11 "altr,socfpga-arria10", "altr,socfpga";
12
13 aliases {
14 serial0 = &uart0;
15 i2c0 = &i2c0;
16 i2c1 = &i2c1;
17 };
18};
19
20&gmac0 {
21 status = "okay";
22};
23
24&gpio0 {
25 status = "okay";
26};
27
28&gpio1 {
29 status = "okay";
30};
31
32&gpio2 {
33 status = "okay";
34};
35
36&i2c0 {
37 status = "okay";
38
39 ssm2603: ssm2603@1a {
40 compatible = "adi,ssm2603";
41 reg = <0x1a>;
42 };
43};
44
45&i2c1 {
46 status = "okay";
47
48 u80: u80@21 {
49 compatible = "nxp,pca9535";
50 reg = <0x21>;
51 gpio-controller;
52 #gpio-cells = <2>;
53
54 gpio-line-names =
55 "SOM_AUD_MUTE",
56 "DP1_OUT_CEC_EN",
57 "DP2_OUT_CEC_EN",
58 "DP1_SOM_PS8469_CAD",
59 "DPD_SOM_PS8469_CAD",
60 "DP_OUT_PWR_EN",
61 "STM32_RST_L",
62 "STM32_BOOT0",
63
64 "FPGA_PROT",
65 "STM32_FPGA_COMM0",
66 "TP119",
67 "TP120",
68 "TP121",
69 "TP122",
70 "TP123",
71 "TP124";
72 };
73};
74
75&mmc {
76 status = "okay";
77};
78
79&uart0 {
80 status = "okay";
81};
82
83&uart1 {
84 status = "okay";
85};
86
87&usb0 {
88 status = "okay";
89 dr_mode = "host";
90};