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Priyanka Jainfd45ca02018-11-28 13:04:27 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2018-2021 NXP
Priyanka Jainfd45ca02018-11-28 13:04:27 +00004 */
5
6#ifndef __LX2_COMMON_H
7#define __LX2_COMMON_H
8
9#include <asm/arch/stream_id_lsch3.h>
10#include <asm/arch/config.h>
11#include <asm/arch/soc.h>
12
Tom Rini6a5dccc2022-11-16 13:10:41 -050013#define CFG_SYS_FLASH_BASE 0x20000000
Priyanka Jainfd45ca02018-11-28 13:04:27 +000014
Priyanka Jainfd45ca02018-11-28 13:04:27 +000015/* DDR */
Tom Rini6a5dccc2022-11-16 13:10:41 -050016#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
Tom Rini376b88a2022-10-28 20:27:13 -040017#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
Tom Rini6a5dccc2022-11-16 13:10:41 -050018#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
Tom Rinibb4dd962022-11-16 13:10:37 -050019#define CFG_SYS_SDRAM_SIZE 0x200000000UL
Tom Rini6a5dccc2022-11-16 13:10:41 -050020#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
Priyanka Jainfd45ca02018-11-28 13:04:27 +000021#define SPD_EEPROM_ADDRESS1 0x51
22#define SPD_EEPROM_ADDRESS2 0x52
23#define SPD_EEPROM_ADDRESS3 0x53
24#define SPD_EEPROM_ADDRESS4 0x54
25#define SPD_EEPROM_ADDRESS5 0x55
26#define SPD_EEPROM_ADDRESS6 0x56
27#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
Priyanka Jainfd45ca02018-11-28 13:04:27 +000028
29/* Miscellaneous configurable options */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000030
31/* SMP Definitinos */
Michael Wallef056e0f2020-06-01 21:53:26 +020032#define CPU_RELEASE_ADDR secondary_boot_addr
Priyanka Jainfd45ca02018-11-28 13:04:27 +000033
34/* Generic Timer Definitions */
35/*
36 * This is not an accurate number. It is used in start.S. The frequency
37 * will be udpated later when get_bus_freq(0) is available.
38 */
39
Priyanka Jainfd45ca02018-11-28 13:04:27 +000040
Priyanka Jainfd45ca02018-11-28 13:04:27 +000041/* Serial Port */
Tom Rini5c896ae2022-12-04 10:13:30 -050042#define CFG_PL011_CLOCK (get_bus_freq(0) / 4)
Tom Rini6a5dccc2022-11-16 13:10:41 -050043#define CFG_SYS_SERIAL0 0x21c0000
44#define CFG_SYS_SERIAL1 0x21d0000
45#define CFG_SYS_SERIAL2 0x21e0000
46#define CFG_SYS_SERIAL3 0x21f0000
Priyanka Jainfd45ca02018-11-28 13:04:27 +000047/*below might needs to be removed*/
Tom Rini9fe2b312022-12-04 10:13:31 -050048#define CFG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
Tom Rini6a5dccc2022-11-16 13:10:41 -050049 (void *)CFG_SYS_SERIAL1, \
50 (void *)CFG_SYS_SERIAL2, \
51 (void *)CFG_SYS_SERIAL3 }
Priyanka Jainfd45ca02018-11-28 13:04:27 +000052
53/* MC firmware */
Tom Rini6a5dccc2022-11-16 13:10:41 -050054#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
55#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
56#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
57#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
58#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
Priyanka Jainfd45ca02018-11-28 13:04:27 +000059
Priyanka Jainfd45ca02018-11-28 13:04:27 +000060/*
61 * Carve out a DDR region which will not be used by u-boot/Linux
62 *
63 * It will be used by MC and Debug Server. The MC region must be
64 * 512MB aligned, so the min size to hide is 512MB.
65 */
66#ifdef CONFIG_FSL_MC_ENET
Tom Rini6a5dccc2022-11-16 13:10:41 -050067#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
Priyanka Jainfd45ca02018-11-28 13:04:27 +000068#endif
69
70/* I2C bus multiplexer */
71#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
72#define I2C_MUX_CH_DEFAULT 0x8
73
74/* RTC */
Tom Rini6a5dccc2022-11-16 13:10:41 -050075#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
Priyanka Jainfd45ca02018-11-28 13:04:27 +000076
Priyanka Jainfd45ca02018-11-28 13:04:27 +000077/* Qixis */
Tom Rini6a5dccc2022-11-16 13:10:41 -050078#define CFG_SYS_I2C_FPGA_ADDR 0x66
Priyanka Jainfd45ca02018-11-28 13:04:27 +000079
Priyanka Jainfd45ca02018-11-28 13:04:27 +000080/* USB */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000081
Tom Rini8c70baa2021-12-14 13:36:40 -050082#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
Priyanka Jainfd45ca02018-11-28 13:04:27 +000083
Priyanka Jainfd45ca02018-11-28 13:04:27 +000084#define HWCONFIG_BUFFER_SIZE 128
85
Priyanka Jainfd45ca02018-11-28 13:04:27 +000086/* Initial environment variables */
Kuldeep Singh3e78c332020-03-12 15:13:00 +053087#define XSPI_MC_INIT_CMD \
88 "sf probe 0:0 && " \
89 "sf read 0x80640000 0x640000 0x80000 && " \
Priyanka Jain5fde1642021-08-18 12:37:03 +053090 "sf read $fdt_addr_r 0xf00000 0x100000 && " \
Kuldeep Singh3e78c332020-03-12 15:13:00 +053091 "env exists secureboot && " \
92 "esbc_validate 0x80640000 && " \
93 "esbc_validate 0x80680000; " \
94 "sf read 0x80a00000 0xa00000 0x300000 && " \
95 "sf read 0x80e00000 0xe00000 0x100000; " \
96 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jainfd45ca02018-11-28 13:04:27 +000097
98#define SD_MC_INIT_CMD \
Pankaj Bansal1972a532019-07-17 10:33:54 +000099 "mmc read 0x80a00000 0x5000 0x1200;" \
100 "mmc read 0x80e00000 0x7000 0x800;" \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530101 "mmc read $fdt_addr_r 0x7800 0x800;" \
Udit Agarwalf34581e2018-12-14 04:43:32 +0000102 "env exists secureboot && " \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000103 "mmc read 0x80640000 0x3200 0x20 && " \
104 "mmc read 0x80680000 0x3400 0x20 && " \
105 "esbc_validate 0x80640000 && " \
106 "esbc_validate 0x80680000 ;" \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000107 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000108
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530109#define SD2_MC_INIT_CMD \
110 "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
111 "mmc read 0x80e00000 0x7000 0x800;" \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530112 "mmc read $fdt_addr_r 0x7800 0x800;" \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530113 "env exists secureboot && " \
114 "mmc read 0x80640000 0x3200 0x20 && " \
115 "mmc read 0x80680000 0x3400 0x20 && " \
116 "esbc_validate 0x80640000 && " \
117 "esbc_validate 0x80680000 ;" \
118 "fsl_mc start mc 0x80a00000 0x80e00000\0"
119
Priyanka Jain16744062019-01-24 05:22:18 +0000120#define EXTRA_ENV_SETTINGS \
121 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
122 "ramdisk_addr=0x800000\0" \
123 "ramdisk_size=0x2000000\0" \
124 "fdt_high=0xa0000000\0" \
125 "initrd_high=0xffffffffffffffff\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000126 "kernel_start=0x1000000\0" \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000127 "kernelheader_start=0x600000\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000128 "scriptaddr=0x80000000\0" \
129 "scripthdraddr=0x80080000\0" \
130 "fdtheader_addr_r=0x80100000\0" \
131 "kernelheader_addr_r=0x80200000\0" \
132 "kernel_addr_r=0x81000000\0" \
133 "kernelheader_size=0x40000\0" \
134 "fdt_addr_r=0x90000000\0" \
135 "load_addr=0xa0000000\0" \
136 "kernel_size=0x2800000\0" \
137 "kernel_addr_sd=0x8000\0" \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000138 "kernelhdr_addr_sd=0x3000\0" \
Manish Tomarebef67f2020-11-05 14:08:56 +0530139 "kernel_size_sd=0x14000\0" \
Udit Agarwal11e1a572019-11-20 08:49:06 +0000140 "kernelhdr_size_sd=0x20\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000141 "console=ttyAMA0,38400n8\0" \
142 BOOTENV \
143 "mcmemsize=0x70000000\0" \
144 XSPI_MC_INIT_CMD \
Priyanka Jain16744062019-01-24 05:22:18 +0000145 "scan_dev_for_boot_part=" \
146 "part list ${devtype} ${devnum} devplist; " \
147 "env exists devplist || setenv devplist 1; " \
148 "for distro_bootpart in ${devplist}; do " \
149 "if fstype ${devtype} " \
150 "${devnum}:${distro_bootpart} " \
151 "bootfstype; then " \
152 "run scan_dev_for_boot; " \
153 "fi; " \
154 "done\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000155 "boot_a_script=" \
156 "load ${devtype} ${devnum}:${distro_bootpart} " \
157 "${scriptaddr} ${prefix}${script}; " \
158 "env exists secureboot && load ${devtype} " \
159 "${devnum}:${distro_bootpart} " \
160 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
161 "&& esbc_validate ${scripthdraddr};" \
162 "source ${scriptaddr}\0"
163
164#define XSPI_NOR_BOOTCOMMAND \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530165 "sf probe 0:0; " \
166 "sf read 0x806c0000 0x6c0000 0x40000; " \
167 "env exists mcinitcmd && env exists secureboot" \
168 " && esbc_validate 0x806c0000; " \
169 "sf read 0x80d00000 0xd00000 0x100000; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000170 "env exists mcinitcmd && " \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530171 "fsl_mc lazyapply dpl 0x80d00000; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000172 "run distro_bootcmd;run xspi_bootcmd; " \
173 "env exists secureboot && esbc_halt;"
174
175#define SD_BOOTCOMMAND \
176 "env exists mcinitcmd && mmcinfo; " \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000177 "mmc read 0x80d00000 0x6800 0x800; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000178 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000179 " && mmc read 0x806C0000 0x3600 0x20 " \
180 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000181 "&& fsl_mc lazyapply dpl 0x80d00000;" \
Priyanka Jain16744062019-01-24 05:22:18 +0000182 "run distro_bootcmd;run sd_bootcmd;" \
183 "env exists secureboot && esbc_halt;"
184
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530185#define SD2_BOOTCOMMAND \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530186 "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530187 "mmc read 0x80d00000 0x6800 0x800; " \
188 "env exists mcinitcmd && env exists secureboot " \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530189 " && mmc read 0x806C0000 0x3600 0x20 " \
190 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530191 "&& fsl_mc lazyapply dpl 0x80d00000;" \
192 "run distro_bootcmd;run sd2_bootcmd;" \
193 "env exists secureboot && esbc_halt;"
194
Daniel Klauerd7daa552022-02-09 15:53:41 +0100195#ifdef CONFIG_CMD_USB
196#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
197#else
198#define BOOT_TARGET_DEVICES_USB(func)
199#endif
200
201#ifdef CONFIG_MMC
202#define BOOT_TARGET_DEVICES_MMC(func, instance) func(MMC, mmc, instance)
203#else
204#define BOOT_TARGET_DEVICES_MMC(func)
205#endif
206
207#ifdef CONFIG_SCSI
208#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
209#else
210#define BOOT_TARGET_DEVICES_SCSI(func)
211#endif
212
213#ifdef CONFIG_CMD_DHCP
214#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
215#else
216#define BOOT_TARGET_DEVICES_DHCP(func)
217#endif
218
Priyanka Jain16744062019-01-24 05:22:18 +0000219#define BOOT_TARGET_DEVICES(func) \
Daniel Klauerd7daa552022-02-09 15:53:41 +0100220 BOOT_TARGET_DEVICES_USB(func) \
221 BOOT_TARGET_DEVICES_MMC(func, 0) \
222 BOOT_TARGET_DEVICES_MMC(func, 1) \
223 BOOT_TARGET_DEVICES_SCSI(func) \
224 BOOT_TARGET_DEVICES_DHCP(func)
Priyanka Jain16744062019-01-24 05:22:18 +0000225#include <config_distro_bootcmd.h>
226
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000227#endif /* __LX2_COMMON_H */