developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * MediaTek SD/MMC Card Interface driver |
| 4 | * |
| 5 | * Copyright (C) 2018 MediaTek Inc. |
| 6 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 7 | */ |
| 8 | |
| 9 | #include <clk.h> |
| 10 | #include <common.h> |
| 11 | #include <dm.h> |
| 12 | #include <mmc.h> |
| 13 | #include <errno.h> |
| 14 | #include <malloc.h> |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 15 | #include <mapmem.h> |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 16 | #include <stdbool.h> |
| 17 | #include <asm/gpio.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 18 | #include <dm/device_compat.h> |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 19 | #include <dm/pinctrl.h> |
| 20 | #include <linux/bitops.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/iopoll.h> |
| 23 | |
| 24 | /* MSDC_CFG */ |
| 25 | #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22) |
| 26 | #define MSDC_CFG_CKMOD_EXT_M 0x300000 |
| 27 | #define MSDC_CFG_CKMOD_EXT_S 20 |
| 28 | #define MSDC_CFG_CKDIV_EXT_M 0xfff00 |
| 29 | #define MSDC_CFG_CKDIV_EXT_S 8 |
| 30 | #define MSDC_CFG_HS400_CK_MODE BIT(18) |
| 31 | #define MSDC_CFG_CKMOD_M 0x30000 |
| 32 | #define MSDC_CFG_CKMOD_S 16 |
| 33 | #define MSDC_CFG_CKDIV_M 0xff00 |
| 34 | #define MSDC_CFG_CKDIV_S 8 |
| 35 | #define MSDC_CFG_CKSTB BIT(7) |
| 36 | #define MSDC_CFG_PIO BIT(3) |
| 37 | #define MSDC_CFG_RST BIT(2) |
| 38 | #define MSDC_CFG_CKPDN BIT(1) |
| 39 | #define MSDC_CFG_MODE BIT(0) |
| 40 | |
| 41 | /* MSDC_IOCON */ |
| 42 | #define MSDC_IOCON_W_DSPL BIT(8) |
| 43 | #define MSDC_IOCON_DSPL BIT(2) |
| 44 | #define MSDC_IOCON_RSPL BIT(1) |
| 45 | |
| 46 | /* MSDC_PS */ |
| 47 | #define MSDC_PS_DAT0 BIT(16) |
| 48 | #define MSDC_PS_CDDBCE_M 0xf000 |
| 49 | #define MSDC_PS_CDDBCE_S 12 |
| 50 | #define MSDC_PS_CDSTS BIT(1) |
| 51 | #define MSDC_PS_CDEN BIT(0) |
| 52 | |
| 53 | /* #define MSDC_INT(EN) */ |
| 54 | #define MSDC_INT_ACMDRDY BIT(3) |
| 55 | #define MSDC_INT_ACMDTMO BIT(4) |
| 56 | #define MSDC_INT_ACMDCRCERR BIT(5) |
| 57 | #define MSDC_INT_CMDRDY BIT(8) |
| 58 | #define MSDC_INT_CMDTMO BIT(9) |
| 59 | #define MSDC_INT_RSPCRCERR BIT(10) |
| 60 | #define MSDC_INT_XFER_COMPL BIT(12) |
| 61 | #define MSDC_INT_DATTMO BIT(14) |
| 62 | #define MSDC_INT_DATCRCERR BIT(15) |
| 63 | |
| 64 | /* MSDC_FIFOCS */ |
| 65 | #define MSDC_FIFOCS_CLR BIT(31) |
| 66 | #define MSDC_FIFOCS_TXCNT_M 0xff0000 |
| 67 | #define MSDC_FIFOCS_TXCNT_S 16 |
| 68 | #define MSDC_FIFOCS_RXCNT_M 0xff |
| 69 | #define MSDC_FIFOCS_RXCNT_S 0 |
| 70 | |
| 71 | /* #define SDC_CFG */ |
| 72 | #define SDC_CFG_DTOC_M 0xff000000 |
| 73 | #define SDC_CFG_DTOC_S 24 |
| 74 | #define SDC_CFG_SDIOIDE BIT(20) |
| 75 | #define SDC_CFG_SDIO BIT(19) |
| 76 | #define SDC_CFG_BUSWIDTH_M 0x30000 |
| 77 | #define SDC_CFG_BUSWIDTH_S 16 |
| 78 | |
| 79 | /* SDC_CMD */ |
| 80 | #define SDC_CMD_BLK_LEN_M 0xfff0000 |
| 81 | #define SDC_CMD_BLK_LEN_S 16 |
| 82 | #define SDC_CMD_STOP BIT(14) |
| 83 | #define SDC_CMD_WR BIT(13) |
| 84 | #define SDC_CMD_DTYPE_M 0x1800 |
| 85 | #define SDC_CMD_DTYPE_S 11 |
| 86 | #define SDC_CMD_RSPTYP_M 0x380 |
| 87 | #define SDC_CMD_RSPTYP_S 7 |
| 88 | #define SDC_CMD_CMD_M 0x3f |
| 89 | #define SDC_CMD_CMD_S 0 |
| 90 | |
| 91 | /* SDC_STS */ |
| 92 | #define SDC_STS_CMDBUSY BIT(1) |
| 93 | #define SDC_STS_SDCBUSY BIT(0) |
| 94 | |
| 95 | /* SDC_ADV_CFG0 */ |
| 96 | #define SDC_RX_ENHANCE_EN BIT(20) |
| 97 | |
| 98 | /* PATCH_BIT0 */ |
| 99 | #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380 |
| 100 | #define MSDC_INT_DAT_LATCH_CK_SEL_S 7 |
| 101 | |
| 102 | /* PATCH_BIT1 */ |
| 103 | #define MSDC_PB1_STOP_DLY_M 0xf00 |
| 104 | #define MSDC_PB1_STOP_DLY_S 8 |
| 105 | |
| 106 | /* PATCH_BIT2 */ |
| 107 | #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000 |
| 108 | #define MSDC_PB2_CRCSTSENSEL_S 29 |
| 109 | #define MSDC_PB2_CFGCRCSTS BIT(28) |
| 110 | #define MSDC_PB2_RESPSTSENSEL_M 0x70000 |
| 111 | #define MSDC_PB2_RESPSTSENSEL_S 16 |
| 112 | #define MSDC_PB2_CFGRESP BIT(15) |
| 113 | #define MSDC_PB2_RESPWAIT_M 0x0c |
| 114 | #define MSDC_PB2_RESPWAIT_S 2 |
| 115 | |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 116 | /* MSDC_PAD_CTRL0 */ |
| 117 | #define MSDC_PAD_CTRL0_CLKRDSEL_M 0xff000000 |
| 118 | #define MSDC_PAD_CTRL0_CLKRDSEL_S 24 |
| 119 | #define MSDC_PAD_CTRL0_CLKTDSEL BIT(20) |
| 120 | #define MSDC_PAD_CTRL0_CLKIES BIT(19) |
| 121 | #define MSDC_PAD_CTRL0_CLKSMT BIT(18) |
| 122 | #define MSDC_PAD_CTRL0_CLKPU BIT(17) |
| 123 | #define MSDC_PAD_CTRL0_CLKPD BIT(16) |
| 124 | #define MSDC_PAD_CTRL0_CLKSR BIT(8) |
| 125 | #define MSDC_PAD_CTRL0_CLKDRVP_M 0x70 |
| 126 | #define MSDC_PAD_CTRL0_CLKDRVP_S 4 |
| 127 | #define MSDC_PAD_CTRL0_CLKDRVN_M 0x7 |
| 128 | #define MSDC_PAD_CTRL0_CLKDRVN_S 0 |
| 129 | |
| 130 | /* MSDC_PAD_CTRL1 */ |
| 131 | #define MSDC_PAD_CTRL1_CMDRDSEL_M 0xff000000 |
| 132 | #define MSDC_PAD_CTRL1_CMDRDSEL_S 24 |
| 133 | #define MSDC_PAD_CTRL1_CMDTDSEL BIT(20) |
| 134 | #define MSDC_PAD_CTRL1_CMDIES BIT(19) |
| 135 | #define MSDC_PAD_CTRL1_CMDSMT BIT(18) |
| 136 | #define MSDC_PAD_CTRL1_CMDPU BIT(17) |
| 137 | #define MSDC_PAD_CTRL1_CMDPD BIT(16) |
| 138 | #define MSDC_PAD_CTRL1_CMDSR BIT(8) |
| 139 | #define MSDC_PAD_CTRL1_CMDDRVP_M 0x70 |
| 140 | #define MSDC_PAD_CTRL1_CMDDRVP_S 4 |
| 141 | #define MSDC_PAD_CTRL1_CMDDRVN_M 0x7 |
| 142 | #define MSDC_PAD_CTRL1_CMDDRVN_S 0 |
| 143 | |
| 144 | /* MSDC_PAD_CTRL2 */ |
| 145 | #define MSDC_PAD_CTRL2_DATRDSEL_M 0xff000000 |
| 146 | #define MSDC_PAD_CTRL2_DATRDSEL_S 24 |
| 147 | #define MSDC_PAD_CTRL2_DATTDSEL BIT(20) |
| 148 | #define MSDC_PAD_CTRL2_DATIES BIT(19) |
| 149 | #define MSDC_PAD_CTRL2_DATSMT BIT(18) |
| 150 | #define MSDC_PAD_CTRL2_DATPU BIT(17) |
| 151 | #define MSDC_PAD_CTRL2_DATPD BIT(16) |
| 152 | #define MSDC_PAD_CTRL2_DATSR BIT(8) |
| 153 | #define MSDC_PAD_CTRL2_DATDRVP_M 0x70 |
| 154 | #define MSDC_PAD_CTRL2_DATDRVP_S 4 |
| 155 | #define MSDC_PAD_CTRL2_DATDRVN_M 0x7 |
| 156 | #define MSDC_PAD_CTRL2_DATDRVN_S 0 |
| 157 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 158 | /* PAD_TUNE */ |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 159 | #define MSDC_PAD_TUNE_CLKTDLY_M 0xf8000000 |
| 160 | #define MSDC_PAD_TUNE_CLKTDLY_S 27 |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 161 | #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000 |
| 162 | #define MSDC_PAD_TUNE_CMDRRDLY_S 22 |
| 163 | #define MSDC_PAD_TUNE_CMD_SEL BIT(21) |
| 164 | #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000 |
| 165 | #define MSDC_PAD_TUNE_CMDRDLY_S 16 |
| 166 | #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) |
| 167 | #define MSDC_PAD_TUNE_RD_SEL BIT(13) |
| 168 | #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00 |
| 169 | #define MSDC_PAD_TUNE_DATRRDLY_S 8 |
| 170 | #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f |
| 171 | #define MSDC_PAD_TUNE_DATWRDLY_S 0 |
| 172 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 173 | #define PAD_CMD_TUNE_RX_DLY3 0x3E |
| 174 | #define PAD_CMD_TUNE_RX_DLY3_S 1 |
| 175 | |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 176 | /* PAD_TUNE0 */ |
| 177 | #define MSDC_PAD_TUNE0_DAT0RDDLY_M 0x1f000000 |
| 178 | #define MSDC_PAD_TUNE0_DAT0RDDLY_S 24 |
| 179 | #define MSDC_PAD_TUNE0_DAT1RDDLY_M 0x1f0000 |
| 180 | #define MSDC_PAD_TUNE0_DAT1RDDLY_S 16 |
| 181 | #define MSDC_PAD_TUNE0_DAT2RDDLY_M 0x1f00 |
| 182 | #define MSDC_PAD_TUNE0_DAT2RDDLY_S 8 |
| 183 | #define MSDC_PAD_TUNE0_DAT3RDDLY_M 0x1f |
| 184 | #define MSDC_PAD_TUNE0_DAT3RDDLY_S 0 |
| 185 | |
| 186 | /* PAD_TUNE1 */ |
| 187 | #define MSDC_PAD_TUNE1_DAT4RDDLY_M 0x1f000000 |
| 188 | #define MSDC_PAD_TUNE1_DAT4RDDLY_S 24 |
| 189 | #define MSDC_PAD_TUNE1_DAT5RDDLY_M 0x1f0000 |
| 190 | #define MSDC_PAD_TUNE1_DAT5RDDLY_S 16 |
| 191 | #define MSDC_PAD_TUNE1_DAT6RDDLY_M 0x1f00 |
| 192 | #define MSDC_PAD_TUNE1_DAT6RDDLY_S 8 |
| 193 | #define MSDC_PAD_TUNE1_DAT7RDDLY_M 0x1f |
| 194 | #define MSDC_PAD_TUNE1_DAT7RDDLY_S 0 |
| 195 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 196 | /* EMMC50_CFG0 */ |
| 197 | #define EMMC50_CFG_CFCSTS_SEL BIT(4) |
| 198 | |
| 199 | /* SDC_FIFO_CFG */ |
| 200 | #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) |
| 201 | #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) |
| 202 | |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 203 | /* EMMC_TOP_CONTROL mask */ |
| 204 | #define PAD_RXDLY_SEL BIT(0) |
| 205 | #define DELAY_EN BIT(1) |
| 206 | #define PAD_DAT_RD_RXDLY2 (0x1f << 2) |
| 207 | #define PAD_DAT_RD_RXDLY (0x1f << 7) |
| 208 | #define PAD_DAT_RD_RXDLY_S 7 |
| 209 | #define PAD_DAT_RD_RXDLY2_SEL BIT(12) |
| 210 | #define PAD_DAT_RD_RXDLY_SEL BIT(13) |
| 211 | #define DATA_K_VALUE_SEL BIT(14) |
| 212 | #define SDC_RX_ENH_EN BIT(15) |
| 213 | |
| 214 | /* EMMC_TOP_CMD mask */ |
| 215 | #define PAD_CMD_RXDLY2 (0x1f << 0) |
| 216 | #define PAD_CMD_RXDLY (0x1f << 5) |
| 217 | #define PAD_CMD_RXDLY_S 5 |
| 218 | #define PAD_CMD_RD_RXDLY2_SEL BIT(10) |
| 219 | #define PAD_CMD_RD_RXDLY_SEL BIT(11) |
| 220 | #define PAD_CMD_TX_DLY (0x1f << 12) |
| 221 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 222 | /* SDC_CFG_BUSWIDTH */ |
| 223 | #define MSDC_BUS_1BITS 0x0 |
| 224 | #define MSDC_BUS_4BITS 0x1 |
| 225 | #define MSDC_BUS_8BITS 0x2 |
| 226 | |
| 227 | #define MSDC_FIFO_SIZE 128 |
| 228 | |
| 229 | #define PAD_DELAY_MAX 32 |
| 230 | |
| 231 | #define DEFAULT_CD_DEBOUNCE 8 |
| 232 | |
developer | c731074 | 2020-11-12 16:36:57 +0800 | [diff] [blame] | 233 | #define SCLK_CYCLES_SHIFT 20 |
| 234 | |
developer | 13b920a | 2021-04-20 16:37:10 +0800 | [diff] [blame] | 235 | #define MIN_BUS_CLK 200000 |
| 236 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 237 | #define CMD_INTS_MASK \ |
| 238 | (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) |
| 239 | |
| 240 | #define DATA_INTS_MASK \ |
| 241 | (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR) |
| 242 | |
| 243 | /* Register offset */ |
| 244 | struct mtk_sd_regs { |
| 245 | u32 msdc_cfg; |
| 246 | u32 msdc_iocon; |
| 247 | u32 msdc_ps; |
| 248 | u32 msdc_int; |
| 249 | u32 msdc_inten; |
| 250 | u32 msdc_fifocs; |
| 251 | u32 msdc_txdata; |
| 252 | u32 msdc_rxdata; |
| 253 | u32 reserved0[4]; |
| 254 | u32 sdc_cfg; |
| 255 | u32 sdc_cmd; |
| 256 | u32 sdc_arg; |
| 257 | u32 sdc_sts; |
| 258 | u32 sdc_resp[4]; |
| 259 | u32 sdc_blk_num; |
| 260 | u32 sdc_vol_chg; |
| 261 | u32 sdc_csts; |
| 262 | u32 sdc_csts_en; |
| 263 | u32 sdc_datcrc_sts; |
| 264 | u32 sdc_adv_cfg0; |
| 265 | u32 reserved1[2]; |
| 266 | u32 emmc_cfg0; |
| 267 | u32 emmc_cfg1; |
| 268 | u32 emmc_sts; |
| 269 | u32 emmc_iocon; |
| 270 | u32 sd_acmd_resp; |
| 271 | u32 sd_acmd19_trg; |
| 272 | u32 sd_acmd19_sts; |
| 273 | u32 dma_sa_high4bit; |
| 274 | u32 dma_sa; |
| 275 | u32 dma_ca; |
| 276 | u32 dma_ctrl; |
| 277 | u32 dma_cfg; |
| 278 | u32 sw_dbg_sel; |
| 279 | u32 sw_dbg_out; |
| 280 | u32 dma_length; |
| 281 | u32 reserved2; |
| 282 | u32 patch_bit0; |
| 283 | u32 patch_bit1; |
| 284 | u32 patch_bit2; |
| 285 | u32 reserved3; |
| 286 | u32 dat0_tune_crc; |
| 287 | u32 dat1_tune_crc; |
| 288 | u32 dat2_tune_crc; |
| 289 | u32 dat3_tune_crc; |
| 290 | u32 cmd_tune_crc; |
| 291 | u32 sdio_tune_wind; |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 292 | u32 reserved4[2]; |
| 293 | u32 pad_ctrl0; |
| 294 | u32 pad_ctrl1; |
| 295 | u32 pad_ctrl2; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 296 | u32 pad_tune; |
| 297 | u32 pad_tune0; |
| 298 | u32 pad_tune1; |
| 299 | u32 dat_rd_dly[4]; |
| 300 | u32 reserved5[2]; |
| 301 | u32 hw_dbg_sel; |
| 302 | u32 main_ver; |
| 303 | u32 eco_ver; |
| 304 | u32 reserved6[27]; |
| 305 | u32 pad_ds_tune; |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 306 | u32 pad_cmd_tune; |
| 307 | u32 reserved7[30]; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 308 | u32 emmc50_cfg0; |
| 309 | u32 reserved8[7]; |
| 310 | u32 sdc_fifo_cfg; |
| 311 | }; |
| 312 | |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 313 | struct msdc_top_regs { |
| 314 | u32 emmc_top_control; |
| 315 | u32 emmc_top_cmd; |
| 316 | u32 emmc50_pad_ctl0; |
| 317 | u32 emmc50_pad_ds_tune; |
| 318 | u32 emmc50_pad_dat0_tune; |
| 319 | u32 emmc50_pad_dat1_tune; |
| 320 | u32 emmc50_pad_dat2_tune; |
| 321 | u32 emmc50_pad_dat3_tune; |
| 322 | u32 emmc50_pad_dat4_tune; |
| 323 | u32 emmc50_pad_dat5_tune; |
| 324 | u32 emmc50_pad_dat6_tune; |
| 325 | u32 emmc50_pad_dat7_tune; |
| 326 | }; |
| 327 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 328 | struct msdc_compatible { |
| 329 | u8 clk_div_bits; |
| 330 | bool pad_tune0; |
| 331 | bool async_fifo; |
| 332 | bool data_tune; |
| 333 | bool busy_check; |
| 334 | bool stop_clk_fix; |
| 335 | bool enhance_rx; |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 336 | bool builtin_pad_ctrl; |
| 337 | bool default_pad_dly; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 338 | }; |
| 339 | |
| 340 | struct msdc_delay_phase { |
| 341 | u8 maxlen; |
| 342 | u8 start; |
| 343 | u8 final_phase; |
| 344 | }; |
| 345 | |
| 346 | struct msdc_plat { |
| 347 | struct mmc_config cfg; |
| 348 | struct mmc mmc; |
| 349 | }; |
| 350 | |
| 351 | struct msdc_tune_para { |
| 352 | u32 iocon; |
| 353 | u32 pad_tune; |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 354 | u32 pad_cmd_tune; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 355 | }; |
| 356 | |
| 357 | struct msdc_host { |
| 358 | struct mtk_sd_regs *base; |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 359 | struct msdc_top_regs *top_base; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 360 | struct mmc *mmc; |
| 361 | |
| 362 | struct msdc_compatible *dev_comp; |
| 363 | |
| 364 | struct clk src_clk; /* for SD/MMC bus clock */ |
Fabien Parent | 297fa1a | 2019-03-24 16:46:32 +0100 | [diff] [blame] | 365 | struct clk src_clk_cg; /* optional, MSDC source clock control gate */ |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 366 | struct clk h_clk; /* MSDC core clock */ |
| 367 | |
| 368 | u32 src_clk_freq; /* source clock */ |
| 369 | u32 mclk; /* mmc framework required bus clock */ |
| 370 | u32 sclk; /* actual calculated bus clock */ |
| 371 | |
| 372 | /* operation timeout clocks */ |
| 373 | u32 timeout_ns; |
| 374 | u32 timeout_clks; |
| 375 | |
| 376 | /* tuning options */ |
| 377 | u32 hs400_ds_delay; |
| 378 | u32 hs200_cmd_int_delay; |
| 379 | u32 hs200_write_int_delay; |
| 380 | u32 latch_ck; |
| 381 | u32 r_smpl; /* sample edge */ |
| 382 | bool hs400_mode; |
| 383 | |
| 384 | /* whether to use gpio detection or built-in hw detection */ |
| 385 | bool builtin_cd; |
developer | 399e4af | 2019-09-25 17:45:38 +0800 | [diff] [blame] | 386 | bool cd_active_high; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 387 | |
| 388 | /* card detection / write protection GPIOs */ |
Fabien Parent | 8ed608a | 2019-03-24 16:46:34 +0100 | [diff] [blame] | 389 | #if CONFIG_IS_ENABLED(DM_GPIO) |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 390 | struct gpio_desc gpio_wp; |
| 391 | struct gpio_desc gpio_cd; |
| 392 | #endif |
| 393 | |
| 394 | uint last_resp_type; |
| 395 | uint last_data_write; |
| 396 | |
| 397 | enum bus_mode timing; |
| 398 | |
| 399 | struct msdc_tune_para def_tune_para; |
| 400 | struct msdc_tune_para saved_tune_para; |
| 401 | }; |
| 402 | |
| 403 | static void msdc_reset_hw(struct msdc_host *host) |
| 404 | { |
| 405 | u32 reg; |
| 406 | |
| 407 | setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST); |
| 408 | |
| 409 | readl_poll_timeout(&host->base->msdc_cfg, reg, |
| 410 | !(reg & MSDC_CFG_RST), 1000000); |
| 411 | } |
| 412 | |
| 413 | static void msdc_fifo_clr(struct msdc_host *host) |
| 414 | { |
| 415 | u32 reg; |
| 416 | |
| 417 | setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR); |
| 418 | |
| 419 | readl_poll_timeout(&host->base->msdc_fifocs, reg, |
| 420 | !(reg & MSDC_FIFOCS_CLR), 1000000); |
| 421 | } |
| 422 | |
| 423 | static u32 msdc_fifo_rx_bytes(struct msdc_host *host) |
| 424 | { |
| 425 | return (readl(&host->base->msdc_fifocs) & |
| 426 | MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S; |
| 427 | } |
| 428 | |
| 429 | static u32 msdc_fifo_tx_bytes(struct msdc_host *host) |
| 430 | { |
| 431 | return (readl(&host->base->msdc_fifocs) & |
| 432 | MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S; |
| 433 | } |
| 434 | |
| 435 | static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd) |
| 436 | { |
| 437 | u32 resp; |
| 438 | |
| 439 | switch (cmd->resp_type) { |
| 440 | /* Actually, R1, R5, R6, R7 are the same */ |
| 441 | case MMC_RSP_R1: |
| 442 | resp = 0x1; |
| 443 | break; |
| 444 | case MMC_RSP_R1b: |
| 445 | resp = 0x7; |
| 446 | break; |
| 447 | case MMC_RSP_R2: |
| 448 | resp = 0x2; |
| 449 | break; |
| 450 | case MMC_RSP_R3: |
| 451 | resp = 0x3; |
| 452 | break; |
| 453 | case MMC_RSP_NONE: |
| 454 | default: |
| 455 | resp = 0x0; |
| 456 | break; |
| 457 | } |
| 458 | |
| 459 | return resp; |
| 460 | } |
| 461 | |
| 462 | static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, |
| 463 | struct mmc_cmd *cmd, |
| 464 | struct mmc_data *data) |
| 465 | { |
| 466 | u32 opcode = cmd->cmdidx; |
| 467 | u32 resp_type = msdc_cmd_find_resp(host, cmd); |
| 468 | uint blocksize = 0; |
| 469 | u32 dtype = 0; |
| 470 | u32 rawcmd = 0; |
| 471 | |
| 472 | switch (opcode) { |
| 473 | case MMC_CMD_WRITE_MULTIPLE_BLOCK: |
| 474 | case MMC_CMD_READ_MULTIPLE_BLOCK: |
| 475 | dtype = 2; |
| 476 | break; |
| 477 | case MMC_CMD_WRITE_SINGLE_BLOCK: |
| 478 | case MMC_CMD_READ_SINGLE_BLOCK: |
| 479 | case SD_CMD_APP_SEND_SCR: |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 480 | case MMC_CMD_SEND_TUNING_BLOCK: |
| 481 | case MMC_CMD_SEND_TUNING_BLOCK_HS200: |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 482 | dtype = 1; |
| 483 | break; |
| 484 | case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */ |
| 485 | case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */ |
| 486 | case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */ |
| 487 | if (data) |
| 488 | dtype = 1; |
| 489 | } |
| 490 | |
| 491 | if (data) { |
| 492 | if (data->flags == MMC_DATA_WRITE) |
| 493 | rawcmd |= SDC_CMD_WR; |
| 494 | |
| 495 | if (data->blocks > 1) |
| 496 | dtype = 2; |
| 497 | |
| 498 | blocksize = data->blocksize; |
| 499 | } |
| 500 | |
| 501 | rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) | |
| 502 | ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) | |
| 503 | ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) | |
| 504 | ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M); |
| 505 | |
| 506 | if (opcode == MMC_CMD_STOP_TRANSMISSION) |
| 507 | rawcmd |= SDC_CMD_STOP; |
| 508 | |
| 509 | return rawcmd; |
| 510 | } |
| 511 | |
| 512 | static int msdc_cmd_done(struct msdc_host *host, int events, |
| 513 | struct mmc_cmd *cmd) |
| 514 | { |
| 515 | u32 *rsp = cmd->response; |
| 516 | int ret = 0; |
| 517 | |
| 518 | if (cmd->resp_type & MMC_RSP_PRESENT) { |
| 519 | if (cmd->resp_type & MMC_RSP_136) { |
| 520 | rsp[0] = readl(&host->base->sdc_resp[3]); |
| 521 | rsp[1] = readl(&host->base->sdc_resp[2]); |
| 522 | rsp[2] = readl(&host->base->sdc_resp[1]); |
| 523 | rsp[3] = readl(&host->base->sdc_resp[0]); |
| 524 | } else { |
| 525 | rsp[0] = readl(&host->base->sdc_resp[0]); |
| 526 | } |
| 527 | } |
| 528 | |
| 529 | if (!(events & MSDC_INT_CMDRDY)) { |
| 530 | if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK && |
| 531 | cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200) |
| 532 | /* |
| 533 | * should not clear fifo/interrupt as the tune data |
| 534 | * may have alreay come. |
| 535 | */ |
| 536 | msdc_reset_hw(host); |
| 537 | |
| 538 | if (events & MSDC_INT_CMDTMO) |
| 539 | ret = -ETIMEDOUT; |
| 540 | else |
| 541 | ret = -EIO; |
| 542 | } |
| 543 | |
| 544 | return ret; |
| 545 | } |
| 546 | |
| 547 | static bool msdc_cmd_is_ready(struct msdc_host *host) |
| 548 | { |
| 549 | int ret; |
| 550 | u32 reg; |
| 551 | |
| 552 | /* The max busy time we can endure is 20ms */ |
| 553 | ret = readl_poll_timeout(&host->base->sdc_sts, reg, |
| 554 | !(reg & SDC_STS_CMDBUSY), 20000); |
| 555 | |
| 556 | if (ret) { |
| 557 | pr_err("CMD bus busy detected\n"); |
| 558 | msdc_reset_hw(host); |
| 559 | return false; |
| 560 | } |
| 561 | |
| 562 | if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) { |
| 563 | ret = readl_poll_timeout(&host->base->msdc_ps, reg, |
| 564 | reg & MSDC_PS_DAT0, 1000000); |
| 565 | |
| 566 | if (ret) { |
| 567 | pr_err("Card stuck in programming state!\n"); |
| 568 | msdc_reset_hw(host); |
| 569 | return false; |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | return true; |
| 574 | } |
| 575 | |
| 576 | static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd, |
| 577 | struct mmc_data *data) |
| 578 | { |
| 579 | u32 rawcmd; |
| 580 | u32 status; |
| 581 | u32 blocks = 0; |
| 582 | int ret; |
| 583 | |
| 584 | if (!msdc_cmd_is_ready(host)) |
| 585 | return -EIO; |
| 586 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 587 | if ((readl(&host->base->msdc_fifocs) & |
| 588 | MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S || |
| 589 | (readl(&host->base->msdc_fifocs) & |
| 590 | MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) { |
| 591 | pr_err("TX/RX FIFO non-empty before start of IO. Reset\n"); |
| 592 | msdc_reset_hw(host); |
| 593 | } |
| 594 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 595 | msdc_fifo_clr(host); |
| 596 | |
| 597 | host->last_resp_type = cmd->resp_type; |
| 598 | host->last_data_write = 0; |
| 599 | |
| 600 | rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data); |
| 601 | |
| 602 | if (data) |
| 603 | blocks = data->blocks; |
| 604 | |
| 605 | writel(CMD_INTS_MASK, &host->base->msdc_int); |
developer | 068cc65 | 2019-12-31 11:29:25 +0800 | [diff] [blame] | 606 | writel(DATA_INTS_MASK, &host->base->msdc_int); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 607 | writel(blocks, &host->base->sdc_blk_num); |
| 608 | writel(cmd->cmdarg, &host->base->sdc_arg); |
| 609 | writel(rawcmd, &host->base->sdc_cmd); |
| 610 | |
| 611 | ret = readl_poll_timeout(&host->base->msdc_int, status, |
| 612 | status & CMD_INTS_MASK, 1000000); |
| 613 | |
| 614 | if (ret) |
| 615 | status = MSDC_INT_CMDTMO; |
| 616 | |
| 617 | return msdc_cmd_done(host, status, cmd); |
| 618 | } |
| 619 | |
| 620 | static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size) |
| 621 | { |
| 622 | u32 *wbuf; |
| 623 | |
| 624 | while ((size_t)buf % 4) { |
| 625 | *buf++ = readb(&host->base->msdc_rxdata); |
| 626 | size--; |
| 627 | } |
| 628 | |
| 629 | wbuf = (u32 *)buf; |
| 630 | while (size >= 4) { |
| 631 | *wbuf++ = readl(&host->base->msdc_rxdata); |
| 632 | size -= 4; |
| 633 | } |
| 634 | |
| 635 | buf = (u8 *)wbuf; |
| 636 | while (size) { |
| 637 | *buf++ = readb(&host->base->msdc_rxdata); |
| 638 | size--; |
| 639 | } |
| 640 | } |
| 641 | |
| 642 | static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size) |
| 643 | { |
| 644 | const u32 *wbuf; |
| 645 | |
| 646 | while ((size_t)buf % 4) { |
| 647 | writeb(*buf++, &host->base->msdc_txdata); |
| 648 | size--; |
| 649 | } |
| 650 | |
| 651 | wbuf = (const u32 *)buf; |
| 652 | while (size >= 4) { |
| 653 | writel(*wbuf++, &host->base->msdc_txdata); |
| 654 | size -= 4; |
| 655 | } |
| 656 | |
| 657 | buf = (const u8 *)wbuf; |
| 658 | while (size) { |
| 659 | writeb(*buf++, &host->base->msdc_txdata); |
| 660 | size--; |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size) |
| 665 | { |
| 666 | u32 status; |
| 667 | u32 chksz; |
| 668 | int ret = 0; |
| 669 | |
| 670 | while (1) { |
| 671 | status = readl(&host->base->msdc_int); |
| 672 | writel(status, &host->base->msdc_int); |
| 673 | status &= DATA_INTS_MASK; |
| 674 | |
| 675 | if (status & MSDC_INT_DATCRCERR) { |
| 676 | ret = -EIO; |
| 677 | break; |
| 678 | } |
| 679 | |
| 680 | if (status & MSDC_INT_DATTMO) { |
| 681 | ret = -ETIMEDOUT; |
| 682 | break; |
| 683 | } |
| 684 | |
Fabien Parent | 79a6073 | 2019-01-17 18:06:00 +0100 | [diff] [blame] | 685 | chksz = min(size, (u32)MSDC_FIFO_SIZE); |
| 686 | |
| 687 | if (msdc_fifo_rx_bytes(host) >= chksz) { |
| 688 | msdc_fifo_read(host, ptr, chksz); |
| 689 | ptr += chksz; |
| 690 | size -= chksz; |
| 691 | } |
| 692 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 693 | if (status & MSDC_INT_XFER_COMPL) { |
| 694 | if (size) { |
| 695 | pr_err("data not fully read\n"); |
| 696 | ret = -EIO; |
| 697 | } |
| 698 | |
| 699 | break; |
| 700 | } |
Fabien Parent | 79a6073 | 2019-01-17 18:06:00 +0100 | [diff] [blame] | 701 | } |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 702 | |
| 703 | return ret; |
| 704 | } |
| 705 | |
| 706 | static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size) |
| 707 | { |
| 708 | u32 status; |
| 709 | u32 chksz; |
| 710 | int ret = 0; |
| 711 | |
| 712 | while (1) { |
| 713 | status = readl(&host->base->msdc_int); |
| 714 | writel(status, &host->base->msdc_int); |
| 715 | status &= DATA_INTS_MASK; |
| 716 | |
| 717 | if (status & MSDC_INT_DATCRCERR) { |
| 718 | ret = -EIO; |
| 719 | break; |
| 720 | } |
| 721 | |
| 722 | if (status & MSDC_INT_DATTMO) { |
| 723 | ret = -ETIMEDOUT; |
| 724 | break; |
| 725 | } |
| 726 | |
| 727 | if (status & MSDC_INT_XFER_COMPL) { |
| 728 | if (size) { |
| 729 | pr_err("data not fully written\n"); |
| 730 | ret = -EIO; |
| 731 | } |
| 732 | |
| 733 | break; |
| 734 | } |
| 735 | |
| 736 | chksz = min(size, (u32)MSDC_FIFO_SIZE); |
| 737 | |
| 738 | if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) { |
| 739 | msdc_fifo_write(host, ptr, chksz); |
| 740 | ptr += chksz; |
| 741 | size -= chksz; |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | return ret; |
| 746 | } |
| 747 | |
| 748 | static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) |
| 749 | { |
| 750 | u32 size; |
| 751 | int ret; |
| 752 | |
| 753 | if (data->flags == MMC_DATA_WRITE) |
| 754 | host->last_data_write = 1; |
| 755 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 756 | size = data->blocks * data->blocksize; |
| 757 | |
| 758 | if (data->flags == MMC_DATA_WRITE) |
| 759 | ret = msdc_pio_write(host, (const u8 *)data->src, size); |
| 760 | else |
| 761 | ret = msdc_pio_read(host, (u8 *)data->dest, size); |
| 762 | |
| 763 | if (ret) { |
| 764 | msdc_reset_hw(host); |
| 765 | msdc_fifo_clr(host); |
| 766 | } |
| 767 | |
| 768 | return ret; |
| 769 | } |
| 770 | |
| 771 | static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
| 772 | struct mmc_data *data) |
| 773 | { |
| 774 | struct msdc_host *host = dev_get_priv(dev); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 775 | int cmd_ret, data_ret; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 776 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 777 | cmd_ret = msdc_start_command(host, cmd, data); |
| 778 | if (cmd_ret && |
| 779 | !(cmd_ret == -EIO && |
| 780 | (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || |
| 781 | cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))) |
| 782 | return cmd_ret; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 783 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 784 | if (data) { |
| 785 | data_ret = msdc_start_data(host, data); |
| 786 | if (cmd_ret) |
| 787 | return cmd_ret; |
| 788 | else |
| 789 | return data_ret; |
| 790 | } |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 791 | |
| 792 | return 0; |
| 793 | } |
| 794 | |
| 795 | static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) |
| 796 | { |
developer | c731074 | 2020-11-12 16:36:57 +0800 | [diff] [blame] | 797 | u32 timeout, clk_ns, shift = SCLK_CYCLES_SHIFT; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 798 | u32 mode = 0; |
| 799 | |
| 800 | host->timeout_ns = ns; |
| 801 | host->timeout_clks = clks; |
| 802 | |
| 803 | if (host->sclk == 0) { |
| 804 | timeout = 0; |
| 805 | } else { |
| 806 | clk_ns = 1000000000UL / host->sclk; |
| 807 | timeout = (ns + clk_ns - 1) / clk_ns + clks; |
| 808 | /* unit is 1048576 sclk cycles */ |
developer | 607faf7 | 2019-09-25 17:45:37 +0800 | [diff] [blame] | 809 | timeout = (timeout + (0x1 << shift) - 1) >> shift; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 810 | if (host->dev_comp->clk_div_bits == 8) |
| 811 | mode = (readl(&host->base->msdc_cfg) & |
| 812 | MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S; |
| 813 | else |
| 814 | mode = (readl(&host->base->msdc_cfg) & |
| 815 | MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S; |
| 816 | /* DDR mode will double the clk cycles for data timeout */ |
| 817 | timeout = mode >= 2 ? timeout * 2 : timeout; |
| 818 | timeout = timeout > 1 ? timeout - 1 : 0; |
| 819 | timeout = timeout > 255 ? 255 : timeout; |
| 820 | } |
| 821 | |
| 822 | clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, |
| 823 | timeout << SDC_CFG_DTOC_S); |
| 824 | } |
| 825 | |
| 826 | static void msdc_set_buswidth(struct msdc_host *host, u32 width) |
| 827 | { |
| 828 | u32 val = readl(&host->base->sdc_cfg); |
| 829 | |
| 830 | val &= ~SDC_CFG_BUSWIDTH_M; |
| 831 | |
| 832 | switch (width) { |
| 833 | default: |
| 834 | case 1: |
| 835 | val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S); |
| 836 | break; |
| 837 | case 4: |
| 838 | val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S); |
| 839 | break; |
| 840 | case 8: |
| 841 | val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S); |
| 842 | break; |
| 843 | } |
| 844 | |
| 845 | writel(val, &host->base->sdc_cfg); |
| 846 | } |
| 847 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 848 | static void msdc_set_mclk(struct udevice *dev, |
| 849 | struct msdc_host *host, enum bus_mode timing, u32 hz) |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 850 | { |
| 851 | u32 mode; |
| 852 | u32 div; |
| 853 | u32 sclk; |
| 854 | u32 reg; |
| 855 | |
| 856 | if (!hz) { |
| 857 | host->mclk = 0; |
| 858 | clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); |
| 859 | return; |
| 860 | } |
| 861 | |
| 862 | if (host->dev_comp->clk_div_bits == 8) |
| 863 | clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE); |
| 864 | else |
| 865 | clrbits_le32(&host->base->msdc_cfg, |
| 866 | MSDC_CFG_HS400_CK_MODE_EXT); |
| 867 | |
| 868 | if (timing == UHS_DDR50 || timing == MMC_DDR_52 || |
| 869 | timing == MMC_HS_400) { |
| 870 | if (timing == MMC_HS_400) |
| 871 | mode = 0x3; |
| 872 | else |
| 873 | mode = 0x2; /* ddr mode and use divisor */ |
| 874 | |
| 875 | if (hz >= (host->src_clk_freq >> 2)) { |
| 876 | div = 0; /* mean div = 1/4 */ |
| 877 | sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ |
| 878 | } else { |
| 879 | div = (host->src_clk_freq + ((hz << 2) - 1)) / |
| 880 | (hz << 2); |
| 881 | sclk = (host->src_clk_freq >> 2) / div; |
| 882 | div = (div >> 1); |
| 883 | } |
| 884 | |
| 885 | if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) { |
| 886 | if (host->dev_comp->clk_div_bits == 8) |
| 887 | setbits_le32(&host->base->msdc_cfg, |
| 888 | MSDC_CFG_HS400_CK_MODE); |
| 889 | else |
| 890 | setbits_le32(&host->base->msdc_cfg, |
| 891 | MSDC_CFG_HS400_CK_MODE_EXT); |
| 892 | |
| 893 | sclk = host->src_clk_freq >> 1; |
| 894 | div = 0; /* div is ignore when bit18 is set */ |
| 895 | } |
| 896 | } else if (hz >= host->src_clk_freq) { |
| 897 | mode = 0x1; /* no divisor */ |
| 898 | div = 0; |
| 899 | sclk = host->src_clk_freq; |
| 900 | } else { |
| 901 | mode = 0x0; /* use divisor */ |
| 902 | if (hz >= (host->src_clk_freq >> 1)) { |
| 903 | div = 0; /* mean div = 1/2 */ |
| 904 | sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ |
| 905 | } else { |
| 906 | div = (host->src_clk_freq + ((hz << 2) - 1)) / |
| 907 | (hz << 2); |
| 908 | sclk = (host->src_clk_freq >> 2) / div; |
| 909 | } |
| 910 | } |
| 911 | |
| 912 | clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); |
| 913 | |
| 914 | if (host->dev_comp->clk_div_bits == 8) { |
| 915 | div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S)); |
| 916 | clrsetbits_le32(&host->base->msdc_cfg, |
| 917 | MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M, |
| 918 | (mode << MSDC_CFG_CKMOD_S) | |
| 919 | (div << MSDC_CFG_CKDIV_S)); |
| 920 | } else { |
| 921 | div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >> |
| 922 | MSDC_CFG_CKDIV_EXT_S)); |
| 923 | clrsetbits_le32(&host->base->msdc_cfg, |
| 924 | MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M, |
| 925 | (mode << MSDC_CFG_CKMOD_EXT_S) | |
| 926 | (div << MSDC_CFG_CKDIV_EXT_S)); |
| 927 | } |
| 928 | |
| 929 | readl_poll_timeout(&host->base->msdc_cfg, reg, |
| 930 | reg & MSDC_CFG_CKSTB, 1000000); |
| 931 | |
| 932 | setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); |
| 933 | host->sclk = sclk; |
| 934 | host->mclk = hz; |
| 935 | host->timing = timing; |
| 936 | |
| 937 | /* needed because clk changed. */ |
| 938 | msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); |
| 939 | |
| 940 | /* |
| 941 | * mmc_select_hs400() will drop to 50Mhz and High speed mode, |
| 942 | * tune result of hs200/200Mhz is not suitable for 50Mhz |
| 943 | */ |
| 944 | if (host->sclk <= 52000000) { |
| 945 | writel(host->def_tune_para.iocon, &host->base->msdc_iocon); |
| 946 | writel(host->def_tune_para.pad_tune, |
| 947 | &host->base->pad_tune); |
| 948 | } else { |
| 949 | writel(host->saved_tune_para.iocon, &host->base->msdc_iocon); |
| 950 | writel(host->saved_tune_para.pad_tune, |
| 951 | &host->base->pad_tune); |
| 952 | } |
| 953 | |
| 954 | dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing); |
| 955 | } |
| 956 | |
| 957 | static int msdc_ops_set_ios(struct udevice *dev) |
| 958 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 959 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 960 | struct msdc_host *host = dev_get_priv(dev); |
| 961 | struct mmc *mmc = &plat->mmc; |
| 962 | uint clock = mmc->clock; |
| 963 | |
| 964 | msdc_set_buswidth(host, mmc->bus_width); |
| 965 | |
| 966 | if (mmc->clk_disable) |
| 967 | clock = 0; |
| 968 | else if (clock < mmc->cfg->f_min) |
| 969 | clock = mmc->cfg->f_min; |
| 970 | |
| 971 | if (host->mclk != clock || host->timing != mmc->selected_mode) |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 972 | msdc_set_mclk(dev, host, mmc->selected_mode, clock); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 973 | |
| 974 | return 0; |
| 975 | } |
| 976 | |
| 977 | static int msdc_ops_get_cd(struct udevice *dev) |
| 978 | { |
| 979 | struct msdc_host *host = dev_get_priv(dev); |
| 980 | u32 val; |
| 981 | |
| 982 | if (host->builtin_cd) { |
| 983 | val = readl(&host->base->msdc_ps); |
developer | 399e4af | 2019-09-25 17:45:38 +0800 | [diff] [blame] | 984 | val = !!(val & MSDC_PS_CDSTS); |
| 985 | |
| 986 | return !val ^ host->cd_active_high; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 987 | } |
| 988 | |
Fabien Parent | 8ed608a | 2019-03-24 16:46:34 +0100 | [diff] [blame] | 989 | #if CONFIG_IS_ENABLED(DM_GPIO) |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 990 | if (!host->gpio_cd.dev) |
| 991 | return 1; |
| 992 | |
| 993 | return dm_gpio_get_value(&host->gpio_cd); |
| 994 | #else |
| 995 | return 1; |
| 996 | #endif |
| 997 | } |
| 998 | |
| 999 | static int msdc_ops_get_wp(struct udevice *dev) |
| 1000 | { |
Fabien Parent | 8ed608a | 2019-03-24 16:46:34 +0100 | [diff] [blame] | 1001 | #if CONFIG_IS_ENABLED(DM_GPIO) |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1002 | struct msdc_host *host = dev_get_priv(dev); |
| 1003 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1004 | if (!host->gpio_wp.dev) |
| 1005 | return 0; |
| 1006 | |
| 1007 | return !dm_gpio_get_value(&host->gpio_wp); |
| 1008 | #else |
| 1009 | return 0; |
| 1010 | #endif |
| 1011 | } |
| 1012 | |
| 1013 | #ifdef MMC_SUPPORTS_TUNING |
| 1014 | static u32 test_delay_bit(u32 delay, u32 bit) |
| 1015 | { |
| 1016 | bit %= PAD_DELAY_MAX; |
| 1017 | return delay & (1 << bit); |
| 1018 | } |
| 1019 | |
| 1020 | static int get_delay_len(u32 delay, u32 start_bit) |
| 1021 | { |
| 1022 | int i; |
| 1023 | |
| 1024 | for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { |
| 1025 | if (test_delay_bit(delay, start_bit + i) == 0) |
| 1026 | return i; |
| 1027 | } |
| 1028 | |
| 1029 | return PAD_DELAY_MAX - start_bit; |
| 1030 | } |
| 1031 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1032 | static struct msdc_delay_phase get_best_delay(struct udevice *dev, |
| 1033 | struct msdc_host *host, u32 delay) |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1034 | { |
| 1035 | int start = 0, len = 0; |
| 1036 | int start_final = 0, len_final = 0; |
| 1037 | u8 final_phase = 0xff; |
| 1038 | struct msdc_delay_phase delay_phase = { 0, }; |
| 1039 | |
| 1040 | if (delay == 0) { |
| 1041 | dev_err(dev, "phase error: [map:%x]\n", delay); |
| 1042 | delay_phase.final_phase = final_phase; |
| 1043 | return delay_phase; |
| 1044 | } |
| 1045 | |
| 1046 | while (start < PAD_DELAY_MAX) { |
| 1047 | len = get_delay_len(delay, start); |
| 1048 | if (len_final < len) { |
| 1049 | start_final = start; |
| 1050 | len_final = len; |
| 1051 | } |
| 1052 | |
| 1053 | start += len ? len : 1; |
| 1054 | if (len >= 12 && start_final < 4) |
| 1055 | break; |
| 1056 | } |
| 1057 | |
| 1058 | /* The rule is to find the smallest delay cell */ |
| 1059 | if (start_final == 0) |
| 1060 | final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; |
| 1061 | else |
| 1062 | final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; |
| 1063 | |
| 1064 | dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", |
| 1065 | delay, len_final, final_phase); |
| 1066 | |
| 1067 | delay_phase.maxlen = len_final; |
| 1068 | delay_phase.start = start_final; |
| 1069 | delay_phase.final_phase = final_phase; |
| 1070 | return delay_phase; |
| 1071 | } |
| 1072 | |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1073 | static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) |
| 1074 | { |
| 1075 | void __iomem *tune_reg = &host->base->pad_tune; |
| 1076 | |
| 1077 | if (host->dev_comp->pad_tune0) |
| 1078 | tune_reg = &host->base->pad_tune0; |
| 1079 | |
| 1080 | if (host->top_base) |
| 1081 | clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY, |
| 1082 | value << PAD_CMD_RXDLY_S); |
| 1083 | else |
| 1084 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, |
| 1085 | value << MSDC_PAD_TUNE_CMDRDLY_S); |
| 1086 | } |
| 1087 | |
| 1088 | static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) |
| 1089 | { |
| 1090 | void __iomem *tune_reg = &host->base->pad_tune; |
| 1091 | |
| 1092 | if (host->dev_comp->pad_tune0) |
| 1093 | tune_reg = &host->base->pad_tune0; |
| 1094 | |
| 1095 | if (host->top_base) |
| 1096 | clrsetbits_le32(&host->top_base->emmc_top_control, |
| 1097 | PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S); |
| 1098 | else |
| 1099 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, |
| 1100 | value << MSDC_PAD_TUNE_DATRRDLY_S); |
| 1101 | } |
| 1102 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1103 | static int hs400_tune_response(struct udevice *dev, u32 opcode) |
| 1104 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1105 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1106 | struct msdc_host *host = dev_get_priv(dev); |
| 1107 | struct mmc *mmc = &plat->mmc; |
| 1108 | u32 cmd_delay = 0; |
| 1109 | struct msdc_delay_phase final_cmd_delay = { 0, }; |
| 1110 | u8 final_delay; |
| 1111 | void __iomem *tune_reg = &host->base->pad_cmd_tune; |
| 1112 | int cmd_err; |
| 1113 | int i, j; |
| 1114 | |
| 1115 | setbits_le32(&host->base->pad_cmd_tune, BIT(0)); |
| 1116 | |
| 1117 | if (mmc->selected_mode == MMC_HS_200 || |
| 1118 | mmc->selected_mode == UHS_SDR104) |
| 1119 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, |
| 1120 | host->hs200_cmd_int_delay << |
| 1121 | MSDC_PAD_TUNE_CMDRRDLY_S); |
| 1122 | |
| 1123 | if (host->r_smpl) |
| 1124 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); |
| 1125 | else |
| 1126 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); |
| 1127 | |
| 1128 | for (i = 0; i < PAD_DELAY_MAX; i++) { |
| 1129 | clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3, |
| 1130 | i << PAD_CMD_TUNE_RX_DLY3_S); |
| 1131 | |
| 1132 | for (j = 0; j < 3; j++) { |
| 1133 | mmc_send_tuning(mmc, opcode, &cmd_err); |
| 1134 | if (!cmd_err) { |
| 1135 | cmd_delay |= (1 << i); |
| 1136 | } else { |
| 1137 | cmd_delay &= ~(1 << i); |
| 1138 | break; |
| 1139 | } |
| 1140 | } |
| 1141 | } |
| 1142 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1143 | final_cmd_delay = get_best_delay(dev, host, cmd_delay); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1144 | clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3, |
| 1145 | final_cmd_delay.final_phase << |
| 1146 | PAD_CMD_TUNE_RX_DLY3_S); |
| 1147 | final_delay = final_cmd_delay.final_phase; |
| 1148 | |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1149 | dev_info(dev, "Final cmd pad delay: %x\n", final_delay); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1150 | return final_delay == 0xff ? -EIO : 0; |
| 1151 | } |
| 1152 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1153 | static int msdc_tune_response(struct udevice *dev, u32 opcode) |
| 1154 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1155 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1156 | struct msdc_host *host = dev_get_priv(dev); |
| 1157 | struct mmc *mmc = &plat->mmc; |
| 1158 | u32 rise_delay = 0, fall_delay = 0; |
| 1159 | struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; |
| 1160 | struct msdc_delay_phase internal_delay_phase; |
| 1161 | u8 final_delay, final_maxlen; |
| 1162 | u32 internal_delay = 0; |
| 1163 | void __iomem *tune_reg = &host->base->pad_tune; |
| 1164 | int cmd_err; |
| 1165 | int i, j; |
| 1166 | |
| 1167 | if (host->dev_comp->pad_tune0) |
| 1168 | tune_reg = &host->base->pad_tune0; |
| 1169 | |
| 1170 | if (mmc->selected_mode == MMC_HS_200 || |
| 1171 | mmc->selected_mode == UHS_SDR104) |
| 1172 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, |
| 1173 | host->hs200_cmd_int_delay << |
| 1174 | MSDC_PAD_TUNE_CMDRRDLY_S); |
| 1175 | |
| 1176 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); |
| 1177 | |
| 1178 | for (i = 0; i < PAD_DELAY_MAX; i++) { |
| 1179 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, |
| 1180 | i << MSDC_PAD_TUNE_CMDRDLY_S); |
| 1181 | |
| 1182 | for (j = 0; j < 3; j++) { |
| 1183 | mmc_send_tuning(mmc, opcode, &cmd_err); |
| 1184 | if (!cmd_err) { |
| 1185 | rise_delay |= (1 << i); |
| 1186 | } else { |
| 1187 | rise_delay &= ~(1 << i); |
| 1188 | break; |
| 1189 | } |
| 1190 | } |
| 1191 | } |
| 1192 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1193 | final_rise_delay = get_best_delay(dev, host, rise_delay); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1194 | /* if rising edge has enough margin, do not scan falling edge */ |
| 1195 | if (final_rise_delay.maxlen >= 12 || |
| 1196 | (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) |
| 1197 | goto skip_fall; |
| 1198 | |
| 1199 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); |
| 1200 | for (i = 0; i < PAD_DELAY_MAX; i++) { |
| 1201 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, |
| 1202 | i << MSDC_PAD_TUNE_CMDRDLY_S); |
| 1203 | |
| 1204 | for (j = 0; j < 3; j++) { |
| 1205 | mmc_send_tuning(mmc, opcode, &cmd_err); |
| 1206 | if (!cmd_err) { |
| 1207 | fall_delay |= (1 << i); |
| 1208 | } else { |
| 1209 | fall_delay &= ~(1 << i); |
| 1210 | break; |
| 1211 | } |
| 1212 | } |
| 1213 | } |
| 1214 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1215 | final_fall_delay = get_best_delay(dev, host, fall_delay); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1216 | |
| 1217 | skip_fall: |
| 1218 | final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); |
| 1219 | if (final_maxlen == final_rise_delay.maxlen) { |
| 1220 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); |
| 1221 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, |
| 1222 | final_rise_delay.final_phase << |
| 1223 | MSDC_PAD_TUNE_CMDRDLY_S); |
| 1224 | final_delay = final_rise_delay.final_phase; |
| 1225 | } else { |
| 1226 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); |
| 1227 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, |
| 1228 | final_fall_delay.final_phase << |
| 1229 | MSDC_PAD_TUNE_CMDRDLY_S); |
| 1230 | final_delay = final_fall_delay.final_phase; |
| 1231 | } |
| 1232 | |
| 1233 | if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) |
| 1234 | goto skip_internal; |
| 1235 | |
| 1236 | for (i = 0; i < PAD_DELAY_MAX; i++) { |
| 1237 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, |
| 1238 | i << MSDC_PAD_TUNE_CMDRRDLY_S); |
| 1239 | |
| 1240 | mmc_send_tuning(mmc, opcode, &cmd_err); |
| 1241 | if (!cmd_err) |
| 1242 | internal_delay |= (1 << i); |
| 1243 | } |
| 1244 | |
Fabien Parent | f9ca467 | 2020-10-15 18:38:18 +0200 | [diff] [blame] | 1245 | dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1246 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1247 | internal_delay_phase = get_best_delay(dev, host, internal_delay); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1248 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, |
| 1249 | internal_delay_phase.final_phase << |
| 1250 | MSDC_PAD_TUNE_CMDRRDLY_S); |
| 1251 | |
| 1252 | skip_internal: |
Fabien Parent | f9ca467 | 2020-10-15 18:38:18 +0200 | [diff] [blame] | 1253 | dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1254 | return final_delay == 0xff ? -EIO : 0; |
| 1255 | } |
| 1256 | |
| 1257 | static int msdc_tune_data(struct udevice *dev, u32 opcode) |
| 1258 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1259 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1260 | struct msdc_host *host = dev_get_priv(dev); |
| 1261 | struct mmc *mmc = &plat->mmc; |
| 1262 | u32 rise_delay = 0, fall_delay = 0; |
| 1263 | struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; |
| 1264 | u8 final_delay, final_maxlen; |
| 1265 | void __iomem *tune_reg = &host->base->pad_tune; |
| 1266 | int cmd_err; |
| 1267 | int i, ret; |
| 1268 | |
| 1269 | if (host->dev_comp->pad_tune0) |
| 1270 | tune_reg = &host->base->pad_tune0; |
| 1271 | |
| 1272 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); |
| 1273 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); |
| 1274 | |
| 1275 | for (i = 0; i < PAD_DELAY_MAX; i++) { |
| 1276 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, |
| 1277 | i << MSDC_PAD_TUNE_DATRRDLY_S); |
| 1278 | |
| 1279 | ret = mmc_send_tuning(mmc, opcode, &cmd_err); |
| 1280 | if (!ret) { |
| 1281 | rise_delay |= (1 << i); |
| 1282 | } else if (cmd_err) { |
| 1283 | /* in this case, retune response is needed */ |
| 1284 | ret = msdc_tune_response(dev, opcode); |
| 1285 | if (ret) |
| 1286 | break; |
| 1287 | } |
| 1288 | } |
| 1289 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1290 | final_rise_delay = get_best_delay(dev, host, rise_delay); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1291 | if (final_rise_delay.maxlen >= 12 || |
| 1292 | (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) |
| 1293 | goto skip_fall; |
| 1294 | |
| 1295 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); |
| 1296 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); |
| 1297 | |
| 1298 | for (i = 0; i < PAD_DELAY_MAX; i++) { |
| 1299 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, |
| 1300 | i << MSDC_PAD_TUNE_DATRRDLY_S); |
| 1301 | |
| 1302 | ret = mmc_send_tuning(mmc, opcode, &cmd_err); |
| 1303 | if (!ret) { |
| 1304 | fall_delay |= (1 << i); |
| 1305 | } else if (cmd_err) { |
| 1306 | /* in this case, retune response is needed */ |
| 1307 | ret = msdc_tune_response(dev, opcode); |
| 1308 | if (ret) |
| 1309 | break; |
| 1310 | } |
| 1311 | } |
| 1312 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1313 | final_fall_delay = get_best_delay(dev, host, fall_delay); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1314 | |
| 1315 | skip_fall: |
| 1316 | final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); |
| 1317 | if (final_maxlen == final_rise_delay.maxlen) { |
| 1318 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); |
| 1319 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); |
| 1320 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, |
| 1321 | final_rise_delay.final_phase << |
| 1322 | MSDC_PAD_TUNE_DATRRDLY_S); |
| 1323 | final_delay = final_rise_delay.final_phase; |
| 1324 | } else { |
| 1325 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); |
| 1326 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); |
| 1327 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, |
| 1328 | final_fall_delay.final_phase << |
| 1329 | MSDC_PAD_TUNE_DATRRDLY_S); |
| 1330 | final_delay = final_fall_delay.final_phase; |
| 1331 | } |
| 1332 | |
| 1333 | if (mmc->selected_mode == MMC_HS_200 || |
| 1334 | mmc->selected_mode == UHS_SDR104) |
| 1335 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M, |
| 1336 | host->hs200_write_int_delay << |
| 1337 | MSDC_PAD_TUNE_DATWRDLY_S); |
| 1338 | |
Fabien Parent | f9ca467 | 2020-10-15 18:38:18 +0200 | [diff] [blame] | 1339 | dev_dbg(dev, "Final data pad delay: %x\n", final_delay); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1340 | |
| 1341 | return final_delay == 0xff ? -EIO : 0; |
| 1342 | } |
| 1343 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1344 | /* |
| 1345 | * MSDC IP which supports data tune + async fifo can do CMD/DAT tune |
| 1346 | * together, which can save the tuning time. |
| 1347 | */ |
| 1348 | static int msdc_tune_together(struct udevice *dev, u32 opcode) |
| 1349 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1350 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1351 | struct msdc_host *host = dev_get_priv(dev); |
| 1352 | struct mmc *mmc = &plat->mmc; |
| 1353 | u32 rise_delay = 0, fall_delay = 0; |
| 1354 | struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; |
| 1355 | u8 final_delay, final_maxlen; |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1356 | int i, ret; |
| 1357 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1358 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); |
| 1359 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); |
| 1360 | |
| 1361 | for (i = 0; i < PAD_DELAY_MAX; i++) { |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1362 | msdc_set_cmd_delay(host, i); |
| 1363 | msdc_set_data_delay(host, i); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1364 | ret = mmc_send_tuning(mmc, opcode, NULL); |
| 1365 | if (!ret) |
| 1366 | rise_delay |= (1 << i); |
| 1367 | } |
| 1368 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1369 | final_rise_delay = get_best_delay(dev, host, rise_delay); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1370 | if (final_rise_delay.maxlen >= 12 || |
| 1371 | (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) |
| 1372 | goto skip_fall; |
| 1373 | |
| 1374 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); |
| 1375 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); |
| 1376 | |
| 1377 | for (i = 0; i < PAD_DELAY_MAX; i++) { |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1378 | msdc_set_cmd_delay(host, i); |
| 1379 | msdc_set_data_delay(host, i); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1380 | ret = mmc_send_tuning(mmc, opcode, NULL); |
| 1381 | if (!ret) |
| 1382 | fall_delay |= (1 << i); |
| 1383 | } |
| 1384 | |
Sean Anderson | 09aa57a | 2020-09-15 10:44:47 -0400 | [diff] [blame] | 1385 | final_fall_delay = get_best_delay(dev, host, fall_delay); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1386 | |
| 1387 | skip_fall: |
| 1388 | final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); |
| 1389 | if (final_maxlen == final_rise_delay.maxlen) { |
| 1390 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); |
| 1391 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1392 | final_delay = final_rise_delay.final_phase; |
| 1393 | } else { |
| 1394 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); |
| 1395 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1396 | final_delay = final_fall_delay.final_phase; |
| 1397 | } |
| 1398 | |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1399 | msdc_set_cmd_delay(host, final_delay); |
| 1400 | msdc_set_data_delay(host, final_delay); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1401 | |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1402 | dev_info(dev, "Final pad delay: %x\n", final_delay); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1403 | return final_delay == 0xff ? -EIO : 0; |
| 1404 | } |
| 1405 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1406 | static int msdc_execute_tuning(struct udevice *dev, uint opcode) |
| 1407 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1408 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1409 | struct msdc_host *host = dev_get_priv(dev); |
| 1410 | struct mmc *mmc = &plat->mmc; |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1411 | int ret = 0; |
| 1412 | |
| 1413 | if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { |
| 1414 | ret = msdc_tune_together(dev, opcode); |
| 1415 | if (ret == -EIO) { |
| 1416 | dev_err(dev, "Tune fail!\n"); |
| 1417 | return ret; |
| 1418 | } |
| 1419 | |
| 1420 | if (mmc->selected_mode == MMC_HS_400) { |
| 1421 | clrbits_le32(&host->base->msdc_iocon, |
| 1422 | MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); |
| 1423 | clrsetbits_le32(&host->base->pad_tune, |
| 1424 | MSDC_PAD_TUNE_DATRRDLY_M, 0); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1425 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1426 | writel(host->hs400_ds_delay, &host->base->pad_ds_tune); |
| 1427 | /* for hs400 mode it must be set to 0 */ |
| 1428 | clrbits_le32(&host->base->patch_bit2, |
| 1429 | MSDC_PB2_CFGCRCSTS); |
| 1430 | host->hs400_mode = true; |
| 1431 | } |
| 1432 | goto tune_done; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1433 | } |
| 1434 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1435 | if (mmc->selected_mode == MMC_HS_400) |
| 1436 | ret = hs400_tune_response(dev, opcode); |
| 1437 | else |
| 1438 | ret = msdc_tune_response(dev, opcode); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1439 | if (ret == -EIO) { |
| 1440 | dev_err(dev, "Tune response fail!\n"); |
| 1441 | return ret; |
| 1442 | } |
| 1443 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1444 | if (mmc->selected_mode != MMC_HS_400) { |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1445 | ret = msdc_tune_data(dev, opcode); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1446 | if (ret == -EIO) { |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1447 | dev_err(dev, "Tune data fail!\n"); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1448 | return ret; |
| 1449 | } |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1450 | } |
| 1451 | |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1452 | tune_done: |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1453 | host->saved_tune_para.iocon = readl(&host->base->msdc_iocon); |
| 1454 | host->saved_tune_para.pad_tune = readl(&host->base->pad_tune); |
developer | 18f9fc7 | 2019-11-07 19:28:42 +0800 | [diff] [blame] | 1455 | host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1456 | |
| 1457 | return ret; |
| 1458 | } |
| 1459 | #endif |
| 1460 | |
| 1461 | static void msdc_init_hw(struct msdc_host *host) |
| 1462 | { |
| 1463 | u32 val; |
| 1464 | void __iomem *tune_reg = &host->base->pad_tune; |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 1465 | void __iomem *rd_dly0_reg = &host->base->pad_tune0; |
| 1466 | void __iomem *rd_dly1_reg = &host->base->pad_tune1; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1467 | |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 1468 | if (host->dev_comp->pad_tune0) { |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1469 | tune_reg = &host->base->pad_tune0; |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 1470 | rd_dly0_reg = &host->base->dat_rd_dly[0]; |
| 1471 | rd_dly1_reg = &host->base->dat_rd_dly[1]; |
| 1472 | } |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1473 | |
| 1474 | /* Configure to MMC/SD mode, clock free running */ |
| 1475 | setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE); |
| 1476 | |
| 1477 | /* Use PIO mode */ |
| 1478 | setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO); |
| 1479 | |
| 1480 | /* Reset */ |
| 1481 | msdc_reset_hw(host); |
| 1482 | |
| 1483 | /* Enable/disable hw card detection according to fdt option */ |
| 1484 | if (host->builtin_cd) |
| 1485 | clrsetbits_le32(&host->base->msdc_ps, |
| 1486 | MSDC_PS_CDDBCE_M, |
| 1487 | (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) | |
| 1488 | MSDC_PS_CDEN); |
| 1489 | else |
| 1490 | clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN); |
| 1491 | |
| 1492 | /* Clear all interrupts */ |
| 1493 | val = readl(&host->base->msdc_int); |
| 1494 | writel(val, &host->base->msdc_int); |
| 1495 | |
| 1496 | /* Enable data & cmd interrupts */ |
| 1497 | writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten); |
| 1498 | |
| 1499 | writel(0, tune_reg); |
| 1500 | writel(0, &host->base->msdc_iocon); |
| 1501 | |
| 1502 | if (host->r_smpl) |
| 1503 | setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); |
| 1504 | else |
| 1505 | clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); |
| 1506 | |
| 1507 | writel(0x403c0046, &host->base->patch_bit0); |
| 1508 | writel(0xffff4089, &host->base->patch_bit1); |
| 1509 | |
| 1510 | if (host->dev_comp->stop_clk_fix) |
| 1511 | clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M, |
| 1512 | 3 << MSDC_PB1_STOP_DLY_S); |
| 1513 | |
| 1514 | if (host->dev_comp->busy_check) |
| 1515 | clrbits_le32(&host->base->patch_bit1, (1 << 7)); |
| 1516 | |
| 1517 | setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL); |
| 1518 | |
| 1519 | if (host->dev_comp->async_fifo) { |
| 1520 | clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M, |
| 1521 | 3 << MSDC_PB2_RESPWAIT_S); |
| 1522 | |
| 1523 | if (host->dev_comp->enhance_rx) { |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1524 | if (host->top_base) |
| 1525 | setbits_le32(&host->top_base->emmc_top_control, |
| 1526 | SDC_RX_ENH_EN); |
| 1527 | else |
| 1528 | setbits_le32(&host->base->sdc_adv_cfg0, |
| 1529 | SDC_RX_ENHANCE_EN); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1530 | } else { |
| 1531 | clrsetbits_le32(&host->base->patch_bit2, |
| 1532 | MSDC_PB2_RESPSTSENSEL_M, |
| 1533 | 2 << MSDC_PB2_RESPSTSENSEL_S); |
| 1534 | clrsetbits_le32(&host->base->patch_bit2, |
| 1535 | MSDC_PB2_CRCSTSENSEL_M, |
| 1536 | 2 << MSDC_PB2_CRCSTSENSEL_S); |
| 1537 | } |
| 1538 | |
| 1539 | /* use async fifo to avoid tune internal delay */ |
| 1540 | clrbits_le32(&host->base->patch_bit2, |
| 1541 | MSDC_PB2_CFGRESP); |
| 1542 | clrbits_le32(&host->base->patch_bit2, |
| 1543 | MSDC_PB2_CFGCRCSTS); |
| 1544 | } |
| 1545 | |
| 1546 | if (host->dev_comp->data_tune) { |
| 1547 | setbits_le32(tune_reg, |
| 1548 | MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); |
| 1549 | clrsetbits_le32(&host->base->patch_bit0, |
| 1550 | MSDC_INT_DAT_LATCH_CK_SEL_M, |
| 1551 | host->latch_ck << |
| 1552 | MSDC_INT_DAT_LATCH_CK_SEL_S); |
| 1553 | } else { |
| 1554 | /* choose clock tune */ |
| 1555 | setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL); |
| 1556 | } |
| 1557 | |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 1558 | if (host->dev_comp->builtin_pad_ctrl) { |
| 1559 | /* Set pins driving strength */ |
| 1560 | writel(MSDC_PAD_CTRL0_CLKPD | MSDC_PAD_CTRL0_CLKSMT | |
| 1561 | MSDC_PAD_CTRL0_CLKIES | (4 << MSDC_PAD_CTRL0_CLKDRVN_S) | |
| 1562 | (4 << MSDC_PAD_CTRL0_CLKDRVP_S), &host->base->pad_ctrl0); |
| 1563 | writel(MSDC_PAD_CTRL1_CMDPU | MSDC_PAD_CTRL1_CMDSMT | |
| 1564 | MSDC_PAD_CTRL1_CMDIES | (4 << MSDC_PAD_CTRL1_CMDDRVN_S) | |
| 1565 | (4 << MSDC_PAD_CTRL1_CMDDRVP_S), &host->base->pad_ctrl1); |
| 1566 | writel(MSDC_PAD_CTRL2_DATPU | MSDC_PAD_CTRL2_DATSMT | |
| 1567 | MSDC_PAD_CTRL2_DATIES | (4 << MSDC_PAD_CTRL2_DATDRVN_S) | |
| 1568 | (4 << MSDC_PAD_CTRL2_DATDRVP_S), &host->base->pad_ctrl2); |
| 1569 | } |
| 1570 | |
| 1571 | if (host->dev_comp->default_pad_dly) { |
| 1572 | /* Default pad delay may be needed if tuning not enabled */ |
| 1573 | clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CLKTDLY_M | |
| 1574 | MSDC_PAD_TUNE_CMDRRDLY_M | |
| 1575 | MSDC_PAD_TUNE_CMDRDLY_M | |
| 1576 | MSDC_PAD_TUNE_DATRRDLY_M | |
| 1577 | MSDC_PAD_TUNE_DATWRDLY_M, |
| 1578 | (0x10 << MSDC_PAD_TUNE_CLKTDLY_S) | |
| 1579 | (0x10 << MSDC_PAD_TUNE_CMDRRDLY_S) | |
| 1580 | (0x10 << MSDC_PAD_TUNE_CMDRDLY_S) | |
| 1581 | (0x10 << MSDC_PAD_TUNE_DATRRDLY_S) | |
| 1582 | (0x10 << MSDC_PAD_TUNE_DATWRDLY_S)); |
| 1583 | |
| 1584 | writel((0x10 << MSDC_PAD_TUNE0_DAT0RDDLY_S) | |
| 1585 | (0x10 << MSDC_PAD_TUNE0_DAT1RDDLY_S) | |
| 1586 | (0x10 << MSDC_PAD_TUNE0_DAT2RDDLY_S) | |
| 1587 | (0x10 << MSDC_PAD_TUNE0_DAT3RDDLY_S), |
| 1588 | rd_dly0_reg); |
| 1589 | |
| 1590 | writel((0x10 << MSDC_PAD_TUNE1_DAT4RDDLY_S) | |
| 1591 | (0x10 << MSDC_PAD_TUNE1_DAT5RDDLY_S) | |
| 1592 | (0x10 << MSDC_PAD_TUNE1_DAT6RDDLY_S) | |
| 1593 | (0x10 << MSDC_PAD_TUNE1_DAT7RDDLY_S), |
| 1594 | rd_dly1_reg); |
| 1595 | } |
| 1596 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1597 | /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */ |
| 1598 | setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO); |
| 1599 | |
| 1600 | /* disable detecting SDIO device interrupt function */ |
| 1601 | clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE); |
| 1602 | |
| 1603 | /* Configure to default data timeout */ |
| 1604 | clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, |
| 1605 | 3 << SDC_CFG_DTOC_S); |
| 1606 | |
| 1607 | if (host->dev_comp->stop_clk_fix) { |
| 1608 | clrbits_le32(&host->base->sdc_fifo_cfg, |
| 1609 | SDC_FIFO_CFG_WRVALIDSEL); |
| 1610 | clrbits_le32(&host->base->sdc_fifo_cfg, |
| 1611 | SDC_FIFO_CFG_RDVALIDSEL); |
| 1612 | } |
| 1613 | |
| 1614 | host->def_tune_para.iocon = readl(&host->base->msdc_iocon); |
| 1615 | host->def_tune_para.pad_tune = readl(&host->base->pad_tune); |
| 1616 | } |
| 1617 | |
| 1618 | static void msdc_ungate_clock(struct msdc_host *host) |
| 1619 | { |
| 1620 | clk_enable(&host->src_clk); |
| 1621 | clk_enable(&host->h_clk); |
Fabien Parent | 297fa1a | 2019-03-24 16:46:32 +0100 | [diff] [blame] | 1622 | if (host->src_clk_cg.dev) |
| 1623 | clk_enable(&host->src_clk_cg); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1624 | } |
| 1625 | |
| 1626 | static int msdc_drv_probe(struct udevice *dev) |
| 1627 | { |
| 1628 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1629 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1630 | struct msdc_host *host = dev_get_priv(dev); |
| 1631 | struct mmc_config *cfg = &plat->cfg; |
| 1632 | |
| 1633 | cfg->name = dev->name; |
| 1634 | |
| 1635 | host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev); |
| 1636 | |
| 1637 | host->src_clk_freq = clk_get_rate(&host->src_clk); |
| 1638 | |
| 1639 | if (host->dev_comp->clk_div_bits == 8) |
| 1640 | cfg->f_min = host->src_clk_freq / (4 * 255); |
| 1641 | else |
| 1642 | cfg->f_min = host->src_clk_freq / (4 * 4095); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1643 | |
developer | 13b920a | 2021-04-20 16:37:10 +0800 | [diff] [blame] | 1644 | if (cfg->f_min < MIN_BUS_CLK) |
| 1645 | cfg->f_min = MIN_BUS_CLK; |
| 1646 | |
Daniel Golle | 1bbd66a | 2021-03-15 15:31:11 +0000 | [diff] [blame] | 1647 | if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq) |
| 1648 | cfg->f_max = host->src_clk_freq; |
developer | dc462a8 | 2020-11-12 16:37:07 +0800 | [diff] [blame] | 1649 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1650 | cfg->b_max = 1024; |
| 1651 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
| 1652 | |
| 1653 | host->mmc = &plat->mmc; |
| 1654 | host->timeout_ns = 100000000; |
developer | c731074 | 2020-11-12 16:36:57 +0800 | [diff] [blame] | 1655 | host->timeout_clks = 3 * (1 << SCLK_CYCLES_SHIFT); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1656 | |
| 1657 | #ifdef CONFIG_PINCTRL |
| 1658 | pinctrl_select_state(dev, "default"); |
| 1659 | #endif |
| 1660 | |
| 1661 | msdc_ungate_clock(host); |
| 1662 | msdc_init_hw(host); |
| 1663 | |
| 1664 | upriv->mmc = &plat->mmc; |
| 1665 | |
| 1666 | return 0; |
| 1667 | } |
| 1668 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 1669 | static int msdc_of_to_plat(struct udevice *dev) |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1670 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1671 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1672 | struct msdc_host *host = dev_get_priv(dev); |
| 1673 | struct mmc_config *cfg = &plat->cfg; |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1674 | fdt_addr_t base, top_base; |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1675 | int ret; |
| 1676 | |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1677 | base = dev_read_addr(dev); |
| 1678 | if (base == FDT_ADDR_T_NONE) |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1679 | return -EINVAL; |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1680 | host->base = map_sysmem(base, 0); |
| 1681 | |
| 1682 | top_base = dev_read_addr_index(dev, 1); |
| 1683 | if (top_base == FDT_ADDR_T_NONE) |
| 1684 | host->top_base = NULL; |
| 1685 | else |
| 1686 | host->top_base = map_sysmem(top_base, 0); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1687 | |
| 1688 | ret = mmc_of_parse(dev, cfg); |
| 1689 | if (ret) |
| 1690 | return ret; |
| 1691 | |
| 1692 | ret = clk_get_by_name(dev, "source", &host->src_clk); |
| 1693 | if (ret < 0) |
| 1694 | return ret; |
| 1695 | |
| 1696 | ret = clk_get_by_name(dev, "hclk", &host->h_clk); |
| 1697 | if (ret < 0) |
| 1698 | return ret; |
| 1699 | |
Fabien Parent | 297fa1a | 2019-03-24 16:46:32 +0100 | [diff] [blame] | 1700 | clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */ |
| 1701 | |
Fabien Parent | 8ed608a | 2019-03-24 16:46:34 +0100 | [diff] [blame] | 1702 | #if CONFIG_IS_ENABLED(DM_GPIO) |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1703 | gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN); |
| 1704 | gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN); |
| 1705 | #endif |
| 1706 | |
| 1707 | host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0); |
| 1708 | host->hs200_cmd_int_delay = |
| 1709 | dev_read_u32_default(dev, "cmd_int_delay", 0); |
| 1710 | host->hs200_write_int_delay = |
| 1711 | dev_read_u32_default(dev, "write_int_delay", 0); |
| 1712 | host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0); |
| 1713 | host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0); |
| 1714 | host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0); |
developer | 399e4af | 2019-09-25 17:45:38 +0800 | [diff] [blame] | 1715 | host->cd_active_high = dev_read_bool(dev, "cd-active-high"); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1716 | |
| 1717 | return 0; |
| 1718 | } |
| 1719 | |
| 1720 | static int msdc_drv_bind(struct udevice *dev) |
| 1721 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1722 | struct msdc_plat *plat = dev_get_plat(dev); |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1723 | |
| 1724 | return mmc_bind(dev, &plat->mmc, &plat->cfg); |
| 1725 | } |
| 1726 | |
Julien Masson | ff2d8bc | 2021-11-05 14:34:14 +0100 | [diff] [blame] | 1727 | static int msdc_ops_wait_dat0(struct udevice *dev, int state, int timeout_us) |
| 1728 | { |
| 1729 | struct msdc_host *host = dev_get_priv(dev); |
| 1730 | int ret; |
| 1731 | u32 reg; |
| 1732 | |
| 1733 | ret = readl_poll_sleep_timeout(&host->base->msdc_ps, reg, |
| 1734 | !!(reg & MSDC_PS_DAT0) == !!state, |
| 1735 | 1000, /* 1 ms */ |
| 1736 | timeout_us); |
| 1737 | |
| 1738 | return ret; |
| 1739 | } |
| 1740 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1741 | static const struct dm_mmc_ops msdc_ops = { |
| 1742 | .send_cmd = msdc_ops_send_cmd, |
| 1743 | .set_ios = msdc_ops_set_ios, |
| 1744 | .get_cd = msdc_ops_get_cd, |
| 1745 | .get_wp = msdc_ops_get_wp, |
| 1746 | #ifdef MMC_SUPPORTS_TUNING |
| 1747 | .execute_tuning = msdc_execute_tuning, |
| 1748 | #endif |
Julien Masson | ff2d8bc | 2021-11-05 14:34:14 +0100 | [diff] [blame] | 1749 | .wait_dat0 = msdc_ops_wait_dat0, |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1750 | }; |
| 1751 | |
developer | 607faf7 | 2019-09-25 17:45:37 +0800 | [diff] [blame] | 1752 | static const struct msdc_compatible mt7620_compat = { |
| 1753 | .clk_div_bits = 8, |
developer | 607faf7 | 2019-09-25 17:45:37 +0800 | [diff] [blame] | 1754 | .pad_tune0 = false, |
| 1755 | .async_fifo = false, |
| 1756 | .data_tune = false, |
| 1757 | .busy_check = false, |
| 1758 | .stop_clk_fix = false, |
developer | 7295c89 | 2020-11-12 16:37:02 +0800 | [diff] [blame] | 1759 | .enhance_rx = false, |
| 1760 | .builtin_pad_ctrl = true, |
| 1761 | .default_pad_dly = true, |
developer | 607faf7 | 2019-09-25 17:45:37 +0800 | [diff] [blame] | 1762 | }; |
| 1763 | |
developer | 5614824 | 2022-05-20 11:23:26 +0800 | [diff] [blame] | 1764 | static const struct msdc_compatible mt7621_compat = { |
| 1765 | .clk_div_bits = 8, |
| 1766 | .pad_tune0 = false, |
| 1767 | .async_fifo = true, |
| 1768 | .data_tune = true, |
| 1769 | .busy_check = false, |
| 1770 | .stop_clk_fix = false, |
| 1771 | .enhance_rx = false, |
| 1772 | .builtin_pad_ctrl = true, |
| 1773 | .default_pad_dly = true, |
| 1774 | }; |
| 1775 | |
developer | 837d334 | 2020-01-10 16:30:32 +0800 | [diff] [blame] | 1776 | static const struct msdc_compatible mt7622_compat = { |
| 1777 | .clk_div_bits = 12, |
| 1778 | .pad_tune0 = true, |
| 1779 | .async_fifo = true, |
| 1780 | .data_tune = true, |
| 1781 | .busy_check = true, |
| 1782 | .stop_clk_fix = true, |
| 1783 | }; |
| 1784 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1785 | static const struct msdc_compatible mt7623_compat = { |
| 1786 | .clk_div_bits = 12, |
| 1787 | .pad_tune0 = true, |
| 1788 | .async_fifo = true, |
| 1789 | .data_tune = true, |
| 1790 | .busy_check = false, |
| 1791 | .stop_clk_fix = false, |
| 1792 | .enhance_rx = false |
| 1793 | }; |
| 1794 | |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1795 | static const struct msdc_compatible mt8512_compat = { |
| 1796 | .clk_div_bits = 12, |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1797 | .pad_tune0 = true, |
| 1798 | .async_fifo = true, |
| 1799 | .data_tune = true, |
| 1800 | .busy_check = true, |
| 1801 | .stop_clk_fix = true, |
| 1802 | }; |
| 1803 | |
Fabien Parent | 1d520a4 | 2019-03-24 16:46:33 +0100 | [diff] [blame] | 1804 | static const struct msdc_compatible mt8516_compat = { |
| 1805 | .clk_div_bits = 12, |
| 1806 | .pad_tune0 = true, |
| 1807 | .async_fifo = true, |
| 1808 | .data_tune = true, |
| 1809 | .busy_check = true, |
| 1810 | .stop_clk_fix = true, |
| 1811 | }; |
| 1812 | |
Fabien Parent | c7da698 | 2019-08-12 20:26:58 +0200 | [diff] [blame] | 1813 | static const struct msdc_compatible mt8183_compat = { |
| 1814 | .clk_div_bits = 12, |
| 1815 | .pad_tune0 = true, |
| 1816 | .async_fifo = true, |
| 1817 | .data_tune = true, |
| 1818 | .busy_check = true, |
| 1819 | .stop_clk_fix = true, |
| 1820 | }; |
| 1821 | |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1822 | static const struct udevice_id msdc_ids[] = { |
developer | 607faf7 | 2019-09-25 17:45:37 +0800 | [diff] [blame] | 1823 | { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat }, |
developer | 5614824 | 2022-05-20 11:23:26 +0800 | [diff] [blame] | 1824 | { .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat }, |
developer | 837d334 | 2020-01-10 16:30:32 +0800 | [diff] [blame] | 1825 | { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat }, |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1826 | { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, |
developer | a2d3a6c | 2019-12-31 11:29:24 +0800 | [diff] [blame] | 1827 | { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, |
Fabien Parent | 1d520a4 | 2019-03-24 16:46:33 +0100 | [diff] [blame] | 1828 | { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, |
Fabien Parent | c7da698 | 2019-08-12 20:26:58 +0200 | [diff] [blame] | 1829 | { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat }, |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1830 | {} |
| 1831 | }; |
| 1832 | |
| 1833 | U_BOOT_DRIVER(mtk_sd_drv) = { |
| 1834 | .name = "mtk_sd", |
| 1835 | .id = UCLASS_MMC, |
| 1836 | .of_match = msdc_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 1837 | .of_to_plat = msdc_of_to_plat, |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1838 | .bind = msdc_drv_bind, |
| 1839 | .probe = msdc_drv_probe, |
| 1840 | .ops = &msdc_ops, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 1841 | .plat_auto = sizeof(struct msdc_plat), |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 1842 | .priv_auto = sizeof(struct msdc_host), |
developer | dc5a9aa | 2018-11-15 10:08:04 +0800 | [diff] [blame] | 1843 | }; |