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git01.mediatek.com / filogic / uboot / 5db5b68efc9cdb11ce469e756c18c4f3557c5133 / . / arch / arm / dts / exynos850.dtsi
blob: 53104e65b9c67024e23468713d3a8da8341d7bc5 [file] [log] [blame]
Sam Protsenko4d718732024-01-10 21:09:07 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos850 SoC device tree source
4 *
5 * Copyright (C) 2018 Samsung Electronics Co., Ltd.
6 * Copyright (C) 2021 Linaro Ltd.
7 *
8 * Samsung Exynos850 SoC device nodes are listed in this file.
9 * Exynos850 based board files can include this file and provide
10 * values for board specific bindings.
11 */
12
13#include <dt-bindings/clock/exynos850.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/soc/samsung,exynos-usi.h>
16
17/ {
18 /* Also known under engineering name Exynos3830 */
19 compatible = "samsung,exynos850";
20 #address-cells = <2>;
21 #size-cells = <1>;
22
23 interrupt-parent = <&gic>;
24
25 aliases {
26 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_cmgp;
28 pinctrl2 = &pinctrl_aud;
29 pinctrl3 = &pinctrl_hsi;
30 pinctrl4 = &pinctrl_core;
31 pinctrl5 = &pinctrl_peri;
32 };
33
34 arm-pmu {
35 compatible = "arm,cortex-a55-pmu";
36 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
45 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
46 };
47
48 /* Main system clock (XTCXO); external, must be 26 MHz */
49 oscclk: clock-oscclk {
50 compatible = "fixed-clock";
51 clock-output-names = "oscclk";
52 #clock-cells = <0>;
53 };
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 cpu-map {
60 cluster0 {
61 core0 {
62 cpu = <&cpu0>;
63 };
64 core1 {
65 cpu = <&cpu1>;
66 };
67 core2 {
68 cpu = <&cpu2>;
69 };
70 core3 {
71 cpu = <&cpu3>;
72 };
73 };
74
75 cluster1 {
76 core0 {
77 cpu = <&cpu4>;
78 };
79 core1 {
80 cpu = <&cpu5>;
81 };
82 core2 {
83 cpu = <&cpu6>;
84 };
85 core3 {
86 cpu = <&cpu7>;
87 };
88 };
89 };
90
91 cpu0: cpu@0 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a55";
94 reg = <0x0>;
95 enable-method = "psci";
96 };
97 cpu1: cpu@1 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a55";
100 reg = <0x1>;
101 enable-method = "psci";
102 };
103 cpu2: cpu@2 {
104 device_type = "cpu";
105 compatible = "arm,cortex-a55";
106 reg = <0x2>;
107 enable-method = "psci";
108 };
109 cpu3: cpu@3 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a55";
112 reg = <0x3>;
113 enable-method = "psci";
114 };
115 cpu4: cpu@100 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a55";
118 reg = <0x100>;
119 enable-method = "psci";
120 };
121 cpu5: cpu@101 {
122 device_type = "cpu";
123 compatible = "arm,cortex-a55";
124 reg = <0x101>;
125 enable-method = "psci";
126 };
127 cpu6: cpu@102 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a55";
130 reg = <0x102>;
131 enable-method = "psci";
132 };
133 cpu7: cpu@103 {
134 device_type = "cpu";
135 compatible = "arm,cortex-a55";
136 reg = <0x103>;
137 enable-method = "psci";
138 };
139 };
140
141 psci {
142 compatible = "arm,psci-1.0";
143 method = "smc";
144 };
145
146 timer {
147 compatible = "arm,armv8-timer";
148 /* Hypervisor Virtual Timer interrupt is not wired to GIC */
149 interrupts =
150 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
154 };
155
156 soc: soc@0 {
157 compatible = "simple-bus";
158 #address-cells = <1>;
159 #size-cells = <1>;
160 ranges = <0x0 0x0 0x0 0x20000000>;
161
162 chipid@10000000 {
163 compatible = "samsung,exynos850-chipid";
164 reg = <0x10000000 0x100>;
165 };
166
167 timer@10040000 {
168 compatible = "samsung,exynos850-mct",
169 "samsung,exynos4210-mct";
170 reg = <0x10040000 0x800>;
171 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
184 clock-names = "fin_pll", "mct";
185 };
186
187 gic: interrupt-controller@12a01000 {
188 compatible = "arm,gic-400";
189 #interrupt-cells = <3>;
190 #address-cells = <0>;
191 reg = <0x12a01000 0x1000>,
192 <0x12a02000 0x2000>,
193 <0x12a04000 0x2000>,
194 <0x12a06000 0x2000>;
195 interrupt-controller;
196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
197 IRQ_TYPE_LEVEL_HIGH)>;
198 };
199
200 pmu_system_controller: system-controller@11860000 {
201 compatible = "samsung,exynos850-pmu", "syscon";
202 reg = <0x11860000 0x10000>;
203
204 reboot: syscon-reboot {
205 compatible = "syscon-reboot";
206 regmap = <&pmu_system_controller>;
207 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
208 mask = <0x2>; /* SWRESET_SYSTEM */
209 value = <0x2>; /* reset value */
210 };
211 };
212
213 watchdog_cl0: watchdog@10050000 {
214 compatible = "samsung,exynos850-wdt";
215 reg = <0x10050000 0x100>;
216 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
218 clock-names = "watchdog", "watchdog_src";
219 samsung,syscon-phandle = <&pmu_system_controller>;
220 samsung,cluster-index = <0>;
221 status = "disabled";
222 };
223
224 watchdog_cl1: watchdog@10060000 {
225 compatible = "samsung,exynos850-wdt";
226 reg = <0x10060000 0x100>;
227 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
229 clock-names = "watchdog", "watchdog_src";
230 samsung,syscon-phandle = <&pmu_system_controller>;
231 samsung,cluster-index = <1>;
232 status = "disabled";
233 };
234
235 cmu_peri: clock-controller@10030000 {
236 compatible = "samsung,exynos850-cmu-peri";
237 reg = <0x10030000 0x8000>;
238 #clock-cells = <1>;
239
240 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
241 <&cmu_top CLK_DOUT_PERI_UART>,
242 <&cmu_top CLK_DOUT_PERI_IP>;
243 clock-names = "oscclk", "dout_peri_bus",
244 "dout_peri_uart", "dout_peri_ip";
245 };
246
247 cmu_g3d: clock-controller@11400000 {
248 compatible = "samsung,exynos850-cmu-g3d";
249 reg = <0x11400000 0x8000>;
250 #clock-cells = <1>;
251
252 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
253 clock-names = "oscclk", "dout_g3d_switch";
254 };
255
256 cmu_apm: clock-controller@11800000 {
257 compatible = "samsung,exynos850-cmu-apm";
258 reg = <0x11800000 0x8000>;
259 #clock-cells = <1>;
260
261 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
262 clock-names = "oscclk", "dout_clkcmu_apm_bus";
263 };
264
265 cmu_cmgp: clock-controller@11c00000 {
266 compatible = "samsung,exynos850-cmu-cmgp";
267 reg = <0x11c00000 0x8000>;
268 #clock-cells = <1>;
269
270 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
271 clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
272 };
273
274 cmu_core: clock-controller@12000000 {
275 compatible = "samsung,exynos850-cmu-core";
276 reg = <0x12000000 0x8000>;
277 #clock-cells = <1>;
278
279 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
280 <&cmu_top CLK_DOUT_CORE_CCI>,
281 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
282 <&cmu_top CLK_DOUT_CORE_SSS>;
283 clock-names = "oscclk", "dout_core_bus",
284 "dout_core_cci", "dout_core_mmc_embd",
285 "dout_core_sss";
286 };
287
288 cmu_top: clock-controller@120e0000 {
289 compatible = "samsung,exynos850-cmu-top";
290 reg = <0x120e0000 0x8000>;
291 #clock-cells = <1>;
292
293 clocks = <&oscclk>;
294 clock-names = "oscclk";
295 };
296
297 cmu_mfcmscl: clock-controller@12c00000 {
298 compatible = "samsung,exynos850-cmu-mfcmscl";
299 reg = <0x12c00000 0x8000>;
300 #clock-cells = <1>;
301
302 clocks = <&oscclk>,
303 <&cmu_top CLK_DOUT_MFCMSCL_MFC>,
304 <&cmu_top CLK_DOUT_MFCMSCL_M2M>,
305 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
306 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
307 clock-names = "oscclk", "dout_mfcmscl_mfc",
308 "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
309 "dout_mfcmscl_jpeg";
310 };
311
312 cmu_dpu: clock-controller@13000000 {
313 compatible = "samsung,exynos850-cmu-dpu";
314 reg = <0x13000000 0x8000>;
315 #clock-cells = <1>;
316
317 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
318 clock-names = "oscclk", "dout_dpu";
319 };
320
321 cmu_hsi: clock-controller@13400000 {
322 compatible = "samsung,exynos850-cmu-hsi";
323 reg = <0x13400000 0x8000>;
324 #clock-cells = <1>;
325
326 clocks = <&oscclk>,
327 <&cmu_top CLK_DOUT_HSI_BUS>,
328 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
329 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
330 clock-names = "oscclk", "dout_hsi_bus",
331 "dout_hsi_mmc_card", "dout_hsi_usb20drd";
332 };
333
334 cmu_is: clock-controller@14500000 {
335 compatible = "samsung,exynos850-cmu-is";
336 reg = <0x14500000 0x8000>;
337 #clock-cells = <1>;
338
339 clocks = <&oscclk>,
340 <&cmu_top CLK_DOUT_IS_BUS>,
341 <&cmu_top CLK_DOUT_IS_ITP>,
342 <&cmu_top CLK_DOUT_IS_VRA>,
343 <&cmu_top CLK_DOUT_IS_GDC>;
344 clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
345 "dout_is_vra", "dout_is_gdc";
346 };
347
348 cmu_aud: clock-controller@14a00000 {
349 compatible = "samsung,exynos850-cmu-aud";
350 reg = <0x14a00000 0x8000>;
351 #clock-cells = <1>;
352
353 clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
354 clock-names = "oscclk", "dout_aud";
355 };
356
357 pinctrl_alive: pinctrl@11850000 {
358 compatible = "samsung,exynos850-pinctrl";
359 reg = <0x11850000 0x1000>;
360
361 wakeup-interrupt-controller {
362 compatible = "samsung,exynos850-wakeup-eint";
363 };
364 };
365
366 pinctrl_cmgp: pinctrl@11c30000 {
367 compatible = "samsung,exynos850-pinctrl";
368 reg = <0x11c30000 0x1000>;
369
370 wakeup-interrupt-controller {
371 compatible = "samsung,exynos850-wakeup-eint";
372 };
373 };
374
375 pinctrl_core: pinctrl@12070000 {
376 compatible = "samsung,exynos850-pinctrl";
377 reg = <0x12070000 0x1000>;
378 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
379 };
380
381 pinctrl_hsi: pinctrl@13430000 {
382 compatible = "samsung,exynos850-pinctrl";
383 reg = <0x13430000 0x1000>;
384 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
385 };
386
387 pinctrl_peri: pinctrl@139b0000 {
388 compatible = "samsung,exynos850-pinctrl";
389 reg = <0x139b0000 0x1000>;
390 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
391 };
392
393 pinctrl_aud: pinctrl@14a60000 {
394 compatible = "samsung,exynos850-pinctrl";
395 reg = <0x14a60000 0x1000>;
396 };
397
398 rtc: rtc@11a30000 {
399 compatible = "samsung,s3c6410-rtc";
400 reg = <0x11a30000 0x100>;
401 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
404 clock-names = "rtc";
405 status = "disabled";
406 };
407
408 mmc_0: mmc@12100000 {
409 compatible = "samsung,exynos7-dw-mshc-smu";
410 reg = <0x12100000 0x2000>;
411 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
415 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
416 clock-names = "biu", "ciu";
417 fifo-depth = <0x40>;
418 status = "disabled";
419 };
420
421 i2c_0: i2c@13830000 {
422 compatible = "samsung,s3c2440-i2c";
423 reg = <0x13830000 0x100>;
424 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2c0_pins>;
429 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
430 clock-names = "i2c";
431 status = "disabled";
432 };
433
434 i2c_1: i2c@13840000 {
435 compatible = "samsung,s3c2440-i2c";
436 reg = <0x13840000 0x100>;
437 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
439 #size-cells = <0>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2c1_pins>;
442 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
443 clock-names = "i2c";
444 status = "disabled";
445 };
446
447 i2c_2: i2c@13850000 {
448 compatible = "samsung,s3c2440-i2c";
449 reg = <0x13850000 0x100>;
450 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
451 #address-cells = <1>;
452 #size-cells = <0>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&i2c2_pins>;
455 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
456 clock-names = "i2c";
457 status = "disabled";
458 };
459
460 i2c_3: i2c@13860000 {
461 compatible = "samsung,s3c2440-i2c";
462 reg = <0x13860000 0x100>;
463 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2c3_pins>;
468 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
469 clock-names = "i2c";
470 status = "disabled";
471 };
472
473 i2c_4: i2c@13870000 {
474 compatible = "samsung,s3c2440-i2c";
475 reg = <0x13870000 0x100>;
476 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&i2c4_pins>;
481 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
482 clock-names = "i2c";
483 status = "disabled";
484 };
485
486 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */
487 i2c_5: i2c@13880000 {
488 compatible = "samsung,s3c2440-i2c";
489 reg = <0x13880000 0x100>;
490 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
492 #size-cells = <0>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&i2c5_pins>;
495 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
496 clock-names = "i2c";
497 status = "disabled";
498 };
499
500 /* I2C_6 (also called MOTOR_I2C in TRM) */
501 i2c_6: i2c@13890000 {
502 compatible = "samsung,s3c2440-i2c";
503 reg = <0x13890000 0x100>;
504 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c6_pins>;
509 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
510 clock-names = "i2c";
511 status = "disabled";
512 };
513
514 sysmmu_mfcmscl: sysmmu@12c50000 {
515 compatible = "samsung,exynos-sysmmu";
516 reg = <0x12c50000 0x9000>;
517 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
518 clock-names = "sysmmu";
519 clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
520 #iommu-cells = <0>;
521 };
522
523 sysmmu_dpu: sysmmu@130c0000 {
524 compatible = "samsung,exynos-sysmmu";
525 reg = <0x130c0000 0x9000>;
526 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
527 clock-names = "sysmmu";
528 clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
529 #iommu-cells = <0>;
530 };
531
532 sysmmu_is0: sysmmu@14550000 {
533 compatible = "samsung,exynos-sysmmu";
534 reg = <0x14550000 0x9000>;
535 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
536 clock-names = "sysmmu";
537 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
538 #iommu-cells = <0>;
539 };
540
541 sysmmu_is1: sysmmu@14570000 {
542 compatible = "samsung,exynos-sysmmu";
543 reg = <0x14570000 0x9000>;
544 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
545 clock-names = "sysmmu";
546 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
547 #iommu-cells = <0>;
548 };
549
550 sysmmu_aud: sysmmu@14850000 {
551 compatible = "samsung,exynos-sysmmu";
552 reg = <0x14850000 0x9000>;
553 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
554 clock-names = "sysmmu";
555 clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
556 #iommu-cells = <0>;
557 };
558
559 sysreg_peri: syscon@10020000 {
560 compatible = "samsung,exynos850-peri-sysreg",
561 "samsung,exynos850-sysreg", "syscon";
562 reg = <0x10020000 0x10000>;
563 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
564 };
565
566 sysreg_cmgp: syscon@11c20000 {
567 compatible = "samsung,exynos850-cmgp-sysreg",
568 "samsung,exynos850-sysreg", "syscon";
569 reg = <0x11c20000 0x10000>;
570 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
571 };
572
573 usbdrd: usb@13600000 {
574 compatible = "samsung,exynos850-dwusb3";
575 ranges = <0x0 0x13600000 0x10000>;
576 clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
577 <&cmu_hsi CLK_GOUT_USB_REF_CLK>;
578 clock-names = "bus_early", "ref";
579 #address-cells = <1>;
580 #size-cells = <1>;
581 status = "disabled";
582
583 usbdrd_dwc3: usb@0 {
584 compatible = "snps,dwc3";
585 reg = <0x0 0x10000>;
586 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
587 phys = <&usbdrd_phy 0>;
588 phy-names = "usb2-phy";
589 };
590 };
591
592 usbdrd_phy: phy@135d0000 {
593 compatible = "samsung,exynos850-usbdrd-phy";
594 reg = <0x135d0000 0x100>;
595 clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
596 <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
597 clock-names = "phy", "ref";
598 samsung,pmu-syscon = <&pmu_system_controller>;
599 #phy-cells = <1>;
600 status = "disabled";
601 };
602
603 usi_uart: usi@138200c0 {
604 compatible = "samsung,exynos850-usi";
605 reg = <0x138200c0 0x20>;
606 samsung,sysreg = <&sysreg_peri 0x1010>;
607 samsung,mode = <USI_V2_UART>;
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges;
611 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
612 <&cmu_peri CLK_GOUT_UART_IPCLK>;
613 clock-names = "pclk", "ipclk";
614 status = "disabled";
615
616 serial_0: serial@13820000 {
617 compatible = "samsung,exynos850-uart";
618 reg = <0x13820000 0xc0>;
619 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&uart0_pins>;
622 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
623 <&cmu_peri CLK_GOUT_UART_IPCLK>;
624 clock-names = "uart", "clk_uart_baud0";
625 status = "disabled";
626 };
627 };
628
629 usi_hsi2c_0: usi@138a00c0 {
630 compatible = "samsung,exynos850-usi";
631 reg = <0x138a00c0 0x20>;
632 samsung,sysreg = <&sysreg_peri 0x1020>;
633 samsung,mode = <USI_V2_I2C>;
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges;
637 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
638 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
639 clock-names = "pclk", "ipclk";
640 status = "disabled";
641
642 hsi2c_0: i2c@138a0000 {
643 compatible = "samsung,exynosautov9-hsi2c";
644 reg = <0x138a0000 0xc0>;
645 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
646 #address-cells = <1>;
647 #size-cells = <0>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&hsi2c0_pins>;
650 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
651 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
652 clock-names = "hsi2c", "hsi2c_pclk";
653 status = "disabled";
654 };
655 };
656
657 usi_hsi2c_1: usi@138b00c0 {
658 compatible = "samsung,exynos850-usi";
659 reg = <0x138b00c0 0x20>;
660 samsung,sysreg = <&sysreg_peri 0x1030>;
661 samsung,mode = <USI_V2_I2C>;
662 #address-cells = <1>;
663 #size-cells = <1>;
664 ranges;
665 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
666 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
667 clock-names = "pclk", "ipclk";
668 status = "disabled";
669
670 hsi2c_1: i2c@138b0000 {
671 compatible = "samsung,exynosautov9-hsi2c";
672 reg = <0x138b0000 0xc0>;
673 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
674 #address-cells = <1>;
675 #size-cells = <0>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&hsi2c1_pins>;
678 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
679 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
680 clock-names = "hsi2c", "hsi2c_pclk";
681 status = "disabled";
682 };
683 };
684
685 usi_hsi2c_2: usi@138c00c0 {
686 compatible = "samsung,exynos850-usi";
687 reg = <0x138c00c0 0x20>;
688 samsung,sysreg = <&sysreg_peri 0x1040>;
689 samsung,mode = <USI_V2_I2C>;
690 #address-cells = <1>;
691 #size-cells = <1>;
692 ranges;
693 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
694 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
695 clock-names = "pclk", "ipclk";
696 status = "disabled";
697
698 hsi2c_2: i2c@138c0000 {
699 compatible = "samsung,exynosautov9-hsi2c";
700 reg = <0x138c0000 0xc0>;
701 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
702 #address-cells = <1>;
703 #size-cells = <0>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&hsi2c2_pins>;
706 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
707 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
708 clock-names = "hsi2c", "hsi2c_pclk";
709 status = "disabled";
710 };
711 };
712
713 usi_spi_0: usi@139400c0 {
714 compatible = "samsung,exynos850-usi";
715 reg = <0x139400c0 0x20>;
716 samsung,sysreg = <&sysreg_peri 0x1050>;
717 samsung,mode = <USI_V2_SPI>;
718 #address-cells = <1>;
719 #size-cells = <1>;
720 ranges;
721 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
722 <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
723 clock-names = "pclk", "ipclk";
724 status = "disabled";
725 };
726
727 usi_cmgp0: usi@11d000c0 {
728 compatible = "samsung,exynos850-usi";
729 reg = <0x11d000c0 0x20>;
730 samsung,sysreg = <&sysreg_cmgp 0x2000>;
731 samsung,mode = <USI_V2_I2C>;
732 #address-cells = <1>;
733 #size-cells = <1>;
734 ranges;
735 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
736 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
737 clock-names = "pclk", "ipclk";
738 status = "disabled";
739
740 hsi2c_3: i2c@11d00000 {
741 compatible = "samsung,exynosautov9-hsi2c";
742 reg = <0x11d00000 0xc0>;
743 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
744 #address-cells = <1>;
745 #size-cells = <0>;
746 pinctrl-names = "default";
747 pinctrl-0 = <&hsi2c3_pins>;
748 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
749 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
750 clock-names = "hsi2c", "hsi2c_pclk";
751 status = "disabled";
752 };
753
754 serial_1: serial@11d00000 {
755 compatible = "samsung,exynos850-uart";
756 reg = <0x11d00000 0xc0>;
757 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&uart1_single_pins>;
760 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
761 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
762 clock-names = "uart", "clk_uart_baud0";
763 status = "disabled";
764 };
765 };
766
767 usi_cmgp1: usi@11d200c0 {
768 compatible = "samsung,exynos850-usi";
769 reg = <0x11d200c0 0x20>;
770 samsung,sysreg = <&sysreg_cmgp 0x2010>;
771 samsung,mode = <USI_V2_I2C>;
772 #address-cells = <1>;
773 #size-cells = <1>;
774 ranges;
775 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
776 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
777 clock-names = "pclk", "ipclk";
778 status = "disabled";
779
780 hsi2c_4: i2c@11d20000 {
781 compatible = "samsung,exynosautov9-hsi2c";
782 reg = <0x11d20000 0xc0>;
783 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
784 #address-cells = <1>;
785 #size-cells = <0>;
786 pinctrl-names = "default";
787 pinctrl-0 = <&hsi2c4_pins>;
788 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
789 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
790 clock-names = "hsi2c", "hsi2c_pclk";
791 status = "disabled";
792 };
793
794 serial_2: serial@11d20000 {
795 compatible = "samsung,exynos850-uart";
796 reg = <0x11d20000 0xc0>;
797 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
798 pinctrl-names = "default";
799 pinctrl-0 = <&uart2_single_pins>;
800 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
801 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
802 clock-names = "uart", "clk_uart_baud0";
803 status = "disabled";
804 };
805 };
806 };
807};
808
809#include "exynos850-pinctrl.dtsi"