Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009 Wind River Systems, Inc. |
| 3 | * Tom Rix <Tom.Rix@windriver.com> |
| 4 | * |
| 5 | * This is file is based on |
| 6 | * repository git.gitorious.org/u-boot-omap3/mainline.git, |
| 7 | * branch omap3-dev-usb, file drivers/usb/gadget/twl4030_usb.c |
| 8 | * |
| 9 | * This is the unique part of its copyright : |
| 10 | * |
| 11 | * ------------------------------------------------------------------------ |
| 12 | * |
| 13 | * * (C) Copyright 2009 Atin Malaviya (atin.malaviya@gmail.com) |
| 14 | * |
| 15 | * Based on: twl4030_usb.c in linux 2.6 (drivers/i2c/chips/twl4030_usb.c) |
| 16 | * Copyright (C) 2004-2007 Texas Instruments |
| 17 | * Copyright (C) 2008 Nokia Corporation |
| 18 | * Contact: Felipe Balbi <felipe.balbi@nokia.com> |
| 19 | * |
| 20 | * Author: Atin Malaviya (atin.malaviya@gmail.com) |
| 21 | * |
| 22 | * ------------------------------------------------------------------------ |
| 23 | * |
| 24 | * This program is free software; you can redistribute it and/or modify |
| 25 | * it under the terms of the GNU General Public License as published by |
| 26 | * the Free Software Foundation; either version 2 of the License, or |
| 27 | * (at your option) any later version. |
| 28 | * |
| 29 | * This program is distributed in the hope that it will be useful, |
| 30 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 31 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 32 | * GNU General Public License for more details. |
| 33 | * |
| 34 | * You should have received a copy of the GNU General Public License |
| 35 | * along with this program; if not, write to the Free Software |
| 36 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 37 | * MA 02111-1307 USA |
| 38 | */ |
| 39 | |
| 40 | #include <twl4030.h> |
| 41 | |
| 42 | /* Defines for bits in registers */ |
| 43 | #define OPMODE_MASK (3 << 3) |
| 44 | #define XCVRSELECT_MASK (3 << 0) |
| 45 | #define CARKITMODE (1 << 2) |
| 46 | #define OTG_ENAB (1 << 5) |
| 47 | #define PHYPWD (1 << 0) |
| 48 | #define CLOCKGATING_EN (1 << 2) |
| 49 | #define CLK32K_EN (1 << 1) |
| 50 | #define REQ_PHY_DPLL_CLK (1 << 0) |
| 51 | #define PHY_DPLL_CLK (1 << 0) |
| 52 | |
| 53 | static int twl4030_usb_write(u8 address, u8 data) |
| 54 | { |
| 55 | int ret; |
| 56 | |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 57 | ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, address, data); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 58 | if (ret != 0) |
| 59 | printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret); |
| 60 | |
| 61 | return ret; |
| 62 | } |
| 63 | |
| 64 | static int twl4030_usb_read(u8 address) |
| 65 | { |
| 66 | u8 data; |
| 67 | int ret; |
| 68 | |
Nishanth Menon | 5d9d6f7 | 2013-03-26 05:20:50 +0000 | [diff] [blame^] | 69 | ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, address, &data); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 70 | if (ret == 0) |
| 71 | ret = data; |
| 72 | else |
| 73 | printf("TWL4030:USB:Read[0x%x] Error %d\n", address, ret); |
| 74 | |
| 75 | return ret; |
| 76 | } |
| 77 | |
| 78 | static void twl4030_usb_ldo_init(void) |
| 79 | { |
| 80 | /* Enable writing to power configuration registers */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 81 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, |
| 82 | TWL4030_PM_MASTER_PROTECT_KEY, 0xC0); |
| 83 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, |
| 84 | TWL4030_PM_MASTER_PROTECT_KEY, 0x0C); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 85 | |
| 86 | /* put VUSB3V1 LDO in active state */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 87 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, |
| 88 | TWL4030_PM_RECEIVER_VUSB_DEDICATED2, 0x00); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 89 | |
| 90 | /* input to VUSB3V1 LDO is from VBAT, not VBUS */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 91 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, |
| 92 | TWL4030_PM_RECEIVER_VUSB_DEDICATED1, 0x14); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 93 | |
| 94 | /* turn on 3.1V regulator */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 95 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, |
| 96 | TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP, 0x20); |
| 97 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, |
| 98 | TWL4030_PM_RECEIVER_VUSB3V1_TYPE, 0x00); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 99 | |
| 100 | /* turn on 1.5V regulator */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 101 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, |
| 102 | TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP, 0x20); |
| 103 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, |
| 104 | TWL4030_PM_RECEIVER_VUSB1V5_TYPE, 0x00); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 105 | |
| 106 | /* turn on 1.8V regulator */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 107 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, |
| 108 | TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP, 0x20); |
| 109 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, |
| 110 | TWL4030_PM_RECEIVER_VUSB1V8_TYPE, 0x00); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 111 | |
| 112 | /* disable access to power configuration registers */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 113 | twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, |
| 114 | TWL4030_PM_MASTER_PROTECT_KEY, 0x00); |
Tom Rix | 03f4fbb | 2009-10-31 12:37:40 -0500 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | static void twl4030_phy_power(void) |
| 118 | { |
| 119 | u8 pwr, clk; |
| 120 | |
| 121 | /* Power the PHY */ |
| 122 | pwr = twl4030_usb_read(TWL4030_USB_PHY_PWR_CTRL); |
| 123 | pwr &= ~PHYPWD; |
| 124 | twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr); |
| 125 | /* Enable clocks */ |
| 126 | clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); |
| 127 | clk |= CLOCKGATING_EN | CLK32K_EN; |
| 128 | twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * Initiaze the ULPI interface |
| 133 | * ULPI : Universal Transceiver Macrocell Low Pin Interface |
| 134 | * An interface between the USB link controller like musb and the |
| 135 | * the PHY or transceiver that drives the actual bus. |
| 136 | */ |
| 137 | int twl4030_usb_ulpi_init(void) |
| 138 | { |
| 139 | long timeout = 1000 * 1000; /* 1 sec */; |
| 140 | u8 clk, sts, pwr; |
| 141 | |
| 142 | /* twl4030 ldo init */ |
| 143 | twl4030_usb_ldo_init(); |
| 144 | |
| 145 | /* Enable the twl4030 phy */ |
| 146 | twl4030_phy_power(); |
| 147 | |
| 148 | /* Enable DPLL to access PHY registers over I2C */ |
| 149 | clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); |
| 150 | clk |= REQ_PHY_DPLL_CLK; |
| 151 | twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); |
| 152 | |
| 153 | /* Check if the PHY DPLL is locked */ |
| 154 | sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); |
| 155 | while (!(sts & PHY_DPLL_CLK) && 0 < timeout) { |
| 156 | udelay(10); |
| 157 | sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); |
| 158 | timeout -= 10; |
| 159 | } |
| 160 | |
| 161 | /* Final check */ |
| 162 | sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); |
| 163 | if (!(sts & PHY_DPLL_CLK)) { |
| 164 | printf("Error:TWL4030:USB Timeout setting PHY DPLL clock\n"); |
| 165 | return -1; |
| 166 | } |
| 167 | |
| 168 | /* |
| 169 | * There are two circuit blocks attached to the PHY, |
| 170 | * Carkit and USB OTG. Disable Carkit and enable USB OTG |
| 171 | */ |
| 172 | twl4030_usb_write(TWL4030_USB_IFC_CTRL_CLR, CARKITMODE); |
| 173 | pwr = twl4030_usb_read(TWL4030_USB_POWER_CTRL); |
| 174 | pwr |= OTG_ENAB; |
| 175 | twl4030_usb_write(TWL4030_USB_POWER_CTRL_SET, pwr); |
| 176 | |
| 177 | /* Clear the opmode bits to ensure normal encode */ |
| 178 | twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, OPMODE_MASK); |
| 179 | |
| 180 | /* Clear the xcvrselect bits to enable the high speed transeiver */ |
| 181 | twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, XCVRSELECT_MASK); |
| 182 | |
| 183 | /* Let ULPI control the DPLL clock */ |
| 184 | clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); |
| 185 | clk &= ~REQ_PHY_DPLL_CLK; |
| 186 | twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); |
| 187 | |
| 188 | return 0; |
| 189 | } |