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git01.mediatek.com / filogic / uboot / 5d65a071b573e33b15d57fdde33f4778467ba9be / . / dts / upstream / src / arm64 / mediatek / mt8195.dtsi
blob: 5d8b68f86ce44655664c07276e8ae813307cb248 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/gce/mt8195-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8195-memory-port.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15#include <dt-bindings/power/mt8195-power.h>
16#include <dt-bindings/reset/mt8195-resets.h>
17#include <dt-bindings/thermal/thermal.h>
18#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
19
20/ {
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
29 gce0 = &gce0;
30 gce1 = &gce1;
31 ethdr0 = &ethdr0;
32 mutex0 = &mutex;
33 mutex1 = &mutex1;
34 merge1 = &merge1;
35 merge2 = &merge2;
36 merge3 = &merge3;
37 merge4 = &merge4;
38 merge5 = &merge5;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a55";
56 reg = <0x000>;
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
70 };
71
72 cpu1: cpu@100 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
75 reg = <0x100>;
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
89 };
90
91 cpu2: cpu@200 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a55";
94 reg = <0x200>;
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
108 };
109
110 cpu3: cpu@300 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a55";
113 reg = <0x300>;
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
127 };
128
129 cpu4: cpu@400 {
130 device_type = "cpu";
131 compatible = "arm,cortex-a78";
132 reg = <0x400>;
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
146 };
147
148 cpu5: cpu@500 {
149 device_type = "cpu";
150 compatible = "arm,cortex-a78";
151 reg = <0x500>;
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
165 };
166
167 cpu6: cpu@600 {
168 device_type = "cpu";
169 compatible = "arm,cortex-a78";
170 reg = <0x600>;
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
184 };
185
186 cpu7: cpu@700 {
187 device_type = "cpu";
188 compatible = "arm,cortex-a78";
189 reg = <0x700>;
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
203 };
204
205 cpu-map {
206 cluster0 {
207 core0 {
208 cpu = <&cpu0>;
209 };
210
211 core1 {
212 cpu = <&cpu1>;
213 };
214
215 core2 {
216 cpu = <&cpu2>;
217 };
218
219 core3 {
220 cpu = <&cpu3>;
221 };
222
223 core4 {
224 cpu = <&cpu4>;
225 };
226
227 core5 {
228 cpu = <&cpu5>;
229 };
230
231 core6 {
232 cpu = <&cpu6>;
233 };
234
235 core7 {
236 cpu = <&cpu7>;
237 };
238 };
239 };
240
241 idle-states {
242 entry-method = "psci";
243
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
251 };
252
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
260 };
261
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
269 };
270
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
278 };
279 };
280
281 l2_0: l2-cache0 {
282 compatible = "cache";
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
289 };
290
291 l2_1: l2-cache1 {
292 compatible = "cache";
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
299 };
300
301 l3_0: l3-cache {
302 compatible = "cache";
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
308 };
309 };
310
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
316 status = "fail";
317 };
318
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
323 };
324
325 sound: mt8195-sound {
326 mediatek,platform = <&afe>;
327 status = "disabled";
328 };
329
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
333 clocks = <&clk26m>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
337 };
338
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
344 };
345
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
351 };
352
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
356 #performance-domain-cells = <1>;
357 };
358
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
362
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
366 };
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
370 };
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
374 };
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
378 };
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
382 };
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
386 };
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
390 };
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
394 };
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
398 };
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
402 };
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
406 };
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
410 };
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
414 };
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
418 };
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
422 };
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
426 };
427 };
428
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
433 };
434
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
439 };
440
441 psci {
442 compatible = "arm,psci-1.0";
443 method = "smc";
444 };
445
446 timer: timer {
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
453 };
454
455 soc {
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
459 ranges;
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
461
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
468 reg = <0 0x0c000000 0 0x40000>,
469 <0 0x0c040000 0 0x200000>;
470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
471
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
475 };
476
477 ppi_cluster1: interrupt-partition-1 {
478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
479 };
480 };
481 };
482
483 topckgen: syscon@10000000 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
485 reg = <0 0x10000000 0 0x1000>;
486 #clock-cells = <1>;
487 };
488
489 infracfg_ao: syscon@10001000 {
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
491 reg = <0 0x10001000 0 0x1000>;
492 #clock-cells = <1>;
493 #reset-cells = <1>;
494 };
495
496 pericfg: syscon@10003000 {
497 compatible = "mediatek,mt8195-pericfg", "syscon";
498 reg = <0 0x10003000 0 0x1000>;
499 #clock-cells = <1>;
500 };
501
502 pio: pinctrl@10005000 {
503 compatible = "mediatek,mt8195-pinctrl";
504 reg = <0 0x10005000 0 0x1000>,
505 <0 0x11d10000 0 0x1000>,
506 <0 0x11d30000 0 0x1000>,
507 <0 0x11d40000 0 0x1000>,
508 <0 0x11e20000 0 0x1000>,
509 <0 0x11eb0000 0 0x1000>,
510 <0 0x11f40000 0 0x1000>,
511 <0 0x1000b000 0 0x1000>;
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
513 "iocfg_br", "iocfg_lm", "iocfg_rb",
514 "iocfg_tl", "eint";
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
520 #interrupt-cells = <2>;
521 };
522
523 scpsys: syscon@10006000 {
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
525 reg = <0 0x10006000 0 0x1000>;
526
527 /* System Power Manager */
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
533
534 /* power domain of the SoC */
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
540
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]542 reg = <MT8195_POWER_DOMAIN_MFG1>;
543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
545 clock-names = "mfg", "alt";
546 mediatek,infracfg = <&infracfg_ao>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
550
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
552 reg = <MT8195_POWER_DOMAIN_MFG2>;
553 #power-domain-cells = <0>;
554 };
555
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
557 reg = <MT8195_POWER_DOMAIN_MFG3>;
558 #power-domain-cells = <0>;
559 };
560
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
562 reg = <MT8195_POWER_DOMAIN_MFG4>;
563 #power-domain-cells = <0>;
564 };
565
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
567 reg = <MT8195_POWER_DOMAIN_MFG5>;
568 #power-domain-cells = <0>;
569 };
570
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
572 reg = <MT8195_POWER_DOMAIN_MFG6>;
573 #power-domain-cells = <0>;
574 };
575 };
576 };
577
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
580 clocks = <&topckgen CLK_TOP_VPP>,
581 <&topckgen CLK_TOP_CAM>,
582 <&topckgen CLK_TOP_CCU>,
583 <&topckgen CLK_TOP_IMG>,
584 <&topckgen CLK_TOP_VENC>,
585 <&topckgen CLK_TOP_VDEC>,
586 <&topckgen CLK_TOP_WPE_VPP>,
587 <&topckgen CLK_TOP_CFG_VPP0>,
588 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
608 "vppsys4", "vppsys5", "vppsys6", "vppsys7",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
615 mediatek,infracfg = <&infracfg_ao>;
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
619
620 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
621 reg = <MT8195_POWER_DOMAIN_VDEC1>;
622 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 clock-names = "vdec1-0";
624 mediatek,infracfg = <&infracfg_ao>;
625 #power-domain-cells = <0>;
626 };
627
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
629 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
630 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
631 clock-names = "venc1-larb";
632 mediatek,infracfg = <&infracfg_ao>;
633 #power-domain-cells = <0>;
634 };
635
636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
637 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
638 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
639 <&vdosys0 CLK_VDO0_SMI_GALS>,
640 <&vdosys0 CLK_VDO0_SMI_COMMON>,
641 <&vdosys0 CLK_VDO0_SMI_EMI>,
642 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
643 <&vdosys0 CLK_VDO0_SMI_LARB>,
644 <&vdosys0 CLK_VDO0_SMI_RSI>;
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 "vdosys0-2", "vdosys0-3",
647 "vdosys0-4", "vdosys0-5";
648 mediatek,infracfg = <&infracfg_ao>;
649 #address-cells = <1>;
650 #size-cells = <0>;
651 #power-domain-cells = <1>;
652
653 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
654 reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
655 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
656 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
657 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
658 clock-names = "vppsys1", "vppsys1-0",
659 "vppsys1-1";
660 mediatek,infracfg = <&infracfg_ao>;
661 #power-domain-cells = <0>;
662 };
663
664 power-domain@MT8195_POWER_DOMAIN_WPESYS {
665 reg = <MT8195_POWER_DOMAIN_WPESYS>;
666 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
667 <&wpesys CLK_WPE_SMI_LARB8>,
668 <&wpesys CLK_WPE_SMI_LARB7_P>,
669 <&wpesys CLK_WPE_SMI_LARB8_P>;
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 "wepsys-3";
672 mediatek,infracfg = <&infracfg_ao>;
673 #power-domain-cells = <0>;
674 };
675
676 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
677 reg = <MT8195_POWER_DOMAIN_VDEC0>;
678 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
679 clock-names = "vdec0-0";
680 mediatek,infracfg = <&infracfg_ao>;
681 #power-domain-cells = <0>;
682 };
683
684 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
685 reg = <MT8195_POWER_DOMAIN_VDEC2>;
686 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
687 clock-names = "vdec2-0";
688 mediatek,infracfg = <&infracfg_ao>;
689 #power-domain-cells = <0>;
690 };
691
692 power-domain@MT8195_POWER_DOMAIN_VENC {
693 reg = <MT8195_POWER_DOMAIN_VENC>;
694 clocks = <&vencsys CLK_VENC_LARB>;
695 clock-names = "venc0-larb";
696 mediatek,infracfg = <&infracfg_ao>;
697 #power-domain-cells = <0>;
698 };
699
700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
701 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
702 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
703 <&vdosys1 CLK_VDO1_SMI_LARB2>,
704 <&vdosys1 CLK_VDO1_SMI_LARB3>,
705 <&vdosys1 CLK_VDO1_GALS>;
706 clock-names = "vdosys1", "vdosys1-0",
707 "vdosys1-1", "vdosys1-2";
708 mediatek,infracfg = <&infracfg_ao>;
709 #address-cells = <1>;
710 #size-cells = <0>;
711 #power-domain-cells = <1>;
712
713 power-domain@MT8195_POWER_DOMAIN_DP_TX {
714 reg = <MT8195_POWER_DOMAIN_DP_TX>;
715 mediatek,infracfg = <&infracfg_ao>;
716 #power-domain-cells = <0>;
717 };
718
719 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
720 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
721 mediatek,infracfg = <&infracfg_ao>;
722 #power-domain-cells = <0>;
723 };
724
725 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
726 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
727 clocks = <&topckgen CLK_TOP_HDMI_APB>;
728 clock-names = "hdmi_tx";
729 #power-domain-cells = <0>;
730 };
731 };
732
733 power-domain@MT8195_POWER_DOMAIN_IMG {
734 reg = <MT8195_POWER_DOMAIN_IMG>;
735 clocks = <&imgsys CLK_IMG_LARB9>,
736 <&imgsys CLK_IMG_GALS>;
737 clock-names = "img-0", "img-1";
738 mediatek,infracfg = <&infracfg_ao>;
739 #address-cells = <1>;
740 #size-cells = <0>;
741 #power-domain-cells = <1>;
742
743 power-domain@MT8195_POWER_DOMAIN_DIP {
744 reg = <MT8195_POWER_DOMAIN_DIP>;
745 #power-domain-cells = <0>;
746 };
747
748 power-domain@MT8195_POWER_DOMAIN_IPE {
749 reg = <MT8195_POWER_DOMAIN_IPE>;
750 clocks = <&topckgen CLK_TOP_IPE>,
751 <&imgsys CLK_IMG_IPE>,
752 <&ipesys CLK_IPE_SMI_LARB12>;
753 clock-names = "ipe", "ipe-0", "ipe-1";
754 mediatek,infracfg = <&infracfg_ao>;
755 #power-domain-cells = <0>;
756 };
757 };
758
759 power-domain@MT8195_POWER_DOMAIN_CAM {
760 reg = <MT8195_POWER_DOMAIN_CAM>;
761 clocks = <&camsys CLK_CAM_LARB13>,
762 <&camsys CLK_CAM_LARB14>,
763 <&camsys CLK_CAM_CAM2MM0_GALS>,
764 <&camsys CLK_CAM_CAM2MM1_GALS>,
765 <&camsys CLK_CAM_CAM2SYS_GALS>;
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 "cam-4";
768 mediatek,infracfg = <&infracfg_ao>;
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <1>;
772
773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
774 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
775 #power-domain-cells = <0>;
776 };
777
778 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
779 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
780 #power-domain-cells = <0>;
781 };
782
783 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
784 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
785 #power-domain-cells = <0>;
786 };
787 };
788 };
789 };
790
791 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
792 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
793 mediatek,infracfg = <&infracfg_ao>;
794 #power-domain-cells = <0>;
795 };
796
797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
798 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
799 mediatek,infracfg = <&infracfg_ao>;
800 #power-domain-cells = <0>;
801 };
802
803 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
804 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
805 #power-domain-cells = <0>;
806 };
807
808 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
809 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
810 #power-domain-cells = <0>;
811 };
812
813 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
814 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
815 clocks = <&topckgen CLK_TOP_SENINF>,
816 <&topckgen CLK_TOP_SENINF2>;
817 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power-domain-cells = <0>;
819 };
820
821 power-domain@MT8195_POWER_DOMAIN_ETHER {
822 reg = <MT8195_POWER_DOMAIN_ETHER>;
823 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
824 clock-names = "ether";
825 #power-domain-cells = <0>;
826 };
827
828 power-domain@MT8195_POWER_DOMAIN_ADSP {
829 reg = <MT8195_POWER_DOMAIN_ADSP>;
830 clocks = <&topckgen CLK_TOP_ADSP>,
831 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
832 clock-names = "adsp", "adsp1";
833 #address-cells = <1>;
834 #size-cells = <0>;
835 mediatek,infracfg = <&infracfg_ao>;
836 #power-domain-cells = <1>;
837
838 power-domain@MT8195_POWER_DOMAIN_AUDIO {
839 reg = <MT8195_POWER_DOMAIN_AUDIO>;
840 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
841 <&topckgen CLK_TOP_AUD_INTBUS>,
842 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
843 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
844 clock-names = "audio", "audio1", "audio2",
845 "audio3";
846 mediatek,infracfg = <&infracfg_ao>;
847 #power-domain-cells = <0>;
848 };
849 };
850 };
851 };
852
853 watchdog: watchdog@10007000 {
854 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrst;
856 reg = <0 0x10007000 0 0x100>;
857 #reset-cells = <1>;
858 };
859
860 apmixedsys: syscon@1000c000 {
861 compatible = "mediatek,mt8195-apmixedsys", "syscon";
862 reg = <0 0x1000c000 0 0x1000>;
863 #clock-cells = <1>;
864 };
865
866 systimer: timer@10017000 {
867 compatible = "mediatek,mt8195-timer",
868 "mediatek,mt6765-timer";
869 reg = <0 0x10017000 0 0x1000>;
870 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
871 clocks = <&clk13m>;
872 };
873
874 pwrap: pwrap@10024000 {
875 compatible = "mediatek,mt8195-pwrap", "syscon";
876 reg = <0 0x10024000 0 0x1000>;
877 reg-names = "pwrap";
878 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
880 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
881 clock-names = "spi", "wrap";
882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
884 };
885
886 spmi: spmi@10027000 {
887 compatible = "mediatek,mt8195-spmi";
888 reg = <0 0x10027000 0 0x000e00>,
889 <0 0x10029000 0 0x000100>;
890 reg-names = "pmif", "spmimst";
891 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
892 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
893 <&topckgen CLK_TOP_SPMI_M_MST>;
894 clock-names = "pmif_sys_ck",
895 "pmif_tmr_ck",
896 "spmimst_clk_mux";
897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
899 };
900
901 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek,mt8195-iommu-infra";
903 reg = <0 0x10315000 0 0x5000>;
904 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
905 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
906 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
907 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
908 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
909 #iommu-cells = <1>;
910 };
911
912 gce0: mailbox@10320000 {
913 compatible = "mediatek,mt8195-gce";
914 reg = <0 0x10320000 0 0x4000>;
915 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
916 #mbox-cells = <2>;
917 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
918 };
919
920 gce1: mailbox@10330000 {
921 compatible = "mediatek,mt8195-gce";
922 reg = <0 0x10330000 0 0x4000>;
923 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
924 #mbox-cells = <2>;
925 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
926 };
927
928 scp: scp@10500000 {
929 compatible = "mediatek,mt8195-scp";
930 reg = <0 0x10500000 0 0x100000>,
931 <0 0x10720000 0 0xe0000>,
932 <0 0x10700000 0 0x8000>;
933 reg-names = "sram", "cfg", "l1tcm";
934 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
935 status = "disabled";
936 };
937
938 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek,mt8195-scp_adsp";
940 reg = <0 0x10720000 0 0x1000>;
941 #clock-cells = <1>;
942 };
943
944 adsp: dsp@10803000 {
945 compatible = "mediatek,mt8195-dsp";
946 reg = <0 0x10803000 0 0x1000>,
947 <0 0x10840000 0 0x40000>;
948 reg-names = "cfg", "sram";
949 clocks = <&topckgen CLK_TOP_ADSP>,
950 <&clk26m>,
951 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
952 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
953 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
954 <&topckgen CLK_TOP_AUDIO_H>;
955 clock-names = "adsp_sel",
956 "clk26m_ck",
957 "audio_local_bus",
958 "mainpll_d7_d2",
959 "scp_adsp_audiodsp",
960 "audio_h";
961 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx";
963 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
964 status = "disabled";
965 };
966
967 adsp_mailbox0: mailbox@10816000 {
968 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>;
970 reg = <0 0x10816000 0 0x1000>;
971 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
972 };
973
974 adsp_mailbox1: mailbox@10817000 {
975 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>;
977 reg = <0 0x10817000 0 0x1000>;
978 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
979 };
980
981 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek,mt8195-audio";
983 reg = <0 0x10890000 0 0x10000>;
984 mediatek,topckgen = <&topckgen>;
985 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
986 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
987 resets = <&watchdog 14>;
988 reset-names = "audiosys";
989 clocks = <&clk26m>,
990 <&apmixedsys CLK_APMIXED_APLL1>,
991 <&apmixedsys CLK_APMIXED_APLL2>,
992 <&topckgen CLK_TOP_APLL12_DIV0>,
993 <&topckgen CLK_TOP_APLL12_DIV1>,
994 <&topckgen CLK_TOP_APLL12_DIV2>,
995 <&topckgen CLK_TOP_APLL12_DIV3>,
996 <&topckgen CLK_TOP_APLL12_DIV9>,
997 <&topckgen CLK_TOP_A1SYS_HP>,
998 <&topckgen CLK_TOP_AUD_INTBUS>,
999 <&topckgen CLK_TOP_AUDIO_H>,
1000 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1001 <&topckgen CLK_TOP_DPTX_MCK>,
1002 <&topckgen CLK_TOP_I2SO1_MCK>,
1003 <&topckgen CLK_TOP_I2SO2_MCK>,
1004 <&topckgen CLK_TOP_I2SI1_MCK>,
1005 <&topckgen CLK_TOP_I2SI2_MCK>,
1006 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1007 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1008 clock-names = "clk26m",
1009 "apll1_ck",
1010 "apll2_ck",
1011 "apll12_div0",
1012 "apll12_div1",
1013 "apll12_div2",
1014 "apll12_div3",
1015 "apll12_div9",
1016 "a1sys_hp_sel",
1017 "aud_intbus_sel",
1018 "audio_h_sel",
1019 "audio_local_bus_sel",
1020 "dptx_m_sel",
1021 "i2so1_m_sel",
1022 "i2so2_m_sel",
1023 "i2si1_m_sel",
1024 "i2si2_m_sel",
1025 "infra_ao_audio_26m_b",
1026 "scp_adsp_audiodsp";
1027 status = "disabled";
1028 };
1029
1030 uart0: serial@11001100 {
1031 compatible = "mediatek,mt8195-uart",
1032 "mediatek,mt6577-uart";
1033 reg = <0 0x11001100 0 0x100>;
1034 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1035 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1036 clock-names = "baud", "bus";
1037 status = "disabled";
1038 };
1039
1040 uart1: serial@11001200 {
1041 compatible = "mediatek,mt8195-uart",
1042 "mediatek,mt6577-uart";
1043 reg = <0 0x11001200 0 0x100>;
1044 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1045 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1046 clock-names = "baud", "bus";
1047 status = "disabled";
1048 };
1049
1050 uart2: serial@11001300 {
1051 compatible = "mediatek,mt8195-uart",
1052 "mediatek,mt6577-uart";
1053 reg = <0 0x11001300 0 0x100>;
1054 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1055 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1056 clock-names = "baud", "bus";
1057 status = "disabled";
1058 };
1059
1060 uart3: serial@11001400 {
1061 compatible = "mediatek,mt8195-uart",
1062 "mediatek,mt6577-uart";
1063 reg = <0 0x11001400 0 0x100>;
1064 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1065 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1066 clock-names = "baud", "bus";
1067 status = "disabled";
1068 };
1069
1070 uart4: serial@11001500 {
1071 compatible = "mediatek,mt8195-uart",
1072 "mediatek,mt6577-uart";
1073 reg = <0 0x11001500 0 0x100>;
1074 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1075 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1076 clock-names = "baud", "bus";
1077 status = "disabled";
1078 };
1079
1080 uart5: serial@11001600 {
1081 compatible = "mediatek,mt8195-uart",
1082 "mediatek,mt6577-uart";
1083 reg = <0 0x11001600 0 0x100>;
1084 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1085 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1086 clock-names = "baud", "bus";
1087 status = "disabled";
1088 };
1089
1090 auxadc: auxadc@11002000 {
1091 compatible = "mediatek,mt8195-auxadc",
1092 "mediatek,mt8173-auxadc";
1093 reg = <0 0x11002000 0 0x1000>;
1094 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1095 clock-names = "main";
1096 #io-channel-cells = <1>;
1097 status = "disabled";
1098 };
1099
1100 pericfg_ao: syscon@11003000 {
1101 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1102 reg = <0 0x11003000 0 0x1000>;
1103 #clock-cells = <1>;
1104 };
1105
1106 spi0: spi@1100a000 {
1107 compatible = "mediatek,mt8195-spi",
1108 "mediatek,mt6765-spi";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 reg = <0 0x1100a000 0 0x1000>;
1112 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1113 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1114 <&topckgen CLK_TOP_SPI>,
1115 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1116 clock-names = "parent-clk", "sel-clk", "spi-clk";
1117 status = "disabled";
1118 };
1119
1120 lvts_ap: thermal-sensor@1100b000 {
1121 compatible = "mediatek,mt8195-lvts-ap";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1122 reg = <0 0x1100b000 0 0xc00>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1123 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1124 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1125 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1126 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1129 };
1130
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1131 svs: svs@1100bc00 {
1132 compatible = "mediatek,mt8195-svs";
1133 reg = <0 0x1100bc00 0 0x400>;
1134 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;
1135 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1136 clock-names = "main";
1137 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1138 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1139 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
1140 reset-names = "svs_rst";
1141 };
1142
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1143 disp_pwm0: pwm@1100e000 {
1144 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1145 reg = <0 0x1100e000 0 0x1000>;
1146 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1147 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1148 #pwm-cells = <2>;
1149 clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1150 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1151 clock-names = "main", "mm";
1152 status = "disabled";
1153 };
1154
1155 disp_pwm1: pwm@1100f000 {
1156 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1157 reg = <0 0x1100f000 0 0x1000>;
1158 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
1159 #pwm-cells = <2>;
1160 clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1161 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1162 clock-names = "main", "mm";
1163 status = "disabled";
1164 };
1165
1166 spi1: spi@11010000 {
1167 compatible = "mediatek,mt8195-spi",
1168 "mediatek,mt6765-spi";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1171 reg = <0 0x11010000 0 0x1000>;
1172 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1173 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1174 <&topckgen CLK_TOP_SPI>,
1175 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1176 clock-names = "parent-clk", "sel-clk", "spi-clk";
1177 status = "disabled";
1178 };
1179
1180 spi2: spi@11012000 {
1181 compatible = "mediatek,mt8195-spi",
1182 "mediatek,mt6765-spi";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 reg = <0 0x11012000 0 0x1000>;
1186 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1187 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1188 <&topckgen CLK_TOP_SPI>,
1189 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1190 clock-names = "parent-clk", "sel-clk", "spi-clk";
1191 status = "disabled";
1192 };
1193
1194 spi3: spi@11013000 {
1195 compatible = "mediatek,mt8195-spi",
1196 "mediatek,mt6765-spi";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 reg = <0 0x11013000 0 0x1000>;
1200 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1201 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1202 <&topckgen CLK_TOP_SPI>,
1203 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1204 clock-names = "parent-clk", "sel-clk", "spi-clk";
1205 status = "disabled";
1206 };
1207
1208 spi4: spi@11018000 {
1209 compatible = "mediatek,mt8195-spi",
1210 "mediatek,mt6765-spi";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213 reg = <0 0x11018000 0 0x1000>;
1214 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1215 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1216 <&topckgen CLK_TOP_SPI>,
1217 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1218 clock-names = "parent-clk", "sel-clk", "spi-clk";
1219 status = "disabled";
1220 };
1221
1222 spi5: spi@11019000 {
1223 compatible = "mediatek,mt8195-spi",
1224 "mediatek,mt6765-spi";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227 reg = <0 0x11019000 0 0x1000>;
1228 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1229 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1230 <&topckgen CLK_TOP_SPI>,
1231 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1232 clock-names = "parent-clk", "sel-clk", "spi-clk";
1233 status = "disabled";
1234 };
1235
1236 spis0: spi@1101d000 {
1237 compatible = "mediatek,mt8195-spi-slave";
1238 reg = <0 0x1101d000 0 0x1000>;
1239 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1240 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1241 clock-names = "spi";
1242 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1244 status = "disabled";
1245 };
1246
1247 spis1: spi@1101e000 {
1248 compatible = "mediatek,mt8195-spi-slave";
1249 reg = <0 0x1101e000 0 0x1000>;
1250 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1251 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1252 clock-names = "spi";
1253 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1255 status = "disabled";
1256 };
1257
1258 eth: ethernet@11021000 {
1259 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1260 reg = <0 0x11021000 0 0x4000>;
1261 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1262 interrupt-names = "macirq";
1263 clock-names = "axi",
1264 "apb",
1265 "mac_main",
1266 "ptp_ref",
1267 "rmii_internal",
1268 "mac_cg";
1269 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1270 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1271 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1272 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1273 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1274 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1275 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1276 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1277 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1278 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1279 <&topckgen CLK_TOP_ETHPLL_D8>,
1280 <&topckgen CLK_TOP_ETHPLL_D10>;
1281 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1282 mediatek,pericfg = <&infracfg_ao>;
1283 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,mtl-rx-config = <&mtl_rx_setup>;
1285 snps,mtl-tx-config = <&mtl_tx_setup>;
1286 snps,txpbl = <16>;
1287 snps,rxpbl = <16>;
1288 snps,clk-csr = <0>;
1289 status = "disabled";
1290
1291 mdio {
1292 compatible = "snps,dwmac-mdio";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1295 };
1296
1297 stmmac_axi_setup: stmmac-axi-config {
1298 snps,wr_osr_lmt = <0x7>;
1299 snps,rd_osr_lmt = <0x7>;
1300 snps,blen = <0 0 0 0 16 8 4>;
1301 };
1302
1303 mtl_rx_setup: rx-queues-config {
1304 snps,rx-queues-to-use = <4>;
1305 snps,rx-sched-sp;
1306 queue0 {
1307 snps,dcb-algorithm;
1308 snps,map-to-dma-channel = <0x0>;
1309 };
1310 queue1 {
1311 snps,dcb-algorithm;
1312 snps,map-to-dma-channel = <0x0>;
1313 };
1314 queue2 {
1315 snps,dcb-algorithm;
1316 snps,map-to-dma-channel = <0x0>;
1317 };
1318 queue3 {
1319 snps,dcb-algorithm;
1320 snps,map-to-dma-channel = <0x0>;
1321 };
1322 };
1323
1324 mtl_tx_setup: tx-queues-config {
1325 snps,tx-queues-to-use = <4>;
1326 snps,tx-sched-wrr;
1327 queue0 {
1328 snps,weight = <0x10>;
1329 snps,dcb-algorithm;
1330 snps,priority = <0x0>;
1331 };
1332 queue1 {
1333 snps,weight = <0x11>;
1334 snps,dcb-algorithm;
1335 snps,priority = <0x1>;
1336 };
1337 queue2 {
1338 snps,weight = <0x12>;
1339 snps,dcb-algorithm;
1340 snps,priority = <0x2>;
1341 };
1342 queue3 {
1343 snps,weight = <0x13>;
1344 snps,dcb-algorithm;
1345 snps,priority = <0x3>;
1346 };
1347 };
1348 };
1349
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1350 ssusb0: usb@11201000 {
1351 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1352 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1353 reg-names = "mac", "ippc";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1354 ranges = <0 0 0 0x11200000 0 0x3f00>;
1355 #address-cells = <2>;
1356 #size-cells = <2>;
1357 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1358 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1359 <&topckgen CLK_TOP_SSUSB_REF>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1360 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1361 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1362 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1363 wakeup-source;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1364 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1365 status = "disabled";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1366
1367 xhci0: usb@0 {
1368 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1369 reg = <0 0 0 0x1000>;
1370 reg-names = "mac";
1371 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1372 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1373 <&topckgen CLK_TOP_SSUSB_XHCI>;
1374 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1375 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1376 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1377 <&topckgen CLK_TOP_SSUSB_REF>,
1378 <&apmixedsys CLK_APMIXED_USB1PLL>,
1379 <&clk26m>,
1380 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1381 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1382 status = "disabled";
1383 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1384 };
1385
1386 mmc0: mmc@11230000 {
1387 compatible = "mediatek,mt8195-mmc",
1388 "mediatek,mt8183-mmc";
1389 reg = <0 0x11230000 0 0x10000>,
1390 <0 0x11f50000 0 0x1000>;
1391 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1392 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1393 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1394 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1395 clock-names = "source", "hclk", "source_cg";
1396 status = "disabled";
1397 };
1398
1399 mmc1: mmc@11240000 {
1400 compatible = "mediatek,mt8195-mmc",
1401 "mediatek,mt8183-mmc";
1402 reg = <0 0x11240000 0 0x1000>,
1403 <0 0x11c70000 0 0x1000>;
1404 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1405 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1406 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1407 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1408 clock-names = "source", "hclk", "source_cg";
1409 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1411 status = "disabled";
1412 };
1413
1414 mmc2: mmc@11250000 {
1415 compatible = "mediatek,mt8195-mmc",
1416 "mediatek,mt8183-mmc";
1417 reg = <0 0x11250000 0 0x1000>,
1418 <0 0x11e60000 0 0x1000>;
1419 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1420 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1421 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1422 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1423 clock-names = "source", "hclk", "source_cg";
1424 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1426 status = "disabled";
1427 };
1428
1429 lvts_mcu: thermal-sensor@11278000 {
1430 compatible = "mediatek,mt8195-lvts-mcu";
1431 reg = <0 0x11278000 0 0x1000>;
1432 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1433 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1434 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1435 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1436 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1437 #thermal-sensor-cells = <1>;
1438 };
1439
1440 xhci1: usb@11290000 {
1441 compatible = "mediatek,mt8195-xhci",
1442 "mediatek,mtk-xhci";
1443 reg = <0 0x11290000 0 0x1000>,
1444 <0 0x11293e00 0 0x0100>;
1445 reg-names = "mac", "ippc";
1446 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1447 phys = <&u2port1 PHY_TYPE_USB2>;
1448 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1452 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1453 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1454 <&apmixedsys CLK_APMIXED_USB1PLL>,
1455 <&clk26m>,
1456 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1457 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1458 "xhci_ck";
1459 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1460 wakeup-source;
1461 status = "disabled";
1462 };
1463
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1464 ssusb2: usb@112a1000 {
1465 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1466 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1467 reg-names = "mac", "ippc";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1468 ranges = <0 0 0 0x112a0000 0 0x3f00>;
1469 #address-cells = <2>;
1470 #size-cells = <2>;
1471 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
1472 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1473 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1474 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1475 <&topckgen CLK_TOP_SSUSB_P2_REF>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1476 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1477 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1478 phys = <&u2port2 PHY_TYPE_USB2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1479 wakeup-source;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1480 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1481 status = "disabled";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1482
1483 xhci2: usb@0 {
1484 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1485 reg = <0 0 0 0x1000>;
1486 reg-names = "mac";
1487 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1488 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1489 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1490 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1491 clock-names = "sys_ck";
1492 status = "disabled";
1493 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1494 };
1495
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1496 ssusb3: usb@112b1000 {
1497 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1498 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1499 reg-names = "mac", "ippc";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1500 ranges = <0 0 0 0x112b0000 0 0x3f00>;
1501 #address-cells = <2>;
1502 #size-cells = <2>;
1503 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
1504 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1505 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1506 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1507 <&topckgen CLK_TOP_SSUSB_P3_REF>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1508 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1509 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1510 phys = <&u2port3 PHY_TYPE_USB2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1511 wakeup-source;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1512 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1513 status = "disabled";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1514
1515 xhci3: usb@0 {
1516 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1517 reg = <0 0 0 0x1000>;
1518 reg-names = "mac";
1519 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1520 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1521 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1522 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1523 clock-names = "sys_ck";
1524 status = "disabled";
1525 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1526 };
1527
1528 pcie0: pcie@112f0000 {
1529 compatible = "mediatek,mt8195-pcie",
1530 "mediatek,mt8192-pcie";
1531 device_type = "pci";
1532 #address-cells = <3>;
1533 #size-cells = <2>;
1534 reg = <0 0x112f0000 0 0x4000>;
1535 reg-names = "pcie-mac";
1536 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1537 bus-range = <0x00 0xff>;
1538 ranges = <0x81000000 0 0x20000000
1539 0x0 0x20000000 0 0x200000>,
1540 <0x82000000 0 0x20200000
1541 0x0 0x20200000 0 0x3e00000>;
1542
1543 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1544 iommu-map-mask = <0x0>;
1545
1546 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1547 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1548 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1549 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1550 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1551 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1552 clock-names = "pl_250m", "tl_26m", "tl_96m",
1553 "tl_32k", "peri_26m", "peri_mem";
1554 assigned-clocks = <&topckgen CLK_TOP_TL>;
1555 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1556
1557 phys = <&pciephy>;
1558 phy-names = "pcie-phy";
1559
1560 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1561
1562 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1563 reset-names = "mac";
1564
1565 #interrupt-cells = <1>;
1566 interrupt-map-mask = <0 0 0 7>;
1567 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1568 <0 0 0 2 &pcie_intc0 1>,
1569 <0 0 0 3 &pcie_intc0 2>,
1570 <0 0 0 4 &pcie_intc0 3>;
1571 status = "disabled";
1572
1573 pcie_intc0: interrupt-controller {
1574 interrupt-controller;
1575 #address-cells = <0>;
1576 #interrupt-cells = <1>;
1577 };
1578 };
1579
1580 pcie1: pcie@112f8000 {
1581 compatible = "mediatek,mt8195-pcie",
1582 "mediatek,mt8192-pcie";
1583 device_type = "pci";
1584 #address-cells = <3>;
1585 #size-cells = <2>;
1586 reg = <0 0x112f8000 0 0x4000>;
1587 reg-names = "pcie-mac";
1588 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1589 bus-range = <0x00 0xff>;
1590 ranges = <0x81000000 0 0x24000000
1591 0x0 0x24000000 0 0x200000>,
1592 <0x82000000 0 0x24200000
1593 0x0 0x24200000 0 0x3e00000>;
1594
1595 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1596 iommu-map-mask = <0x0>;
1597
1598 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1599 <&clk26m>,
1600 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1601 <&clk26m>,
1602 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1603 /* Designer has connect pcie1 with peri_mem_p0 clock */
1604 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1605 clock-names = "pl_250m", "tl_26m", "tl_96m",
1606 "tl_32k", "peri_26m", "peri_mem";
1607 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1608 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1609
1610 phys = <&u3port1 PHY_TYPE_PCIE>;
1611 phy-names = "pcie-phy";
1612 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1613
1614 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1615 reset-names = "mac";
1616
1617 #interrupt-cells = <1>;
1618 interrupt-map-mask = <0 0 0 7>;
1619 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1620 <0 0 0 2 &pcie_intc1 1>,
1621 <0 0 0 3 &pcie_intc1 2>,
1622 <0 0 0 4 &pcie_intc1 3>;
1623 status = "disabled";
1624
1625 pcie_intc1: interrupt-controller {
1626 interrupt-controller;
1627 #address-cells = <0>;
1628 #interrupt-cells = <1>;
1629 };
1630 };
1631
1632 nor_flash: spi@1132c000 {
1633 compatible = "mediatek,mt8195-nor",
1634 "mediatek,mt8173-nor";
1635 reg = <0 0x1132c000 0 0x1000>;
1636 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1637 clocks = <&topckgen CLK_TOP_SPINOR>,
1638 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1639 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1640 clock-names = "spi", "sf", "axi";
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1643 status = "disabled";
1644 };
1645
1646 efuse: efuse@11c10000 {
1647 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1648 reg = <0 0x11c10000 0 0x1000>;
1649 #address-cells = <1>;
1650 #size-cells = <1>;
1651 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1652 reg = <0x184 0x1>;
1653 bits = <0 5>;
1654 };
1655 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1656 reg = <0x184 0x2>;
1657 bits = <5 5>;
1658 };
1659 u3_intr_p0: usb3-intr@185 {
1660 reg = <0x185 0x1>;
1661 bits = <2 6>;
1662 };
1663 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1664 reg = <0x186 0x1>;
1665 bits = <0 5>;
1666 };
1667 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1668 reg = <0x186 0x2>;
1669 bits = <5 5>;
1670 };
1671 comb_intr_p1: usb3-intr@187 {
1672 reg = <0x187 0x1>;
1673 bits = <2 6>;
1674 };
1675 u2_intr_p0: usb2-intr-p0@188,1 {
1676 reg = <0x188 0x1>;
1677 bits = <0 5>;
1678 };
1679 u2_intr_p1: usb2-intr-p1@188,2 {
1680 reg = <0x188 0x2>;
1681 bits = <5 5>;
1682 };
1683 u2_intr_p2: usb2-intr-p2@189,1 {
1684 reg = <0x189 0x1>;
1685 bits = <2 5>;
1686 };
1687 u2_intr_p3: usb2-intr-p3@189,2 {
1688 reg = <0x189 0x2>;
1689 bits = <7 5>;
1690 };
1691 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1692 reg = <0x190 0x1>;
1693 bits = <0 4>;
1694 };
1695 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1696 reg = <0x190 0x1>;
1697 bits = <4 4>;
1698 };
1699 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1700 reg = <0x191 0x1>;
1701 bits = <0 4>;
1702 };
1703 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1704 reg = <0x191 0x1>;
1705 bits = <4 4>;
1706 };
1707 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1708 reg = <0x192 0x1>;
1709 bits = <0 4>;
1710 };
1711 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1712 reg = <0x192 0x1>;
1713 bits = <4 4>;
1714 };
1715 pciephy_glb_intr: pciephy-glb-intr@193 {
1716 reg = <0x193 0x1>;
1717 bits = <0 4>;
1718 };
1719 dp_calibration: dp-data@1ac {
1720 reg = <0x1ac 0x10>;
1721 };
1722 lvts_efuse_data1: lvts1-calib@1bc {
1723 reg = <0x1bc 0x14>;
1724 };
1725 lvts_efuse_data2: lvts2-calib@1d0 {
1726 reg = <0x1d0 0x38>;
1727 };
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1728 svs_calib_data: svs-calib@580 {
1729 reg = <0x580 0x64>;
1730 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1731 socinfo-data1@7a0 {
1732 reg = <0x7a0 0x4>;
1733 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1734 };
1735
1736 u3phy2: t-phy@11c40000 {
1737 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1738 #address-cells = <1>;
1739 #size-cells = <1>;
1740 ranges = <0 0 0x11c40000 0x700>;
1741 status = "disabled";
1742
1743 u2port2: usb-phy@0 {
1744 reg = <0x0 0x700>;
1745 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1746 clock-names = "ref";
1747 #phy-cells = <1>;
1748 };
1749 };
1750
1751 u3phy3: t-phy@11c50000 {
1752 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1753 #address-cells = <1>;
1754 #size-cells = <1>;
1755 ranges = <0 0 0x11c50000 0x700>;
1756 status = "disabled";
1757
1758 u2port3: usb-phy@0 {
1759 reg = <0x0 0x700>;
1760 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1761 clock-names = "ref";
1762 #phy-cells = <1>;
1763 };
1764 };
1765
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1766 mipi_tx0: dsi-phy@11c80000 {
1767 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1768 reg = <0 0x11c80000 0 0x1000>;
1769 clocks = <&clk26m>;
1770 clock-output-names = "mipi_tx0_pll";
1771 #clock-cells = <0>;
1772 #phy-cells = <0>;
1773 status = "disabled";
1774 };
1775
1776 mipi_tx1: dsi-phy@11c90000 {
1777 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1778 reg = <0 0x11c90000 0 0x1000>;
1779 clocks = <&clk26m>;
1780 clock-output-names = "mipi_tx1_pll";
1781 #clock-cells = <0>;
1782 #phy-cells = <0>;
1783 status = "disabled";
1784 };
1785
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1786 i2c5: i2c@11d00000 {
1787 compatible = "mediatek,mt8195-i2c",
1788 "mediatek,mt8192-i2c";
1789 reg = <0 0x11d00000 0 0x1000>,
1790 <0 0x10220580 0 0x80>;
1791 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1792 clock-div = <1>;
1793 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1794 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1795 clock-names = "main", "dma";
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1798 status = "disabled";
1799 };
1800
1801 i2c6: i2c@11d01000 {
1802 compatible = "mediatek,mt8195-i2c",
1803 "mediatek,mt8192-i2c";
1804 reg = <0 0x11d01000 0 0x1000>,
1805 <0 0x10220600 0 0x80>;
1806 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1807 clock-div = <1>;
1808 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1809 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1810 clock-names = "main", "dma";
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1813 status = "disabled";
1814 };
1815
1816 i2c7: i2c@11d02000 {
1817 compatible = "mediatek,mt8195-i2c",
1818 "mediatek,mt8192-i2c";
1819 reg = <0 0x11d02000 0 0x1000>,
1820 <0 0x10220680 0 0x80>;
1821 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1822 clock-div = <1>;
1823 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1824 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1825 clock-names = "main", "dma";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1828 status = "disabled";
1829 };
1830
1831 imp_iic_wrap_s: clock-controller@11d03000 {
1832 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1833 reg = <0 0x11d03000 0 0x1000>;
1834 #clock-cells = <1>;
1835 };
1836
1837 i2c0: i2c@11e00000 {
1838 compatible = "mediatek,mt8195-i2c",
1839 "mediatek,mt8192-i2c";
1840 reg = <0 0x11e00000 0 0x1000>,
1841 <0 0x10220080 0 0x80>;
1842 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1843 clock-div = <1>;
1844 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1845 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1846 clock-names = "main", "dma";
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1849 status = "disabled";
1850 };
1851
1852 i2c1: i2c@11e01000 {
1853 compatible = "mediatek,mt8195-i2c",
1854 "mediatek,mt8192-i2c";
1855 reg = <0 0x11e01000 0 0x1000>,
1856 <0 0x10220200 0 0x80>;
1857 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1858 clock-div = <1>;
1859 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1860 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1861 clock-names = "main", "dma";
1862 #address-cells = <1>;
1863 #size-cells = <0>;
1864 status = "disabled";
1865 };
1866
1867 i2c2: i2c@11e02000 {
1868 compatible = "mediatek,mt8195-i2c",
1869 "mediatek,mt8192-i2c";
1870 reg = <0 0x11e02000 0 0x1000>,
1871 <0 0x10220380 0 0x80>;
1872 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1873 clock-div = <1>;
1874 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1875 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1876 clock-names = "main", "dma";
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1879 status = "disabled";
1880 };
1881
1882 i2c3: i2c@11e03000 {
1883 compatible = "mediatek,mt8195-i2c",
1884 "mediatek,mt8192-i2c";
1885 reg = <0 0x11e03000 0 0x1000>,
1886 <0 0x10220480 0 0x80>;
1887 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1888 clock-div = <1>;
1889 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1890 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1891 clock-names = "main", "dma";
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1894 status = "disabled";
1895 };
1896
1897 i2c4: i2c@11e04000 {
1898 compatible = "mediatek,mt8195-i2c",
1899 "mediatek,mt8192-i2c";
1900 reg = <0 0x11e04000 0 0x1000>,
1901 <0 0x10220500 0 0x80>;
1902 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1903 clock-div = <1>;
1904 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1905 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1906 clock-names = "main", "dma";
1907 #address-cells = <1>;
1908 #size-cells = <0>;
1909 status = "disabled";
1910 };
1911
1912 imp_iic_wrap_w: clock-controller@11e05000 {
1913 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1914 reg = <0 0x11e05000 0 0x1000>;
1915 #clock-cells = <1>;
1916 };
1917
1918 u3phy1: t-phy@11e30000 {
1919 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1920 #address-cells = <1>;
1921 #size-cells = <1>;
1922 ranges = <0 0 0x11e30000 0xe00>;
1923 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1924 status = "disabled";
1925
1926 u2port1: usb-phy@0 {
1927 reg = <0x0 0x700>;
1928 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1929 <&clk26m>;
1930 clock-names = "ref", "da_ref";
1931 #phy-cells = <1>;
1932 };
1933
1934 u3port1: usb-phy@700 {
1935 reg = <0x700 0x700>;
1936 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1937 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1938 clock-names = "ref", "da_ref";
1939 nvmem-cells = <&comb_intr_p1>,
1940 <&comb_rx_imp_p1>,
1941 <&comb_tx_imp_p1>;
1942 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1943 #phy-cells = <1>;
1944 };
1945 };
1946
1947 u3phy0: t-phy@11e40000 {
1948 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1949 #address-cells = <1>;
1950 #size-cells = <1>;
1951 ranges = <0 0 0x11e40000 0xe00>;
1952 status = "disabled";
1953
1954 u2port0: usb-phy@0 {
1955 reg = <0x0 0x700>;
1956 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1957 <&clk26m>;
1958 clock-names = "ref", "da_ref";
1959 #phy-cells = <1>;
1960 };
1961
1962 u3port0: usb-phy@700 {
1963 reg = <0x700 0x700>;
1964 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1965 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1966 clock-names = "ref", "da_ref";
1967 nvmem-cells = <&u3_intr_p0>,
1968 <&u3_rx_imp_p0>,
1969 <&u3_tx_imp_p0>;
1970 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1971 #phy-cells = <1>;
1972 };
1973 };
1974
1975 pciephy: phy@11e80000 {
1976 compatible = "mediatek,mt8195-pcie-phy";
1977 reg = <0 0x11e80000 0 0x10000>;
1978 reg-names = "sif";
1979 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1980 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1981 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1982 <&pciephy_rx_ln1>;
1983 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1984 "tx_ln0_nmos", "rx_ln0",
1985 "tx_ln1_pmos", "tx_ln1_nmos",
1986 "rx_ln1";
1987 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1988 #phy-cells = <0>;
1989 status = "disabled";
1990 };
1991
1992 ufsphy: ufs-phy@11fa0000 {
1993 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1994 reg = <0 0x11fa0000 0 0xc000>;
1995 clocks = <&clk26m>, <&clk26m>;
1996 clock-names = "unipro", "mp";
1997 #phy-cells = <0>;
1998 status = "disabled";
1999 };
2000
2001 gpu: gpu@13000000 {
2002 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
2003 "arm,mali-valhall-jm";
2004 reg = <0 0x13000000 0 0x4000>;
2005
2006 clocks = <&mfgcfg CLK_MFG_BG3D>;
2007 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
2008 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
2009 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
2010 interrupt-names = "job", "mmu", "gpu";
2011 operating-points-v2 = <&gpu_opp_table>;
2012 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
2013 <&spm MT8195_POWER_DOMAIN_MFG3>,
2014 <&spm MT8195_POWER_DOMAIN_MFG4>,
2015 <&spm MT8195_POWER_DOMAIN_MFG5>,
2016 <&spm MT8195_POWER_DOMAIN_MFG6>;
2017 power-domain-names = "core0", "core1", "core2", "core3", "core4";
2018 status = "disabled";
2019 };
2020
2021 mfgcfg: clock-controller@13fbf000 {
2022 compatible = "mediatek,mt8195-mfgcfg";
2023 reg = <0 0x13fbf000 0 0x1000>;
2024 #clock-cells = <1>;
2025 };
2026
2027 vppsys0: syscon@14000000 {
2028 compatible = "mediatek,mt8195-vppsys0", "syscon";
2029 reg = <0 0x14000000 0 0x1000>;
2030 #clock-cells = <1>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]2031 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2032 };
2033
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2034 dma-controller@14001000 {
2035 compatible = "mediatek,mt8195-mdp3-rdma";
2036 reg = <0 0x14001000 0 0x1000>;
2037 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2038 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2039 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
2040 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2041 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
2042 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
2043 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
2044 <&gce1 13 CMDQ_THR_PRIO_1>,
2045 <&gce1 14 CMDQ_THR_PRIO_1>,
2046 <&gce1 21 CMDQ_THR_PRIO_1>,
2047 <&gce1 22 CMDQ_THR_PRIO_1>;
2048 #dma-cells = <1>;
2049 };
2050
2051 display@14002000 {
2052 compatible = "mediatek,mt8195-mdp3-fg";
2053 reg = <0 0x14002000 0 0x1000>;
2054 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2055 clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
2056 };
2057
2058 display@14003000 {
2059 compatible = "mediatek,mt8195-mdp3-stitch";
2060 reg = <0 0x14003000 0 0x1000>;
2061 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2062 clocks = <&vppsys0 CLK_VPP0_STITCH>;
2063 };
2064
2065 display@14004000 {
2066 compatible = "mediatek,mt8195-mdp3-hdr";
2067 reg = <0 0x14004000 0 0x1000>;
2068 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2069 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
2070 };
2071
2072 display@14005000 {
2073 compatible = "mediatek,mt8195-mdp3-aal";
2074 reg = <0 0x14005000 0 0x1000>;
2075 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
2076 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2077 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
2078 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2079 };
2080
2081 display@14006000 {
2082 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2083 reg = <0 0x14006000 0 0x1000>;
2084 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2085 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2086 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
2087 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
2088 };
2089
2090 display@14007000 {
2091 compatible = "mediatek,mt8195-mdp3-tdshp";
2092 reg = <0 0x14007000 0 0x1000>;
2093 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2094 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
2095 };
2096
2097 display@14008000 {
2098 compatible = "mediatek,mt8195-mdp3-color";
2099 reg = <0 0x14008000 0 0x1000>;
2100 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
2101 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2102 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
2103 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2104 };
2105
2106 display@14009000 {
2107 compatible = "mediatek,mt8195-mdp3-ovl";
2108 reg = <0 0x14009000 0 0x1000>;
2109 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
2110 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2111 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
2112 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2113 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
2114 };
2115
2116 display@1400a000 {
2117 compatible = "mediatek,mt8195-mdp3-padding";
2118 reg = <0 0x1400a000 0 0x1000>;
2119 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2120 clocks = <&vppsys0 CLK_VPP0_PADDING>;
2121 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2122 };
2123
2124 display@1400b000 {
2125 compatible = "mediatek,mt8195-mdp3-tcc";
2126 reg = <0 0x1400b000 0 0x1000>;
2127 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2128 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
2129 };
2130
2131 dma-controller@1400c000 {
2132 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2133 reg = <0 0x1400c000 0 0x1000>;
2134 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2135 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2136 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
2137 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
2138 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
2139 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2140 #dma-cells = <1>;
2141 };
2142
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2143 mutex@1400f000 {
2144 compatible = "mediatek,mt8195-vpp-mutex";
2145 reg = <0 0x1400f000 0 0x1000>;
2146 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
2147 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2148 clocks = <&vppsys0 CLK_VPP0_MUTEX>;
2149 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2150 };
2151
2152 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
2153 compatible = "mediatek,mt8195-smi-sub-common";
2154 reg = <0 0x14010000 0 0x1000>;
2155 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2156 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2157 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2158 clock-names = "apb", "smi", "gals0";
2159 mediatek,smi = <&smi_common_vpp>;
2160 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2161 };
2162
2163 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
2164 compatible = "mediatek,mt8195-smi-sub-common";
2165 reg = <0 0x14011000 0 0x1000>;
2166 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2167 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2168 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2169 clock-names = "apb", "smi", "gals0";
2170 mediatek,smi = <&smi_common_vpp>;
2171 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2172 };
2173
2174 smi_common_vpp: smi@14012000 {
2175 compatible = "mediatek,mt8195-smi-common-vpp";
2176 reg = <0 0x14012000 0 0x1000>;
2177 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2178 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2179 <&vppsys0 CLK_VPP0_SMI_RSI>,
2180 <&vppsys0 CLK_VPP0_SMI_RSI>;
2181 clock-names = "apb", "smi", "gals0", "gals1";
2182 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2183 };
2184
2185 larb4: larb@14013000 {
2186 compatible = "mediatek,mt8195-smi-larb";
2187 reg = <0 0x14013000 0 0x1000>;
2188 mediatek,larb-id = <4>;
2189 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2190 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2191 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2192 clock-names = "apb", "smi";
2193 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2194 };
2195
2196 iommu_vpp: iommu@14018000 {
2197 compatible = "mediatek,mt8195-iommu-vpp";
2198 reg = <0 0x14018000 0 0x1000>;
2199 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2200 &larb12 &larb14 &larb16 &larb18
2201 &larb20 &larb22 &larb23 &larb26
2202 &larb27>;
2203 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2204 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2205 clock-names = "bclk";
2206 #iommu-cells = <1>;
2207 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2208 };
2209
2210 wpesys: clock-controller@14e00000 {
2211 compatible = "mediatek,mt8195-wpesys";
2212 reg = <0 0x14e00000 0 0x1000>;
2213 #clock-cells = <1>;
2214 };
2215
2216 wpesys_vpp0: clock-controller@14e02000 {
2217 compatible = "mediatek,mt8195-wpesys_vpp0";
2218 reg = <0 0x14e02000 0 0x1000>;
2219 #clock-cells = <1>;
2220 };
2221
2222 wpesys_vpp1: clock-controller@14e03000 {
2223 compatible = "mediatek,mt8195-wpesys_vpp1";
2224 reg = <0 0x14e03000 0 0x1000>;
2225 #clock-cells = <1>;
2226 };
2227
2228 larb7: larb@14e04000 {
2229 compatible = "mediatek,mt8195-smi-larb";
2230 reg = <0 0x14e04000 0 0x1000>;
2231 mediatek,larb-id = <7>;
2232 mediatek,smi = <&smi_common_vdo>;
2233 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2234 <&wpesys CLK_WPE_SMI_LARB7>;
2235 clock-names = "apb", "smi";
2236 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2237 };
2238
2239 larb8: larb@14e05000 {
2240 compatible = "mediatek,mt8195-smi-larb";
2241 reg = <0 0x14e05000 0 0x1000>;
2242 mediatek,larb-id = <8>;
2243 mediatek,smi = <&smi_common_vpp>;
2244 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2245 <&wpesys CLK_WPE_SMI_LARB8>,
2246 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2247 clock-names = "apb", "smi", "gals";
2248 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2249 };
2250
2251 vppsys1: syscon@14f00000 {
2252 compatible = "mediatek,mt8195-vppsys1", "syscon";
2253 reg = <0 0x14f00000 0 0x1000>;
2254 #clock-cells = <1>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]2255 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2256 };
2257
2258 mutex@14f01000 {
2259 compatible = "mediatek,mt8195-vpp-mutex";
2260 reg = <0 0x14f01000 0 0x1000>;
2261 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2262 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2263 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
2264 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2265 };
2266
2267 larb5: larb@14f02000 {
2268 compatible = "mediatek,mt8195-smi-larb";
2269 reg = <0 0x14f02000 0 0x1000>;
2270 mediatek,larb-id = <5>;
2271 mediatek,smi = <&smi_common_vdo>;
2272 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2273 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2274 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2275 clock-names = "apb", "smi", "gals";
2276 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2277 };
2278
2279 larb6: larb@14f03000 {
2280 compatible = "mediatek,mt8195-smi-larb";
2281 reg = <0 0x14f03000 0 0x1000>;
2282 mediatek,larb-id = <6>;
2283 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2284 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2285 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2286 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2287 clock-names = "apb", "smi", "gals";
2288 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2289 };
2290
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2291 display@14f06000 {
2292 compatible = "mediatek,mt8195-mdp3-split";
2293 reg = <0 0x14f06000 0 0x1000>;
2294 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2295 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
2296 <&vppsys1 CLK_VPP1_HDMI_META>,
2297 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
2298 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2299 };
2300
2301 display@14f07000 {
2302 compatible = "mediatek,mt8195-mdp3-tcc";
2303 reg = <0 0x14f07000 0 0x1000>;
2304 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2305 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
2306 };
2307
2308 dma-controller@14f08000 {
2309 compatible = "mediatek,mt8195-mdp3-rdma";
2310 reg = <0 0x14f08000 0 0x1000>;
2311 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2312 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2313 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
2314 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
2315 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
2316 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2317 #dma-cells = <1>;
2318 };
2319
2320 dma-controller@14f09000 {
2321 compatible = "mediatek,mt8195-mdp3-rdma";
2322 reg = <0 0x14f09000 0 0x1000>;
2323 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2324 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2325 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
2326 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
2327 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
2328 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2329 #dma-cells = <1>;
2330 };
2331
2332 dma-controller@14f0a000 {
2333 compatible = "mediatek,mt8195-mdp3-rdma";
2334 reg = <0 0x14f0a000 0 0x1000>;
2335 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2336 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2337 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
2338 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
2339 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
2340 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2341 #dma-cells = <1>;
2342 };
2343
2344 display@14f0b000 {
2345 compatible = "mediatek,mt8195-mdp3-fg";
2346 reg = <0 0x14f0b000 0 0x1000>;
2347 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2348 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
2349 };
2350
2351 display@14f0c000 {
2352 compatible = "mediatek,mt8195-mdp3-fg";
2353 reg = <0 0x14f0c000 0 0x1000>;
2354 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2355 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
2356 };
2357
2358 display@14f0d000 {
2359 compatible = "mediatek,mt8195-mdp3-fg";
2360 reg = <0 0x14f0d000 0 0x1000>;
2361 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2362 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
2363 };
2364
2365 display@14f0e000 {
2366 compatible = "mediatek,mt8195-mdp3-hdr";
2367 reg = <0 0x14f0e000 0 0x1000>;
2368 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2369 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
2370 };
2371
2372 display@14f0f000 {
2373 compatible = "mediatek,mt8195-mdp3-hdr";
2374 reg = <0 0x14f0f000 0 0x1000>;
2375 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2376 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
2377 };
2378
2379 display@14f10000 {
2380 compatible = "mediatek,mt8195-mdp3-hdr";
2381 reg = <0 0x14f10000 0 0x1000>;
2382 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2383 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
2384 };
2385
2386 display@14f11000 {
2387 compatible = "mediatek,mt8195-mdp3-aal";
2388 reg = <0 0x14f11000 0 0x1000>;
2389 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
2390 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2391 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
2392 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2393 };
2394
2395 display@14f12000 {
2396 compatible = "mediatek,mt8195-mdp3-aal";
2397 reg = <0 0x14f12000 0 0x1000>;
2398 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
2399 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2400 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
2401 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2402 };
2403
2404 display@14f13000 {
2405 compatible = "mediatek,mt8195-mdp3-aal";
2406 reg = <0 0x14f13000 0 0x1000>;
2407 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
2408 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2409 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
2410 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2411 };
2412
2413 display@14f14000 {
2414 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2415 reg = <0 0x14f14000 0 0x1000>;
2416 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2417 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2418 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
2419 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
2420 };
2421
2422 display@14f15000 {
2423 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2424 reg = <0 0x14f15000 0 0x1000>;
2425 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2426 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2427 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
2428 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
2429 };
2430
2431 display@14f16000 {
2432 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2433 reg = <0 0x14f16000 0 0x1000>;
2434 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2435 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2436 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
2437 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
2438 };
2439
2440 display@14f17000 {
2441 compatible = "mediatek,mt8195-mdp3-tdshp";
2442 reg = <0 0x14f17000 0 0x1000>;
2443 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2444 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
2445 };
2446
2447 display@14f18000 {
2448 compatible = "mediatek,mt8195-mdp3-tdshp";
2449 reg = <0 0x14f18000 0 0x1000>;
2450 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2451 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
2452 };
2453
2454 display@14f19000 {
2455 compatible = "mediatek,mt8195-mdp3-tdshp";
2456 reg = <0 0x14f19000 0 0x1000>;
2457 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2458 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
2459 };
2460
2461 display@14f1a000 {
2462 compatible = "mediatek,mt8195-mdp3-merge";
2463 reg = <0 0x14f1a000 0 0x1000>;
2464 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2465 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
2466 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2467 };
2468
2469 display@14f1b000 {
2470 compatible = "mediatek,mt8195-mdp3-merge";
2471 reg = <0 0x14f1b000 0 0x1000>;
2472 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2473 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
2474 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2475 };
2476
2477 display@14f1c000 {
2478 compatible = "mediatek,mt8195-mdp3-color";
2479 reg = <0 0x14f1c000 0 0x1000>;
2480 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
2481 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2482 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
2483 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2484 };
2485
2486 display@14f1d000 {
2487 compatible = "mediatek,mt8195-mdp3-color";
2488 reg = <0 0x14f1d000 0 0x1000>;
2489 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2490 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
2491 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
2492 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2493 };
2494
2495 display@14f1e000 {
2496 compatible = "mediatek,mt8195-mdp3-color";
2497 reg = <0 0x14f1e000 0 0x1000>;
2498 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
2499 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2500 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
2501 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2502 };
2503
2504 display@14f1f000 {
2505 compatible = "mediatek,mt8195-mdp3-ovl";
2506 reg = <0 0x14f1f000 0 0x1000>;
2507 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
2508 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2509 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
2510 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2511 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
2512 };
2513
2514 display@14f20000 {
2515 compatible = "mediatek,mt8195-mdp3-padding";
2516 reg = <0 0x14f20000 0 0x1000>;
2517 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2518 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
2519 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2520 };
2521
2522 display@14f21000 {
2523 compatible = "mediatek,mt8195-mdp3-padding";
2524 reg = <0 0x14f21000 0 0x1000>;
2525 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2526 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
2527 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2528 };
2529
2530 display@14f22000 {
2531 compatible = "mediatek,mt8195-mdp3-padding";
2532 reg = <0 0x14f22000 0 0x1000>;
2533 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2534 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
2535 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2536 };
2537
2538 dma-controller@14f23000 {
2539 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2540 reg = <0 0x14f23000 0 0x1000>;
2541 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2542 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2543 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
2544 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
2545 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
2546 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2547 #dma-cells = <1>;
2548 };
2549
2550 dma-controller@14f24000 {
2551 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2552 reg = <0 0x14f24000 0 0x1000>;
2553 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2554 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2555 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
2556 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
2557 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
2558 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2559 #dma-cells = <1>;
2560 };
2561
2562 dma-controller@14f25000 {
2563 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2564 reg = <0 0x14f25000 0 0x1000>;
2565 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2566 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2567 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
2568 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
2569 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
2570 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2571 #dma-cells = <1>;
2572 };
2573
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2574 imgsys: clock-controller@15000000 {
2575 compatible = "mediatek,mt8195-imgsys";
2576 reg = <0 0x15000000 0 0x1000>;
2577 #clock-cells = <1>;
2578 };
2579
2580 larb9: larb@15001000 {
2581 compatible = "mediatek,mt8195-smi-larb";
2582 reg = <0 0x15001000 0 0x1000>;
2583 mediatek,larb-id = <9>;
2584 mediatek,smi = <&smi_sub_common_img1_3x1>;
2585 clocks = <&imgsys CLK_IMG_LARB9>,
2586 <&imgsys CLK_IMG_LARB9>,
2587 <&imgsys CLK_IMG_GALS>;
2588 clock-names = "apb", "smi", "gals";
2589 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2590 };
2591
2592 smi_sub_common_img0_3x1: smi@15002000 {
2593 compatible = "mediatek,mt8195-smi-sub-common";
2594 reg = <0 0x15002000 0 0x1000>;
2595 clocks = <&imgsys CLK_IMG_IPE>,
2596 <&imgsys CLK_IMG_IPE>,
2597 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2598 clock-names = "apb", "smi", "gals0";
2599 mediatek,smi = <&smi_common_vpp>;
2600 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2601 };
2602
2603 smi_sub_common_img1_3x1: smi@15003000 {
2604 compatible = "mediatek,mt8195-smi-sub-common";
2605 reg = <0 0x15003000 0 0x1000>;
2606 clocks = <&imgsys CLK_IMG_LARB9>,
2607 <&imgsys CLK_IMG_LARB9>,
2608 <&imgsys CLK_IMG_GALS>;
2609 clock-names = "apb", "smi", "gals0";
2610 mediatek,smi = <&smi_common_vdo>;
2611 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2612 };
2613
2614 imgsys1_dip_top: clock-controller@15110000 {
2615 compatible = "mediatek,mt8195-imgsys1_dip_top";
2616 reg = <0 0x15110000 0 0x1000>;
2617 #clock-cells = <1>;
2618 };
2619
2620 larb10: larb@15120000 {
2621 compatible = "mediatek,mt8195-smi-larb";
2622 reg = <0 0x15120000 0 0x1000>;
2623 mediatek,larb-id = <10>;
2624 mediatek,smi = <&smi_sub_common_img1_3x1>;
2625 clocks = <&imgsys CLK_IMG_DIP0>,
2626 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2627 clock-names = "apb", "smi";
2628 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2629 };
2630
2631 imgsys1_dip_nr: clock-controller@15130000 {
2632 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2633 reg = <0 0x15130000 0 0x1000>;
2634 #clock-cells = <1>;
2635 };
2636
2637 imgsys1_wpe: clock-controller@15220000 {
2638 compatible = "mediatek,mt8195-imgsys1_wpe";
2639 reg = <0 0x15220000 0 0x1000>;
2640 #clock-cells = <1>;
2641 };
2642
2643 larb11: larb@15230000 {
2644 compatible = "mediatek,mt8195-smi-larb";
2645 reg = <0 0x15230000 0 0x1000>;
2646 mediatek,larb-id = <11>;
2647 mediatek,smi = <&smi_sub_common_img1_3x1>;
2648 clocks = <&imgsys CLK_IMG_WPE0>,
2649 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2650 clock-names = "apb", "smi";
2651 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2652 };
2653
2654 ipesys: clock-controller@15330000 {
2655 compatible = "mediatek,mt8195-ipesys";
2656 reg = <0 0x15330000 0 0x1000>;
2657 #clock-cells = <1>;
2658 };
2659
2660 larb12: larb@15340000 {
2661 compatible = "mediatek,mt8195-smi-larb";
2662 reg = <0 0x15340000 0 0x1000>;
2663 mediatek,larb-id = <12>;
2664 mediatek,smi = <&smi_sub_common_img0_3x1>;
2665 clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2666 <&ipesys CLK_IPE_SMI_LARB12>;
2667 clock-names = "apb", "smi";
2668 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2669 };
2670
2671 camsys: clock-controller@16000000 {
2672 compatible = "mediatek,mt8195-camsys";
2673 reg = <0 0x16000000 0 0x1000>;
2674 #clock-cells = <1>;
2675 };
2676
2677 larb13: larb@16001000 {
2678 compatible = "mediatek,mt8195-smi-larb";
2679 reg = <0 0x16001000 0 0x1000>;
2680 mediatek,larb-id = <13>;
2681 mediatek,smi = <&smi_sub_common_cam_4x1>;
2682 clocks = <&camsys CLK_CAM_LARB13>,
2683 <&camsys CLK_CAM_LARB13>,
2684 <&camsys CLK_CAM_CAM2MM0_GALS>;
2685 clock-names = "apb", "smi", "gals";
2686 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2687 };
2688
2689 larb14: larb@16002000 {
2690 compatible = "mediatek,mt8195-smi-larb";
2691 reg = <0 0x16002000 0 0x1000>;
2692 mediatek,larb-id = <14>;
2693 mediatek,smi = <&smi_sub_common_cam_7x1>;
2694 clocks = <&camsys CLK_CAM_LARB14>,
2695 <&camsys CLK_CAM_LARB14>;
2696 clock-names = "apb", "smi";
2697 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2698 };
2699
2700 smi_sub_common_cam_4x1: smi@16004000 {
2701 compatible = "mediatek,mt8195-smi-sub-common";
2702 reg = <0 0x16004000 0 0x1000>;
2703 clocks = <&camsys CLK_CAM_LARB13>,
2704 <&camsys CLK_CAM_LARB13>,
2705 <&camsys CLK_CAM_CAM2MM0_GALS>;
2706 clock-names = "apb", "smi", "gals0";
2707 mediatek,smi = <&smi_common_vdo>;
2708 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2709 };
2710
2711 smi_sub_common_cam_7x1: smi@16005000 {
2712 compatible = "mediatek,mt8195-smi-sub-common";
2713 reg = <0 0x16005000 0 0x1000>;
2714 clocks = <&camsys CLK_CAM_LARB14>,
2715 <&camsys CLK_CAM_CAM2MM1_GALS>,
2716 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2717 clock-names = "apb", "smi", "gals0";
2718 mediatek,smi = <&smi_common_vpp>;
2719 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2720 };
2721
2722 larb16: larb@16012000 {
2723 compatible = "mediatek,mt8195-smi-larb";
2724 reg = <0 0x16012000 0 0x1000>;
2725 mediatek,larb-id = <16>;
2726 mediatek,smi = <&smi_sub_common_cam_7x1>;
2727 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2728 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2729 clock-names = "apb", "smi";
2730 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2731 };
2732
2733 larb17: larb@16013000 {
2734 compatible = "mediatek,mt8195-smi-larb";
2735 reg = <0 0x16013000 0 0x1000>;
2736 mediatek,larb-id = <17>;
2737 mediatek,smi = <&smi_sub_common_cam_4x1>;
2738 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2739 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2740 clock-names = "apb", "smi";
2741 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2742 };
2743
2744 larb27: larb@16014000 {
2745 compatible = "mediatek,mt8195-smi-larb";
2746 reg = <0 0x16014000 0 0x1000>;
2747 mediatek,larb-id = <27>;
2748 mediatek,smi = <&smi_sub_common_cam_7x1>;
2749 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2750 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2751 clock-names = "apb", "smi";
2752 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2753 };
2754
2755 larb28: larb@16015000 {
2756 compatible = "mediatek,mt8195-smi-larb";
2757 reg = <0 0x16015000 0 0x1000>;
2758 mediatek,larb-id = <28>;
2759 mediatek,smi = <&smi_sub_common_cam_4x1>;
2760 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2761 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2762 clock-names = "apb", "smi";
2763 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2764 };
2765
2766 camsys_rawa: clock-controller@1604f000 {
2767 compatible = "mediatek,mt8195-camsys_rawa";
2768 reg = <0 0x1604f000 0 0x1000>;
2769 #clock-cells = <1>;
2770 };
2771
2772 camsys_yuva: clock-controller@1606f000 {
2773 compatible = "mediatek,mt8195-camsys_yuva";
2774 reg = <0 0x1606f000 0 0x1000>;
2775 #clock-cells = <1>;
2776 };
2777
2778 camsys_rawb: clock-controller@1608f000 {
2779 compatible = "mediatek,mt8195-camsys_rawb";
2780 reg = <0 0x1608f000 0 0x1000>;
2781 #clock-cells = <1>;
2782 };
2783
2784 camsys_yuvb: clock-controller@160af000 {
2785 compatible = "mediatek,mt8195-camsys_yuvb";
2786 reg = <0 0x160af000 0 0x1000>;
2787 #clock-cells = <1>;
2788 };
2789
2790 camsys_mraw: clock-controller@16140000 {
2791 compatible = "mediatek,mt8195-camsys_mraw";
2792 reg = <0 0x16140000 0 0x1000>;
2793 #clock-cells = <1>;
2794 };
2795
2796 larb25: larb@16141000 {
2797 compatible = "mediatek,mt8195-smi-larb";
2798 reg = <0 0x16141000 0 0x1000>;
2799 mediatek,larb-id = <25>;
2800 mediatek,smi = <&smi_sub_common_cam_4x1>;
2801 clocks = <&camsys CLK_CAM_LARB13>,
2802 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2803 <&camsys CLK_CAM_CAM2MM0_GALS>;
2804 clock-names = "apb", "smi", "gals";
2805 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2806 };
2807
2808 larb26: larb@16142000 {
2809 compatible = "mediatek,mt8195-smi-larb";
2810 reg = <0 0x16142000 0 0x1000>;
2811 mediatek,larb-id = <26>;
2812 mediatek,smi = <&smi_sub_common_cam_7x1>;
2813 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2814 <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2815 clock-names = "apb", "smi";
2816 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2817
2818 };
2819
2820 ccusys: clock-controller@17200000 {
2821 compatible = "mediatek,mt8195-ccusys";
2822 reg = <0 0x17200000 0 0x1000>;
2823 #clock-cells = <1>;
2824 };
2825
2826 larb18: larb@17201000 {
2827 compatible = "mediatek,mt8195-smi-larb";
2828 reg = <0 0x17201000 0 0x1000>;
2829 mediatek,larb-id = <18>;
2830 mediatek,smi = <&smi_sub_common_cam_7x1>;
2831 clocks = <&ccusys CLK_CCU_LARB18>,
2832 <&ccusys CLK_CCU_LARB18>;
2833 clock-names = "apb", "smi";
2834 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2835 };
2836
2837 video-codec@18000000 {
2838 compatible = "mediatek,mt8195-vcodec-dec";
2839 mediatek,scp = <&scp>;
2840 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
2841 #address-cells = <2>;
2842 #size-cells = <2>;
2843 reg = <0 0x18000000 0 0x1000>,
2844 <0 0x18004000 0 0x1000>;
2845 ranges = <0 0 0 0x18000000 0 0x26000>;
2846
2847 video-codec@2000 {
2848 compatible = "mediatek,mtk-vcodec-lat-soc";
2849 reg = <0 0x2000 0 0x800>;
2850 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
2851 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
2852 clocks = <&topckgen CLK_TOP_VDEC>,
2853 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2854 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2855 <&topckgen CLK_TOP_UNIVPLL_D4>;
2856 clock-names = "sel", "vdec", "lat", "top";
2857 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2858 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2859 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2860 };
2861
2862 video-codec@10000 {
2863 compatible = "mediatek,mtk-vcodec-lat";
2864 reg = <0 0x10000 0 0x800>;
2865 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
2866 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
2867 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
2868 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
2869 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
2870 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
2871 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
2872 clocks = <&topckgen CLK_TOP_VDEC>,
2873 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2874 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2875 <&topckgen CLK_TOP_UNIVPLL_D4>;
2876 clock-names = "sel", "vdec", "lat", "top";
2877 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2878 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2879 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2880 };
2881
2882 video-codec@25000 {
2883 compatible = "mediatek,mtk-vcodec-core";
2884 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */
2885 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
2886 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
2887 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
2888 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
2889 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
2890 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
2891 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
2892 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
2893 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
2894 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
2895 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
2896 clocks = <&topckgen CLK_TOP_VDEC>,
2897 <&vdecsys CLK_VDEC_VDEC>,
2898 <&vdecsys CLK_VDEC_LAT>,
2899 <&topckgen CLK_TOP_UNIVPLL_D4>;
2900 clock-names = "sel", "vdec", "lat", "top";
2901 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2902 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2903 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2904 };
2905 };
2906
2907 larb24: larb@1800d000 {
2908 compatible = "mediatek,mt8195-smi-larb";
2909 reg = <0 0x1800d000 0 0x1000>;
2910 mediatek,larb-id = <24>;
2911 mediatek,smi = <&smi_common_vdo>;
2912 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2913 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2914 clock-names = "apb", "smi";
2915 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2916 };
2917
2918 larb23: larb@1800e000 {
2919 compatible = "mediatek,mt8195-smi-larb";
2920 reg = <0 0x1800e000 0 0x1000>;
2921 mediatek,larb-id = <23>;
2922 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2923 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2924 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2925 clock-names = "apb", "smi";
2926 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2927 };
2928
2929 vdecsys_soc: clock-controller@1800f000 {
2930 compatible = "mediatek,mt8195-vdecsys_soc";
2931 reg = <0 0x1800f000 0 0x1000>;
2932 #clock-cells = <1>;
2933 };
2934
2935 larb21: larb@1802e000 {
2936 compatible = "mediatek,mt8195-smi-larb";
2937 reg = <0 0x1802e000 0 0x1000>;
2938 mediatek,larb-id = <21>;
2939 mediatek,smi = <&smi_common_vdo>;
2940 clocks = <&vdecsys CLK_VDEC_LARB1>,
2941 <&vdecsys CLK_VDEC_LARB1>;
2942 clock-names = "apb", "smi";
2943 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2944 };
2945
2946 vdecsys: clock-controller@1802f000 {
2947 compatible = "mediatek,mt8195-vdecsys";
2948 reg = <0 0x1802f000 0 0x1000>;
2949 #clock-cells = <1>;
2950 };
2951
2952 larb22: larb@1803e000 {
2953 compatible = "mediatek,mt8195-smi-larb";
2954 reg = <0 0x1803e000 0 0x1000>;
2955 mediatek,larb-id = <22>;
2956 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2957 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2958 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2959 clock-names = "apb", "smi";
2960 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2961 };
2962
2963 vdecsys_core1: clock-controller@1803f000 {
2964 compatible = "mediatek,mt8195-vdecsys_core1";
2965 reg = <0 0x1803f000 0 0x1000>;
2966 #clock-cells = <1>;
2967 };
2968
2969 apusys_pll: clock-controller@190f3000 {
2970 compatible = "mediatek,mt8195-apusys_pll";
2971 reg = <0 0x190f3000 0 0x1000>;
2972 #clock-cells = <1>;
2973 };
2974
2975 vencsys: clock-controller@1a000000 {
2976 compatible = "mediatek,mt8195-vencsys";
2977 reg = <0 0x1a000000 0 0x1000>;
2978 #clock-cells = <1>;
2979 };
2980
2981 larb19: larb@1a010000 {
2982 compatible = "mediatek,mt8195-smi-larb";
2983 reg = <0 0x1a010000 0 0x1000>;
2984 mediatek,larb-id = <19>;
2985 mediatek,smi = <&smi_common_vdo>;
2986 clocks = <&vencsys CLK_VENC_VENC>,
2987 <&vencsys CLK_VENC_GALS>;
2988 clock-names = "apb", "smi";
2989 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2990 };
2991
2992 venc: video-codec@1a020000 {
2993 compatible = "mediatek,mt8195-vcodec-enc";
2994 reg = <0 0x1a020000 0 0x10000>;
2995 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
2996 <&iommu_vdo M4U_PORT_L19_VENC_REC>,
2997 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
2998 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
2999 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
3000 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
3001 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
3002 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
3003 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
3004 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
3005 mediatek,scp = <&scp>;
3006 clocks = <&vencsys CLK_VENC_VENC>;
3007 clock-names = "venc_sel";
3008 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3009 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3010 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3011 #address-cells = <2>;
3012 #size-cells = <2>;
3013 };
3014
3015 jpgdec-master {
3016 compatible = "mediatek,mt8195-jpgdec";
3017 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3018 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3019 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3020 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3021 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3022 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3023 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3024 #address-cells = <2>;
3025 #size-cells = <2>;
3026 ranges;
3027
3028 jpgdec@1a040000 {
3029 compatible = "mediatek,mt8195-jpgdec-hw";
3030 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
3031 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3032 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3033 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3034 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3035 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3036 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3037 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
3038 clocks = <&vencsys CLK_VENC_JPGDEC>;
3039 clock-names = "jpgdec";
3040 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3041 };
3042
3043 jpgdec@1a050000 {
3044 compatible = "mediatek,mt8195-jpgdec-hw";
3045 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
3046 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3047 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3048 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3049 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3050 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3051 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3052 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
3053 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
3054 clock-names = "jpgdec";
3055 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3056 };
3057
3058 jpgdec@1b040000 {
3059 compatible = "mediatek,mt8195-jpgdec-hw";
3060 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
3061 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
3062 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
3063 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
3064 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
3065 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
3066 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
3067 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
3068 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
3069 clock-names = "jpgdec";
3070 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3071 };
3072 };
3073
3074 vencsys_core1: clock-controller@1b000000 {
3075 compatible = "mediatek,mt8195-vencsys_core1";
3076 reg = <0 0x1b000000 0 0x1000>;
3077 #clock-cells = <1>;
3078 };
3079
3080 vdosys0: syscon@1c01a000 {
3081 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3082 reg = <0 0x1c01a000 0 0x1000>;
3083 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3084 #clock-cells = <1>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]3085 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3086 };
3087
3088
3089 jpgenc-master {
3090 compatible = "mediatek,mt8195-jpgenc";
3091 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3092 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3093 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3094 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3095 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3096 #address-cells = <2>;
3097 #size-cells = <2>;
3098 ranges;
3099
3100 jpgenc@1a030000 {
3101 compatible = "mediatek,mt8195-jpgenc-hw";
3102 reg = <0 0x1a030000 0 0x10000>;
3103 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
3104 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
3105 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
3106 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
3107 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
3108 clocks = <&vencsys CLK_VENC_JPGENC>;
3109 clock-names = "jpgenc";
3110 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3111 };
3112
3113 jpgenc@1b030000 {
3114 compatible = "mediatek,mt8195-jpgenc-hw";
3115 reg = <0 0x1b030000 0 0x10000>;
3116 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3117 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3118 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3119 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3120 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
3121 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
3122 clock-names = "jpgenc";
3123 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3124 };
3125 };
3126
3127 larb20: larb@1b010000 {
3128 compatible = "mediatek,mt8195-smi-larb";
3129 reg = <0 0x1b010000 0 0x1000>;
3130 mediatek,larb-id = <20>;
3131 mediatek,smi = <&smi_common_vpp>;
3132 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
3133 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
3134 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3135 clock-names = "apb", "smi", "gals";
3136 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3137 };
3138
3139 ovl0: ovl@1c000000 {
3140 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
3141 reg = <0 0x1c000000 0 0x1000>;
3142 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
3143 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3144 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
3145 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
3146 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3147 };
3148
3149 rdma0: rdma@1c002000 {
3150 compatible = "mediatek,mt8195-disp-rdma";
3151 reg = <0 0x1c002000 0 0x1000>;
3152 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
3153 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3154 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
3155 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
3156 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3157 };
3158
3159 color0: color@1c003000 {
3160 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3161 reg = <0 0x1c003000 0 0x1000>;
3162 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
3163 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3164 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
3165 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3166 };
3167
3168 ccorr0: ccorr@1c004000 {
3169 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3170 reg = <0 0x1c004000 0 0x1000>;
3171 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
3172 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3173 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
3174 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3175 };
3176
3177 aal0: aal@1c005000 {
3178 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3179 reg = <0 0x1c005000 0 0x1000>;
3180 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
3181 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3182 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
3183 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3184 };
3185
3186 gamma0: gamma@1c006000 {
3187 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3188 reg = <0 0x1c006000 0 0x1000>;
3189 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
3190 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3191 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
3192 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3193 };
3194
3195 dither0: dither@1c007000 {
3196 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3197 reg = <0 0x1c007000 0 0x1000>;
3198 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
3199 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3200 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
3201 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3202 };
3203
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3204 dsi0: dsi@1c008000 {
3205 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3206 reg = <0 0x1c008000 0 0x1000>;
3207 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
3208 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3209 clocks = <&vdosys0 CLK_VDO0_DSI0>,
3210 <&vdosys0 CLK_VDO0_DSI0_DSI>,
3211 <&mipi_tx0>;
3212 clock-names = "engine", "digital", "hs";
3213 phys = <&mipi_tx0>;
3214 phy-names = "dphy";
3215 status = "disabled";
3216 };
3217
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3218 dsc0: dsc@1c009000 {
3219 compatible = "mediatek,mt8195-disp-dsc";
3220 reg = <0 0x1c009000 0 0x1000>;
3221 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
3222 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3223 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
3224 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3225 };
3226
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3227 dsi1: dsi@1c012000 {
3228 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3229 reg = <0 0x1c012000 0 0x1000>;
3230 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
3231 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3232 clocks = <&vdosys0 CLK_VDO0_DSI1>,
3233 <&vdosys0 CLK_VDO0_DSI1_DSI>,
3234 <&mipi_tx1>;
3235 clock-names = "engine", "digital", "hs";
3236 phys = <&mipi_tx1>;
3237 phy-names = "dphy";
3238 status = "disabled";
3239 };
3240
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3241 merge0: merge@1c014000 {
3242 compatible = "mediatek,mt8195-disp-merge";
3243 reg = <0 0x1c014000 0 0x1000>;
3244 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
3245 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3246 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3247 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3248 };
3249
3250 dp_intf0: dp-intf@1c015000 {
3251 compatible = "mediatek,mt8195-dp-intf";
3252 reg = <0 0x1c015000 0 0x1000>;
3253 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
3254 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
3255 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
3256 <&apmixedsys CLK_APMIXED_TVDPLL1>;
3257 clock-names = "engine", "pixel", "pll";
3258 status = "disabled";
3259 };
3260
3261 mutex: mutex@1c016000 {
3262 compatible = "mediatek,mt8195-disp-mutex";
3263 reg = <0 0x1c016000 0 0x1000>;
3264 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3265 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3266 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]3267 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3268 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3269 };
3270
3271 larb0: larb@1c018000 {
3272 compatible = "mediatek,mt8195-smi-larb";
3273 reg = <0 0x1c018000 0 0x1000>;
3274 mediatek,larb-id = <0>;
3275 mediatek,smi = <&smi_common_vdo>;
3276 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3277 <&vdosys0 CLK_VDO0_SMI_LARB>,
3278 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3279 clock-names = "apb", "smi", "gals";
3280 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3281 };
3282
3283 larb1: larb@1c019000 {
3284 compatible = "mediatek,mt8195-smi-larb";
3285 reg = <0 0x1c019000 0 0x1000>;
3286 mediatek,larb-id = <1>;
3287 mediatek,smi = <&smi_common_vpp>;
3288 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3289 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3290 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3291 clock-names = "apb", "smi", "gals";
3292 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3293 };
3294
3295 vdosys1: syscon@1c100000 {
3296 compatible = "mediatek,mt8195-vdosys1", "syscon";
3297 reg = <0 0x1c100000 0 0x1000>;
3298 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
3299 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3300 #clock-cells = <1>;
3301 #reset-cells = <1>;
3302 };
3303
3304 smi_common_vdo: smi@1c01b000 {
3305 compatible = "mediatek,mt8195-smi-common-vdo";
3306 reg = <0 0x1c01b000 0 0x1000>;
3307 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
3308 <&vdosys0 CLK_VDO0_SMI_EMI>,
3309 <&vdosys0 CLK_VDO0_SMI_RSI>,
3310 <&vdosys0 CLK_VDO0_SMI_GALS>;
3311 clock-names = "apb", "smi", "gals0", "gals1";
3312 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3313
3314 };
3315
3316 iommu_vdo: iommu@1c01f000 {
3317 compatible = "mediatek,mt8195-iommu-vdo";
3318 reg = <0 0x1c01f000 0 0x1000>;
3319 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
3320 &larb10 &larb11 &larb13 &larb17
3321 &larb19 &larb21 &larb24 &larb25
3322 &larb28>;
3323 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
3324 #iommu-cells = <1>;
3325 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
3326 clock-names = "bclk";
3327 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3328 };
3329
3330 mutex1: mutex@1c101000 {
3331 compatible = "mediatek,mt8195-disp-mutex";
3332 reg = <0 0x1c101000 0 0x1000>;
3333 reg-names = "vdo1_mutex";
3334 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
3335 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3336 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3337 clock-names = "vdo1_mutex";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]3338 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3339 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3340 };
3341
3342 larb2: larb@1c102000 {
3343 compatible = "mediatek,mt8195-smi-larb";
3344 reg = <0 0x1c102000 0 0x1000>;
3345 mediatek,larb-id = <2>;
3346 mediatek,smi = <&smi_common_vdo>;
3347 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3348 <&vdosys1 CLK_VDO1_SMI_LARB2>,
3349 <&vdosys1 CLK_VDO1_GALS>;
3350 clock-names = "apb", "smi", "gals";
3351 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3352 };
3353
3354 larb3: larb@1c103000 {
3355 compatible = "mediatek,mt8195-smi-larb";
3356 reg = <0 0x1c103000 0 0x1000>;
3357 mediatek,larb-id = <3>;
3358 mediatek,smi = <&smi_common_vpp>;
3359 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3360 <&vdosys1 CLK_VDO1_GALS>,
3361 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3362 clock-names = "apb", "smi", "gals";
3363 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3364 };
3365
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3366 vdo1_rdma0: dma-controller@1c104000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3367 compatible = "mediatek,mt8195-vdo1-rdma";
3368 reg = <0 0x1c104000 0 0x1000>;
3369 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
3370 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
3371 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3372 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
3373 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3374 #dma-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3375 };
3376
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3377 vdo1_rdma1: dma-controller@1c105000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3378 compatible = "mediatek,mt8195-vdo1-rdma";
3379 reg = <0 0x1c105000 0 0x1000>;
3380 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
3381 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
3382 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3383 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
3384 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3385 #dma-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3386 };
3387
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3388 vdo1_rdma2: dma-controller@1c106000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3389 compatible = "mediatek,mt8195-vdo1-rdma";
3390 reg = <0 0x1c106000 0 0x1000>;
3391 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
3392 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
3393 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3394 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
3395 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3396 #dma-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3397 };
3398
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3399 vdo1_rdma3: dma-controller@1c107000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3400 compatible = "mediatek,mt8195-vdo1-rdma";
3401 reg = <0 0x1c107000 0 0x1000>;
3402 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
3403 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
3404 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3405 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
3406 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3407 #dma-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3408 };
3409
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3410 vdo1_rdma4: dma-controller@1c108000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3411 compatible = "mediatek,mt8195-vdo1-rdma";
3412 reg = <0 0x1c108000 0 0x1000>;
3413 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
3414 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
3415 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3416 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
3417 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3418 #dma-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3419 };
3420
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3421 vdo1_rdma5: dma-controller@1c109000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3422 compatible = "mediatek,mt8195-vdo1-rdma";
3423 reg = <0 0x1c109000 0 0x1000>;
3424 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
3425 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
3426 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3427 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
3428 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3429 #dma-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3430 };
3431
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3432 vdo1_rdma6: dma-controller@1c10a000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3433 compatible = "mediatek,mt8195-vdo1-rdma";
3434 reg = <0 0x1c10a000 0 0x1000>;
3435 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
3436 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
3437 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3438 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
3439 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3440 #dma-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3441 };
3442
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3443 vdo1_rdma7: dma-controller@1c10b000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3444 compatible = "mediatek,mt8195-vdo1-rdma";
3445 reg = <0 0x1c10b000 0 0x1000>;
3446 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
3447 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
3448 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3449 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
3450 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3451 #dma-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3452 };
3453
3454 merge1: vpp-merge@1c10c000 {
3455 compatible = "mediatek,mt8195-disp-merge";
3456 reg = <0 0x1c10c000 0 0x1000>;
3457 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
3458 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
3459 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
3460 clock-names = "merge","merge_async";
3461 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3462 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3463 mediatek,merge-mute;
3464 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
3465 };
3466
3467 merge2: vpp-merge@1c10d000 {
3468 compatible = "mediatek,mt8195-disp-merge";
3469 reg = <0 0x1c10d000 0 0x1000>;
3470 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
3471 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
3472 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
3473 clock-names = "merge","merge_async";
3474 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3475 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3476 mediatek,merge-mute;
3477 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
3478 };
3479
3480 merge3: vpp-merge@1c10e000 {
3481 compatible = "mediatek,mt8195-disp-merge";
3482 reg = <0 0x1c10e000 0 0x1000>;
3483 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
3484 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
3485 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
3486 clock-names = "merge","merge_async";
3487 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3488 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3489 mediatek,merge-mute;
3490 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
3491 };
3492
3493 merge4: vpp-merge@1c10f000 {
3494 compatible = "mediatek,mt8195-disp-merge";
3495 reg = <0 0x1c10f000 0 0x1000>;
3496 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
3497 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
3498 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
3499 clock-names = "merge","merge_async";
3500 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3501 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3502 mediatek,merge-mute;
3503 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3504 };
3505
3506 merge5: vpp-merge@1c110000 {
3507 compatible = "mediatek,mt8195-disp-merge";
3508 reg = <0 0x1c110000 0 0x1000>;
3509 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
3510 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3511 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3512 clock-names = "merge","merge_async";
3513 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3514 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3515 mediatek,merge-fifo-en;
3516 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3517 };
3518
3519 dp_intf1: dp-intf@1c113000 {
3520 compatible = "mediatek,mt8195-dp-intf";
3521 reg = <0 0x1c113000 0 0x1000>;
3522 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3523 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3524 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3525 <&vdosys1 CLK_VDO1_DPINTF>,
3526 <&apmixedsys CLK_APMIXED_TVDPLL2>;
3527 clock-names = "engine", "pixel", "pll";
3528 status = "disabled";
3529 };
3530
3531 ethdr0: hdr-engine@1c114000 {
3532 compatible = "mediatek,mt8195-disp-ethdr";
3533 reg = <0 0x1c114000 0 0x1000>,
3534 <0 0x1c115000 0 0x1000>,
3535 <0 0x1c117000 0 0x1000>,
3536 <0 0x1c119000 0 0x1000>,
3537 <0 0x1c11a000 0 0x1000>,
3538 <0 0x1c11b000 0 0x1000>,
3539 <0 0x1c11c000 0 0x1000>;
3540 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3541 "vdo_be", "adl_ds";
3542 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3543 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
3544 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
3545 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
3546 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
3547 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
3548 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
3549 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
3550 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
3551 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
3552 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
3553 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
3554 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
3555 <&vdosys1 CLK_VDO1_26M_SLOW>,
3556 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
3557 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
3558 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
3559 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
3560 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
3561 <&topckgen CLK_TOP_ETHDR>;
3562 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3563 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
3564 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
3565 "ethdr_top";
3566 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3567 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
3568 <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
3569 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
3570 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
3571 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
3572 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
3573 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
3574 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
3575 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3576 "gfx_fe1_async", "vdo_be_async";
3577 };
3578
3579 edp_tx: edp-tx@1c500000 {
3580 compatible = "mediatek,mt8195-edp-tx";
3581 reg = <0 0x1c500000 0 0x8000>;
3582 nvmem-cells = <&dp_calibration>;
3583 nvmem-cell-names = "dp_calibration_data";
3584 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3585 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
3586 max-linkrate-mhz = <8100>;
3587 status = "disabled";
3588 };
3589
3590 dp_tx: dp-tx@1c600000 {
3591 compatible = "mediatek,mt8195-dp-tx";
3592 reg = <0 0x1c600000 0 0x8000>;
3593 nvmem-cells = <&dp_calibration>;
3594 nvmem-cell-names = "dp_calibration_data";
3595 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3596 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
3597 max-linkrate-mhz = <8100>;
3598 status = "disabled";
3599 };
3600 };
3601
3602 thermal_zones: thermal-zones {
3603 cpu0-thermal {
3604 polling-delay = <1000>;
3605 polling-delay-passive = <250>;
3606 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3607
3608 trips {
3609 cpu0_alert: trip-alert {
3610 temperature = <85000>;
3611 hysteresis = <2000>;
3612 type = "passive";
3613 };
3614
3615 cpu0_crit: trip-crit {
3616 temperature = <100000>;
3617 hysteresis = <2000>;
3618 type = "critical";
3619 };
3620 };
3621
3622 cooling-maps {
3623 map0 {
3624 trip = <&cpu0_alert>;
3625 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3626 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3627 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3628 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3629 };
3630 };
3631 };
3632
3633 cpu1-thermal {
3634 polling-delay = <1000>;
3635 polling-delay-passive = <250>;
3636 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3637
3638 trips {
3639 cpu1_alert: trip-alert {
3640 temperature = <85000>;
3641 hysteresis = <2000>;
3642 type = "passive";
3643 };
3644
3645 cpu1_crit: trip-crit {
3646 temperature = <100000>;
3647 hysteresis = <2000>;
3648 type = "critical";
3649 };
3650 };
3651
3652 cooling-maps {
3653 map0 {
3654 trip = <&cpu1_alert>;
3655 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3656 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3659 };
3660 };
3661 };
3662
3663 cpu2-thermal {
3664 polling-delay = <1000>;
3665 polling-delay-passive = <250>;
3666 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3667
3668 trips {
3669 cpu2_alert: trip-alert {
3670 temperature = <85000>;
3671 hysteresis = <2000>;
3672 type = "passive";
3673 };
3674
3675 cpu2_crit: trip-crit {
3676 temperature = <100000>;
3677 hysteresis = <2000>;
3678 type = "critical";
3679 };
3680 };
3681
3682 cooling-maps {
3683 map0 {
3684 trip = <&cpu2_alert>;
3685 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3686 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3687 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3688 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3689 };
3690 };
3691 };
3692
3693 cpu3-thermal {
3694 polling-delay = <1000>;
3695 polling-delay-passive = <250>;
3696 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3697
3698 trips {
3699 cpu3_alert: trip-alert {
3700 temperature = <85000>;
3701 hysteresis = <2000>;
3702 type = "passive";
3703 };
3704
3705 cpu3_crit: trip-crit {
3706 temperature = <100000>;
3707 hysteresis = <2000>;
3708 type = "critical";
3709 };
3710 };
3711
3712 cooling-maps {
3713 map0 {
3714 trip = <&cpu3_alert>;
3715 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3716 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3717 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3718 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3719 };
3720 };
3721 };
3722
3723 cpu4-thermal {
3724 polling-delay = <1000>;
3725 polling-delay-passive = <250>;
3726 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3727
3728 trips {
3729 cpu4_alert: trip-alert {
3730 temperature = <85000>;
3731 hysteresis = <2000>;
3732 type = "passive";
3733 };
3734
3735 cpu4_crit: trip-crit {
3736 temperature = <100000>;
3737 hysteresis = <2000>;
3738 type = "critical";
3739 };
3740 };
3741
3742 cooling-maps {
3743 map0 {
3744 trip = <&cpu4_alert>;
3745 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3746 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3747 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3748 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3749 };
3750 };
3751 };
3752
3753 cpu5-thermal {
3754 polling-delay = <1000>;
3755 polling-delay-passive = <250>;
3756 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3757
3758 trips {
3759 cpu5_alert: trip-alert {
3760 temperature = <85000>;
3761 hysteresis = <2000>;
3762 type = "passive";
3763 };
3764
3765 cpu5_crit: trip-crit {
3766 temperature = <100000>;
3767 hysteresis = <2000>;
3768 type = "critical";
3769 };
3770 };
3771
3772 cooling-maps {
3773 map0 {
3774 trip = <&cpu5_alert>;
3775 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3776 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3779 };
3780 };
3781 };
3782
3783 cpu6-thermal {
3784 polling-delay = <1000>;
3785 polling-delay-passive = <250>;
3786 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3787
3788 trips {
3789 cpu6_alert: trip-alert {
3790 temperature = <85000>;
3791 hysteresis = <2000>;
3792 type = "passive";
3793 };
3794
3795 cpu6_crit: trip-crit {
3796 temperature = <100000>;
3797 hysteresis = <2000>;
3798 type = "critical";
3799 };
3800 };
3801
3802 cooling-maps {
3803 map0 {
3804 trip = <&cpu6_alert>;
3805 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3806 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3807 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3808 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3809 };
3810 };
3811 };
3812
3813 cpu7-thermal {
3814 polling-delay = <1000>;
3815 polling-delay-passive = <250>;
3816 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3817
3818 trips {
3819 cpu7_alert: trip-alert {
3820 temperature = <85000>;
3821 hysteresis = <2000>;
3822 type = "passive";
3823 };
3824
3825 cpu7_crit: trip-crit {
3826 temperature = <100000>;
3827 hysteresis = <2000>;
3828 type = "critical";
3829 };
3830 };
3831
3832 cooling-maps {
3833 map0 {
3834 trip = <&cpu7_alert>;
3835 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3836 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3837 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3838 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3839 };
3840 };
3841 };
3842
3843 vpu0-thermal {
3844 polling-delay = <1000>;
3845 polling-delay-passive = <250>;
3846 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3847
3848 trips {
3849 vpu0_alert: trip-alert {
3850 temperature = <85000>;
3851 hysteresis = <2000>;
3852 type = "passive";
3853 };
3854
3855 vpu0_crit: trip-crit {
3856 temperature = <100000>;
3857 hysteresis = <2000>;
3858 type = "critical";
3859 };
3860 };
3861 };
3862
3863 vpu1-thermal {
3864 polling-delay = <1000>;
3865 polling-delay-passive = <250>;
3866 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3867
3868 trips {
3869 vpu1_alert: trip-alert {
3870 temperature = <85000>;
3871 hysteresis = <2000>;
3872 type = "passive";
3873 };
3874
3875 vpu1_crit: trip-crit {
3876 temperature = <100000>;
3877 hysteresis = <2000>;
3878 type = "critical";
3879 };
3880 };
3881 };
3882
3883 gpu0-thermal {
3884 polling-delay = <1000>;
3885 polling-delay-passive = <250>;
3886 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3887
3888 trips {
3889 gpu0_alert: trip-alert {
3890 temperature = <85000>;
3891 hysteresis = <2000>;
3892 type = "passive";
3893 };
3894
3895 gpu0_crit: trip-crit {
3896 temperature = <100000>;
3897 hysteresis = <2000>;
3898 type = "critical";
3899 };
3900 };
3901 };
3902
3903 gpu1-thermal {
3904 polling-delay = <1000>;
3905 polling-delay-passive = <250>;
3906 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3907
3908 trips {
3909 gpu1_alert: trip-alert {
3910 temperature = <85000>;
3911 hysteresis = <2000>;
3912 type = "passive";
3913 };
3914
3915 gpu1_crit: trip-crit {
3916 temperature = <100000>;
3917 hysteresis = <2000>;
3918 type = "critical";
3919 };
3920 };
3921 };
3922
3923 vdec-thermal {
3924 polling-delay = <1000>;
3925 polling-delay-passive = <250>;
3926 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3927
3928 trips {
3929 vdec_alert: trip-alert {
3930 temperature = <85000>;
3931 hysteresis = <2000>;
3932 type = "passive";
3933 };
3934
3935 vdec_crit: trip-crit {
3936 temperature = <100000>;
3937 hysteresis = <2000>;
3938 type = "critical";
3939 };
3940 };
3941 };
3942
3943 img-thermal {
3944 polling-delay = <1000>;
3945 polling-delay-passive = <250>;
3946 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3947
3948 trips {
3949 img_alert: trip-alert {
3950 temperature = <85000>;
3951 hysteresis = <2000>;
3952 type = "passive";
3953 };
3954
3955 img_crit: trip-crit {
3956 temperature = <100000>;
3957 hysteresis = <2000>;
3958 type = "critical";
3959 };
3960 };
3961 };
3962
3963 infra-thermal {
3964 polling-delay = <1000>;
3965 polling-delay-passive = <250>;
3966 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3967
3968 trips {
3969 infra_alert: trip-alert {
3970 temperature = <85000>;
3971 hysteresis = <2000>;
3972 type = "passive";
3973 };
3974
3975 infra_crit: trip-crit {
3976 temperature = <100000>;
3977 hysteresis = <2000>;
3978 type = "critical";
3979 };
3980 };
3981 };
3982
3983 cam0-thermal {
3984 polling-delay = <1000>;
3985 polling-delay-passive = <250>;
3986 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3987
3988 trips {
3989 cam0_alert: trip-alert {
3990 temperature = <85000>;
3991 hysteresis = <2000>;
3992 type = "passive";
3993 };
3994
3995 cam0_crit: trip-crit {
3996 temperature = <100000>;
3997 hysteresis = <2000>;
3998 type = "critical";
3999 };
4000 };
4001 };
4002
4003 cam1-thermal {
4004 polling-delay = <1000>;
4005 polling-delay-passive = <250>;
4006 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
4007
4008 trips {
4009 cam1_alert: trip-alert {
4010 temperature = <85000>;
4011 hysteresis = <2000>;
4012 type = "passive";
4013 };
4014
4015 cam1_crit: trip-crit {
4016 temperature = <100000>;
4017 hysteresis = <2000>;
4018 type = "critical";
4019 };
4020 };
4021 };
4022 };
4023};