| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2020 NXP |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | |
| 8 | #include "imx8mm-evk.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; |
| 12 | compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; |
| 13 | |
| 14 | leds { |
| 15 | pinctrl-0 = <&pinctrl_gpio_led_2>; |
| 16 | |
| 17 | status { |
| 18 | gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; |
| 19 | }; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | &gpmi { |
| 24 | pinctrl-names = "default"; |
| 25 | pinctrl-0 = <&pinctrl_gpmi_nand>; |
| 26 | status = "okay"; |
| 27 | }; |
| 28 | |
| 29 | &iomuxc { |
| 30 | pinctrl_gpmi_nand: gpminandgrp { |
| 31 | fsl,pins = < |
| 32 | MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 |
| 33 | MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 |
| 34 | MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 |
| 35 | MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 |
| 36 | MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 |
| 37 | MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 |
| 38 | MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 |
| 39 | MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 |
| 40 | MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 |
| 41 | MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 |
| 42 | MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 |
| 43 | MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 |
| 44 | MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 |
| 45 | MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 |
| 46 | MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 |
| 47 | MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 |
| 48 | >; |
| 49 | }; |
| 50 | |
| 51 | pinctrl_gpio_led_2: gpioled2grp { |
| 52 | fsl,pins = < |
| 53 | MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 |
| 54 | >; |
| 55 | }; |
| 56 | }; |