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git01.mediatek.com / filogic / uboot / 5d4bcee23394daa20cf4c9f9406989e0ee554112 / . / arch / arm / dts / imx6qdl-mba6b.dtsi
blob: 7d1cd7454c7f5b5033d7d3856dff4ff284fcdfba [file] [log] [blame]
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2013 Sascha Hauer, Pengutronix
4 *
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 */
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]8
9&fec {
10 pinctrl-names = "default";
11 pinctrl-0 = <&pinctrl_enet>;
12};
13
14&i2c1 {
15 clock-frequency = <100000>;
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame^]16 pinctrl-names = "default", "gpio";
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]17 pinctrl-0 = <&pinctrl_i2c1>;
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame^]18 pinctrl-1 = <&pinctrl_i2c1_recovery>;
19 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
20 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]21 status = "okay";
22};
23
24&i2c3 {
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame^]25 lm75: temperature-sensor@49 {
26 compatible = "national,lm75";
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]27 reg = <0x49>;
28 };
29
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame^]30 m24c64_57: eeprom@57 {
31 compatible = "atmel,24c64";
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]32 reg = <0x57>;
33 pagesize = <32>;
34 };
35
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame^]36 rtc0: rtc@68 {
37 compatible = "dallas,ds1339";
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]38 reg = <0x68>;
39 };
40};
41
42&iomuxc {
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame^]43 pinctrl_i2c1: i2c1grp {
44 fsl,pins = <
45 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
46 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
47 >;
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]48 };
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]49};