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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warren23d7fe92012-12-11 13:34:18 +00002/*
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warren23d7fe92012-12-11 13:34:18 +00005 */
6
Tom Warrendf450952013-02-26 12:18:48 +00007#ifndef _TEGRA_COMMON_H_
8#define _TEGRA_COMMON_H_
Alexey Brodkin267d8e22014-02-26 17:47:58 +04009#include <linux/sizes.h>
Tom Warren23d7fe92012-12-11 13:34:18 +000010#include <linux/stringify.h>
11
12/*
13 * High Level Configuration Options
14 */
Tom Warren23d7fe92012-12-11 13:34:18 +000015
Tom Warren23d7fe92012-12-11 13:34:18 +000016#include <asm/arch/tegra.h> /* get chip and board defs */
17
Thierry Reding26748712015-07-28 11:35:54 +020018/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
19#ifndef CONFIG_ARM64
Rob Herring741a0bd2013-10-04 10:22:47 -050020#define CONFIG_SYS_TIMER_RATE 1000000
21#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
Thierry Reding26748712015-07-28 11:35:54 +020022#endif
Rob Herring741a0bd2013-10-04 10:22:47 -050023
Tom Warren23d7fe92012-12-11 13:34:18 +000024/* Environment */
Tom Warren23d7fe92012-12-11 13:34:18 +000025
26/*
Tom Warrendf450952013-02-26 12:18:48 +000027 * NS16550 Configuration
Tom Warren23d7fe92012-12-11 13:34:18 +000028 */
Thomas Choue3b90262015-11-19 21:48:11 +080029#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Tom Warren23d7fe92012-12-11 13:34:18 +000030
31/*
Stephen Warren2c0ea602014-04-18 10:56:11 -060032 * Common HW configuration.
33 * If this varies between SoCs later, move to tegraNN-common.h
34 * Note: This is number of devices, not max device ID.
35 */
36#define CONFIG_SYS_MMC_MAX_DEVICE 4
37
Tom Warren23d7fe92012-12-11 13:34:18 +000038/*
Tom Warren23d7fe92012-12-11 13:34:18 +000039 * Increasing the size of the IO buffer as default nfsargs size is more
40 * than 256 and so it is not possible to edit it
41 */
Bryan Wub644fad2016-09-01 23:49:57 +000042#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
Tom Warren23d7fe92012-12-11 13:34:18 +000043/* Print Buffer Size */
Bryan Wub644fad2016-09-01 23:49:57 +000044#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
45
Tom Warren23d7fe92012-12-11 13:34:18 +000046/* Boot Argument Buffer Size */
47#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
48
Peter Robinson637ac012020-04-02 00:28:54 +010049#ifdef CONFIG_ARM64
50#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
51#else
52#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
53#endif
54
Tom Warren23d7fe92012-12-11 13:34:18 +000055/*-----------------------------------------------------------------------
56 * Physical Memory Map
57 */
Tom Warren23d7fe92012-12-11 13:34:18 +000058#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
59#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
60
Tom Warren23d7fe92012-12-11 13:34:18 +000061#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
62
63#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
64
Stephen Warrenf599a032017-12-19 18:30:37 -070065#ifndef CONFIG_ARM64
Tom Warren23d7fe92012-12-11 13:34:18 +000066#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
67#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
68#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
69 CONFIG_SYS_INIT_RAM_SIZE - \
70 GENERATED_GBL_DATA_SIZE)
Stephen Warrenf599a032017-12-19 18:30:37 -070071#endif
Tom Warren23d7fe92012-12-11 13:34:18 +000072
Stephen Warrenef2a1152017-12-19 18:30:35 -070073#ifndef CONFIG_ARM64
Tom Warren23d7fe92012-12-11 13:34:18 +000074/* Defines for SPL */
Albert ARIBAUDe916e052013-04-12 05:14:30 +000075#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
Tom Warren23d7fe92012-12-11 13:34:18 +000076 CONFIG_SPL_TEXT_BASE)
77#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
Stephen Warrenef2a1152017-12-19 18:30:35 -070078#endif
Tom Warren23d7fe92012-12-11 13:34:18 +000079
Tom Warren23d7fe92012-12-11 13:34:18 +000080#endif /* _TEGRA_COMMON_H_ */