blob: 199ec4a31098f771830b44932723eb2f13bd834d [file] [log] [blame]
Chris Brandt1f3b6672017-08-23 14:53:59 -05001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017 Renesas Electronics
4 * Copyright (C) Chris Brandt
5 */
6
7#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07008#include <cpu_func.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
Chris Brandt1f3b6672017-08-23 14:53:59 -050011#include <asm/io.h>
12#include <asm/arch/sys_proto.h>
13
14#define RZA1_WDT_BASE 0xfcfe0000
15#define WTCSR 0x00
16#define WTCNT 0x02
17#define WRCSR 0x04
18
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_init(void)
22{
23 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
24
25 return 0;
26}
27
28int dram_init(void)
29{
30 if (fdtdec_setup_mem_size_base() != 0)
31 return -EINVAL;
32
33 return 0;
34}
35
36int dram_init_banksize(void)
37{
38 fdtdec_setup_memory_banksize();
39
40 return 0;
41}
42
Harald Seiler6f14d5f2020-12-15 16:47:52 +010043void reset_cpu(void)
Chris Brandt1f3b6672017-08-23 14:53:59 -050044{
45 /* Dummy read (must read WRCSR:WOVF at least once before clearing) */
46 readb(RZA1_WDT_BASE + WRCSR);
47
48 writew(0xa500, RZA1_WDT_BASE + WRCSR);
49 writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
50 writew(0x5a00, RZA1_WDT_BASE + WTCNT);
51 writew(0xa578, RZA1_WDT_BASE + WTCSR);
52
53 for (;;)
54 asm volatile("wfi");
55}